Removed the remnants of the attempt at an ARM port, because it had

bit-rotted badly and was clogging up the code.

I put the useful remnants in docs/porting-to-ARM in case anyone ever
wants to try porting to ARM again.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4092 a5019735-40e9-0310-863c-91ae7b9d1cf9

2 files changed, 0 insertions, 48 deletions

diff --git a/cachegrind/cg-arm.c b/cachegrind/cg-arm.c
deleted file mode 100644
index 04ad82b8..00000000
--- a/cachegrind/cg-arm.c
+++ /dev/null
@@ -1,48 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- ARM-specific definitions.                           cg-arm.c ---*/
-/*--------------------------------------------------------------------*/
-
-/*
-   This file is part of Cachegrind, a Valgrind tool for cache
-   profiling programs.
-
-   Copyright (C) 2002-2005 Nicholas Nethercote
-      njn@valgrind.org
-
-   This program is free software; you can redistribute it and/or
-   modify it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-   02111-1307, USA.
-
-   The GNU General Public License is contained in the file COPYING.
-*/
-
-#include "cg_arch.h"
-
-void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
-                           Bool all_caches_clo_defined)
-{
-   // XXX: I1 and D1 are vaguely plausible, although they could really be
-   // anything.  However, most (all?) ARMs don't have an L2 cache.  But
-   // Cachegrind assumes the presence of an L2 cache... so we just copy the
-   // x86 defaults.  Urk.
-   *I1c = (cache_t) {   4096, 2, 32 };
-   *D1c = (cache_t) {   4096, 2, 32 };
-   *L2c = (cache_t) { 262144, 8, 64 };
-}
-
-/*--------------------------------------------------------------------*/
-/*--- end                                                          ---*/
-/*--------------------------------------------------------------------*/
-
diff --git a/cachegrind/tests/arm/Makefile.am b/cachegrind/tests/arm/Makefile.am
deleted file mode 100644
index e69de29b..00000000
--- a/cachegrind/tests/arm/Makefile.am
+++ /dev/null