diff options
| author | florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2011-08-19 19:41:57 +0000 |
|---|---|---|
| committer | florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2011-08-19 19:41:57 +0000 |
| commit | 603896cefec5110be02227c80f7032a899f5163c (patch) | |
| tree | 685c9be2e76a0b3de20d38e211d40375b8546212 | |
| parent | c542ba4a7e3514f665e1848644017d180d3c9331 (diff) | |
Add more info about cache sizes.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11996 a5019735-40e9-0310-863c-91ae7b9d1cf9
| -rw-r--r-- | cachegrind/cg-s390x.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/cachegrind/cg-s390x.c b/cachegrind/cg-s390x.c index 905a15f5..824a0d7f 100644 --- a/cachegrind/cg-s390x.c +++ b/cachegrind/cg-s390x.c @@ -1,3 +1,4 @@ +/* -*- mode: C; c-basic-offset: 3; -*- */ /*--------------------------------------------------------------------*/ /*--- s390x-specific definitions. cg-s390x.c ---*/ @@ -41,6 +42,62 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, Bool all_caches_clo_defined) { + // z900 + // + // Source: + // The microarchitecture of the IBM eServer z900 processor + // IBM Journal of Research and Development + // Volume 46, Number 4/5, pp 381-395, July/September 2002 + // + // Split L1 I/D cache + // Size: 256 kB each + // Line size: 256 bytes + // 4-way set associative + // L2 cache: 16 MB x 2 (16 MB per 10 CPs) (Charles Webb) + + // z800 + // + // Source: Charles Webb from IBM + // + // Split L1 I/D cache + // Size: 256 kB each + // Line size: 256 bytes + // 4-way set associative + // L2 cache: 16 MB (or half that size) + + // z990 + // + // The IBM eServer z990 microprocessor + // IBM Journal of Research and Development + // Volume 48, Number 3/4, pp 295-309, May/July 2004 + // + // Split L1 I/D cache + // Size: 256 kB each + // Line size: 256 bytes + // 4-way set associative + // L2 cache: 32 MB x 4 (32 MB per book/node) (Charles Webb) + + // z890 + // + // Source: Charles Webb from IBM + // + // Split L1 I/D cache + // Size: 256 kB each + // Line size: 256 bytes + // 4-way set associative + // L2 cache: 32 MB (or half that size) + + // z9 + // + // Source: Charles Webb from IBM + // + // Split L1 I/D cache + // Size: 256 kB each + // Line size: 256 bytes + // 4-way set associative + // L2 cache: 40 MB x 4 (40 MB per book/node) + + // Set caches to z10 default. // See IBM Journal of Research and Development // Issue Date: Jan. 2009 |