path: root/r600_batch.c

/*
 * Copyright © 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 */
#include "radeon_device.h"
#include "r600_atom.h"
#include "r600d.h"

/* state creation functions prototype */
int r600_cb_emit(struct radeon_device *rdev, struct radeon_atom *atom, void *data, struct radeon_ib *ib);
int r600_cb_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_cb_cntl_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_pa_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_vport_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_blend_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_constants_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_db_emit(struct radeon_device *rdev, struct radeon_atom *atom, void *data, struct radeon_ib *ib);
int r600_db_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_db_cntl_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_vs_shader_emit(struct radeon_device *rdev, struct radeon_atom *atom, void *data, struct radeon_ib *ib);
int r600_vs_shader_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);
int r600_ps_shader_emit(struct radeon_device *rdev, struct radeon_atom *atom, void *data, struct radeon_ib *ib);
int r600_ps_shader_create(struct radeon_device *rdev, struct radeon_atom *atom, void *data);

/*
 * helpers functions
 */
static void r600_emit_flush(struct radeon_device *rdev,
				struct radeon_ib *ib,
				struct radeon_bo *bo,
				u32 flags)
{
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SURFACE_SYNC, 3);
	ib->ptr[ib->cpkts++] = flags;
	ib->ptr[ib->cpkts++] = radeon_bo_size(bo) >> 8;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x0000000A;
	ib->ptr[ib->cpkts++] = PKT3(PKT3_NOP, 0);
	ib->ptr[ib->cpkts++] = radeon_ib_reloc(ib, bo, RADEON_GEM_DOMAIN_VRAM |
						RADEON_GEM_DOMAIN_GTT);
}

static void r600_emit_resources(struct radeon_device *rdev,
				struct radeon_ib *ib,
				struct radeon_bo *bo,
				u32 dw0, u32 dw1, u32 dw2, u32 dw3,
				u32 dw4, u32 dw5, u32 dw6, u32 dw7)
{
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SURFACE_SYNC, 3);
	ib->ptr[ib->cpkts++] = 0x01000000;
	ib->ptr[ib->cpkts++] = radeon_bo_size(bo) >> 8;
	ib->ptr[ib->cpkts++] = 0x00000000;
	ib->ptr[ib->cpkts++] = 0x0000000A;
	ib->ptr[ib->cpkts++] = PKT3(PKT3_NOP, 0);
	ib->ptr[ib->cpkts++] = radeon_ib_reloc(ib, bo, RADEON_GEM_DOMAIN_VRAM |
						RADEON_GEM_DOMAIN_GTT);
	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_RESOURCE, 7);
	ib->ptr[ib->cpkts++] = dw0;
	ib->ptr[ib->cpkts++] = dw1;
	ib->ptr[ib->cpkts++] = dw2;
	ib->ptr[ib->cpkts++] = dw3;
	ib->ptr[ib->cpkts++] = dw4;
	ib->ptr[ib->cpkts++] = dw5;
	ib->ptr[ib->cpkts++] = dw6;
	ib->ptr[ib->cpkts++] = dw7;
	ib->ptr[ib->cpkts++] = PKT3(PKT3_NOP, 0);
	ib->ptr[ib->cpkts++] = radeon_ib_reloc(ib, bo, RADEON_GEM_DOMAIN_VRAM |
						RADEON_GEM_DOMAIN_GTT);
}

/*
 * r600_batch
 */
static int r600_batch_alloc(struct r600_batch **batch)
{
	struct r600_batch *rbatch;

	*batch = NULL;
	rbatch = malloc(sizeof(*rbatch));
	if (rbatch == NULL)
		return -ENOMEM;
	INIT_LIST_HEAD(&rbatch->list);
	INIT_LIST_HEAD(&rbatch->pre_flushes);
	INIT_LIST_HEAD(&rbatch->post_flushes);
	rbatch->nemit_atoms = 0;
	rbatch->shaders_idx = 0;
	rbatch->nfs_resources = 0;
	*batch = rbatch;
	return 0;
}

/*
 * r600_batches
 */
static int r600_batches_fs_resource_is_present(struct radeon_device *rdev,
						struct r600_batches *batches,
						struct drm_r600_vs_buffer *buffer)
{
	int i;

	for (i = 0; i < batches->nfs_resources; i++) {
		if (!memcmp(&batches->fs_resource[i], buffer, sizeof(struct drm_r600_vs_buffer))) {
			buffer->resource_id = i;
			return 1;
		}
	}
	return 0;
}

static int r600_batches_fs_resource_add(struct radeon_device *rdev,
						struct r600_batches *batches,
						struct drm_r600_vs_buffer *buffer)
{
	int i = batches->nfs_resources++;

	buffer->resource_id = i;
	memcpy(&batches->fs_resource[i].drm, buffer, sizeof(struct drm_r600_vs_buffer));
	batches->fs_resource[i].bo = radeon_bo_lookup(rdev, buffer->handle);
	if (batches->fs_resource[i].bo == NULL)
		return -EINVAL;
	return 0;
}

static void r600_batches_clear_locked(struct radeon_device *rdev, struct r600_batches *batches)
{
	struct r600_batch *batch, *n;
	int i;

	list_for_each_entry_safe(batch, n, &batches->batches, list) {
		for (i = 0; i < R600_BATCH_NATOMS; i++) {
			if (batch->atoms[i])
				radeon_atom_put(batch->atoms[i]);
		}
		radeon_atom_flush_cleanup(&batch->pre_flushes);
		radeon_atom_flush_cleanup(&batch->post_flushes);
		list_del(&batch->list);
		radeon_bo_unmap(batch->shaders);
		radeon_bo_unref(batch->shaders);
		free(batch);
	}
	INIT_LIST_HEAD(&batches->batches);
	for (i = 0; i < batches->nfs_resources; i++) {
		radeon_bo_unref(batches->fs_resource[i].bo);
	}
	batches->nfs_resources = 0;
	r700_batches_states_default(rdev, batches);
	batches->npkts = batches->ib->cpkts;
}

static int r600_batches_flush_locked(struct radeon_device *rdev, struct r600_batches *batches)
{
	struct r600_batch *batch;
	struct radeon_atom_flush *flush;
	int r, i;

	for (i = 0; i < batches->nfs_resources; i++) {
		r600_emit_resources(rdev, batches->ib, batches->fs_resource[i].bo,
					(batches->fs_resource[i].drm.resource_id + 160) * 7,
					batches->fs_resource[i].drm.sq_vtx_constant_word0,
					radeon_bo_size(batches->fs_resource[i].bo) -
					batches->fs_resource[i].drm.sq_vtx_constant_word0,
					batches->fs_resource[i].drm.sq_vtx_constant_word2,
					batches->fs_resource[i].drm.sq_vtx_constant_word3,
					0, 0, 0xC0000000);
	}
	list_for_each_entry(batch, &batches->batches, list) {
		list_for_each_entry(flush, &batch->pre_flushes, list) {
			r600_emit_flush(rdev, batches->ib, flush->bo, flush->flags);
		}
		/* FIXME shader flush should be conditional */
		r600_emit_flush(rdev, batches->ib, batch->shaders, 0x08000000);
		for (i = 0; i < batch->nemit_atoms; i++) {
			r = batch->emit_atoms[i]->emit(rdev, batch->emit_atoms[i], batch, batches->ib);
			if (r)
				goto out_err;
		}
		/* flush + wait until */
		batches->ib->ptr[batches->ib->cpkts++] = PKT3(PKT3_EVENT_WRITE, 0);
		batches->ib->ptr[batches->ib->cpkts++] = 0x00000016;
		batches->ib->ptr[batches->ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
		batches->ib->ptr[batches->ib->cpkts++] = 0x00000010;
		batches->ib->ptr[batches->ib->cpkts++] = 0x00028000;
		list_for_each_entry(flush, &batch->post_flushes, list) {
			r600_emit_flush(rdev, batches->ib, flush->bo, flush->flags);
		}
	}
	r = radeon_ib_schedule(rdev, batches->ib);
out_err:
	/* FIXME helper function */
	batches->ib->cpkts = 0;
	batches->ib->nrelocs = 0;
	r600_batches_clear_locked(rdev, batches);
	return r;
}

int r600_batches_queue(struct radeon_device *rdev, struct drm_r600_batch *batch)
{
	struct r600_batch *rbatch;
	struct r600_batches *batches =  &rdev->batches;
	int r, i, j;

	r = r600_batch_alloc(&rbatch);
	if (r)
		return r;
	memcpy(&rbatch->inputs, &batch->inputs, sizeof(struct r600_vs_input));
	i = 0;
	if (batch->blend == NULL || batch->cb_cntl == NULL ||
		batch->pa == NULL || batch->vport == NULL ||
		batch->cb == NULL || batch->db_cntl == NULL ||
		batch->vs_shader == NULL || batch->ps_shader == NULL) {
		free(rbatch);
		fprintf(stderr, "invalid batch\n");
		return -EINVAL;
	}
	rbatch->shaders = radeon_bo_open(rdev->bom, 0, 4096 * 16, 0, RADEON_GEM_DOMAIN_GTT, 0);
	if (rbatch->shaders == NULL) {
		free(rbatch);
		fprintf(stderr, "can't create buffer for shaders\n");
		return -ENOMEM;
	}
	r = radeon_bo_map(rbatch->shaders, 1);
	if (r) {
		free(rbatch);
		fprintf(stderr, "can't map buffer for shaders\n");
		return r;
	}
	rbatch->atoms[i++] = batch->blend; kref_get(&batch->blend->kref);
	rbatch->atoms[i++] = batch->cb_cntl; kref_get(&batch->cb_cntl->kref);
	rbatch->atoms[i++] = batch->pa; kref_get(&batch->pa->kref);
	rbatch->atoms[i++] = batch->vport; kref_get(&batch->vport->kref);
	rbatch->atoms[i++] = batch->vs_shader; kref_get(&batch->vs_shader->kref);
	rbatch->atoms[i++] = batch->ps_shader; kref_get(&batch->ps_shader->kref);
	rbatch->atoms[i++] = batch->db_cntl; kref_get(&batch->db_cntl->kref);
	rbatch->atoms[i++] = batch->vs_constants;
	if (batch->vs_constants)
		kref_get(&batch->vs_constants->kref);
	rbatch->atoms[i++] = batch->ps_constants;
	if (batch->ps_constants)
		kref_get(&batch->ps_constants->kref);
	rbatch->atoms[i++] = batch->db;
	if (batch->db)
		kref_get(&batch->db->kref);
	rbatch->atoms[i++] = batch->cb; kref_get(&batch->cb->kref);
reprocess:
	radeon_atom_flush_cleanup(&rbatch->pre_flushes);
	radeon_atom_flush_cleanup(&rbatch->post_flushes);
	rbatch->nflushes = 0;
	rbatch->npkts = 0;
	/* flush + wait until = 5dw */
	rbatch->npkts += 5;
	for (i = 0; i < rbatch->inputs.drm.nbuffers; i++) {
		if (!r600_batches_fs_resource_is_present(rdev, batches, &rbatch->inputs.drm.buffers[i])) {
			rbatch->nfs_resources += 1;
			rbatch->inputs.drm.buffers[i].resource_id = -1;
		}
	}
	rbatch->npkts += rbatch->nfs_resources * 18;
	for (i = 0; i < R600_BATCH_NATOMS; i++) {
		if (rbatch->atoms[i]) {
			for (j = 0; j < rbatch->atoms[i]->nbo; j++) {
				r = radeon_atom_flush_add(&rbatch->pre_flushes, rbatch->atoms[i]->bo[j],  rbatch->atoms[i]->flags[j]);
				if (r < 0)
					goto out_err;
			}
			rbatch->nflushes += rbatch->atoms[i]->nbo;
			rbatch->emit_atoms[rbatch->nemit_atoms++] = rbatch->atoms[i];
		}
	}
	/* add flush */
	rbatch->npkts += rbatch->nflushes * 7;
	/* FIXME shader flush should be conditional only if we change shaders */
	rbatch->npkts += 7;
	/* if batch is bigger than ib size it's an invalid one, this should
	 * not happen
	 */
	if (rbatch->npkts > batches->ib->length_dw) {
		fprintf(stderr, "single batch to big (%d) to fit into ib (%d)\n",
			rbatch->npkts, batches->ib->length_dw);
		goto out_err;
	}
	/* flush or not ? */
	if (batches->npkts + rbatch->npkts > batches->ib->length_dw) {
		r = r600_batches_flush_locked(rdev, batches);
		if (r)
			goto out_err;
		goto reprocess;
	}
	/* batch is queued */
	for (i = 0; i < R600_BATCH_NATOMS; i++) {
		if (rbatch->atoms[i]) {
			batches->last_id[i] = rbatch->atoms[i]->id;
		}
	}
	radeon_device_set_bo_list(rdev, rbatch->inputs.nbo, rbatch->inputs.bo);
	for (i = 0; i < rbatch->inputs.drm.nbuffers; i++) {
		if (rbatch->inputs.drm.buffers[i].resource_id == -1) {
			r = r600_batches_fs_resource_add(rdev, batches, &rbatch->inputs.drm.buffers[i]);
			if (r)
				goto out_err;
		}
	}
	batches->npkts += rbatch->npkts;
	list_add_tail(&rbatch->list, &batches->batches);
	return 0;
out_err:
	for (i = 0; i < R600_BATCH_NATOMS; i++) {
		if (rbatch->atoms[i])
			radeon_atom_put(rbatch->atoms[i]);
	}
	radeon_bo_unmap(rbatch->shaders);
	radeon_bo_unref(rbatch->shaders);
	free(rbatch);
	return r;
}

static int r600_batches_init(struct radeon_device *rdev, struct r600_batches *batches)
{
	int r;

	memset(batches, 0 , sizeof(struct r600_batches));
	INIT_LIST_HEAD(&batches->batches);
	r = radeon_ib_get(rdev, &batches->ib);
	if (r)
		return r;
	r700_batches_states_default(rdev, batches);
	batches->npkts = batches->ib->cpkts;
	return 0;
}

static void r600_batches_cleanup_locked(struct radeon_device *rdev, struct r600_batches *batches)
{
	r600_batches_clear_locked(rdev, batches);
	radeon_ib_free(batches->ib);
	batches->ib = NULL;
}

int r600_batches_flush(struct radeon_device *rdev)
{
	int r;

	r = r600_batches_flush_locked(rdev, &rdev->batches);
	return r;
}

int r600_atoms_init(struct radeon_device *rdev)
{
	rdev->npipes = 2;
	rdev->nbanks = 4;
	rdev->group_bytes = 256;
	return r600_batches_init(rdev, &rdev->batches);
}

void r600_atoms_release(struct radeon_device *rdev)
{
	r600_batches_cleanup_locked(rdev, &rdev->batches);
}

/*
 * r600 atom core functions
 */
static struct r600_atom_funcs _r600_atom_funcs[] = {
	{0, 0, NULL, NULL},
	{R600_ATOM_CB, sizeof(struct drm_r600_cb),
		&r600_cb_create, &r600_cb_emit},
	{R600_ATOM_PA, sizeof(struct drm_r600_pa),
		&r600_pa_create, &radeon_atom_emit_default},
	{R600_ATOM_CB_CNTL, sizeof(struct drm_r600_cb_cntl),
		&r600_cb_cntl_create, &radeon_atom_emit_default},
	{R600_ATOM_VPORT, sizeof(struct drm_r600_vport),
		&r600_vport_create, &radeon_atom_emit_default},
	{R600_ATOM_BLEND, sizeof(struct drm_r600_blend),
		&r600_blend_create, &radeon_atom_emit_default},
	{R600_ATOM_CONSTANTS, sizeof(struct drm_r600_constants),
		&r600_constants_create, &radeon_atom_emit_default},
	{R600_ATOM_DB, sizeof(struct drm_r600_db),
		&r600_db_create, &r600_db_emit},
	{R600_ATOM_DB_CNTL, sizeof(struct drm_r600_db_cntl),
		&r600_db_cntl_create, &radeon_atom_emit_default},
	{R600_ATOM_VS_SHADER, sizeof(struct drm_r600_vs_shader),
		&r600_vs_shader_create, &r600_vs_shader_emit},
	{R600_ATOM_PS_SHADER, sizeof(struct drm_r600_ps_shader),
		&r600_ps_shader_create, &r600_ps_shader_emit},
};


struct radeon_atom *r600_atom_create(struct radeon_device *rdev, struct drm_radeon_atom *patom)
{
	struct radeon_atom *atom;
	struct r600_state_container *cont;
	int r;

	if (!patom->type || patom->type >= R600_BATCH_NATOMS) {
		fprintf(stderr, "%s %d invalid atom type %d\n", __func__, __LINE__);
		return NULL;
	}
	if (_r600_atom_funcs[patom->type].type != patom->type) {
		fprintf(stderr, "%s %d mismatch for type %d have %d\n",
			__func__, __LINE__, _r600_atom_funcs[patom->type].type, patom->type);
		return NULL;
	}
	cont = patom->data;
	radeon_device_set_bo_list(rdev, cont->nbo, cont->bo);
	/* create the atom */
	atom = malloc(sizeof(struct radeon_atom));
	if (atom == NULL)
		return NULL;
	memset(atom, 0, sizeof(struct radeon_atom));
	INIT_LIST_HEAD(&atom->list);
	kref_init(&atom->kref);
	atom->emit = _r600_atom_funcs[patom->type].emit;
	atom->nflushes = 0;
	atom->id = crc_64(cont->data, _r600_atom_funcs[patom->type].size);
	atom->type = patom->type;
	r = _r600_atom_funcs[patom->type].create(rdev, atom, cont->data);
	if (r) {
		radeon_atom_put(atom);
		return NULL;
	}
	return atom;
}