cleanup and default states

RENDERING LIKELY BROKEN

7 files changed, 114 insertions, 162 deletions

diff --git a/r600_atom.c b/r600_atom.c
index 09be7f9..5664942 100644
--- a/r600_atom.c
+++ b/r600_atom.c
@@ -82,10 +82,9 @@ static void r600_emit_resources(struct radeon_device *rdev,
  */
 struct r600_cb {
 	struct radeon_atom	atom;
-	u32			pkts[512];
+	u32			pkts[128];
 	u32			placements[2];
 	struct radeon_bo	*bo;
-	struct radeon_bo	*vbo1;
 	struct r600_atoms	*atoms;
 };
 
@@ -99,8 +98,6 @@ static void r600_cb_release(struct kref *kref)
 	mutex_unlock(&cb->atoms->mutex);
 	if (cb->bo)
 		radeon_bo_unref(cb->bo);
-	if (cb->vbo1)
-		radeon_bo_unref(cb->vbo1);
 	kfree(cb);
 }
 
@@ -115,10 +112,6 @@ static int r600_cb_emit(struct radeon_device *rdev,
 	cb->pkts[16] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
 	cb->pkts[21] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
 	cb->pkts[26] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
-	cb->pkts[96] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[107] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[114] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[125] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
 	r = radeon_ib_copy(ib, cb->pkts, atom->npkts);
 	return r;
 }
@@ -143,8 +136,6 @@ static int r600_cb_process(struct radeon_device *rdev,
 
 /* FIXME delete */
 void r600_tflat(struct radeon_atom *atom);
-int r600_tflat_init(struct radeon *radeon, struct r600_cb *cb);
-
 static int r600_cb_create(struct radeon_device *rdev,
 				struct r600_atoms *atoms,
 				struct drm_radeon_atom *patom,
@@ -173,9 +164,6 @@ static int r600_cb_create(struct radeon_device *rdev,
 	/* take a references on the bo */
 	cb->bo = pcb.bo;
 	radeon_bo_ref(cb->bo);
-	r = r600_tflat_init(rdev->radeon, cb);
-	if (r)
-		goto out_err;
 	/* check cb configuration */
 	switch (G_0280A0_FORMAT(pcb.color_info)) {
 	case V_0280A0_COLOR_8:
@@ -1494,14 +1482,12 @@ static int r600_vs_shader_emit(struct radeon_device *rdev,
 				&batch->inputs, &vs_shader->vs);
 	if (r)
 		return r;
-printf("FS at %d\n", batch->shaders_idx);
 	vs_shader->pkts[2] = batch->shaders_idx >> 6;
 	vs_shader->pkts[4] = radeon_ib_reloc(ib, batch->shaders, RADEON_GEM_DOMAIN_GTT);
 	batch->shaders_idx += (ndwords + 63) & 0xFFFFFFC0;
 	memcpy(&opcodes[batch->shaders_idx], vs_shader->vs.opcodes, vs_shader->vs.ndwords * 4);
 	vs_shader->pkts[13] = batch->shaders_idx >> 6;
 	vs_shader->pkts[15] = radeon_ib_reloc(ib, batch->shaders, RADEON_GEM_DOMAIN_GTT);
-printf("VS at %d\n", batch->shaders_idx);
 	batch->shaders_idx += (vs_shader->vs.ndwords + 63) & 0xFFFFFFC0;
 	r = radeon_ib_copy(ib, vs_shader->pkts, atom->npkts);
 	return r;
@@ -1883,11 +1869,12 @@ static void r600_batches_clear_locked(struct radeon_device *rdev, struct r600_ba
 		kfree(batch);
 	}
 	INIT_LIST_HEAD(&batches->batches);
-	batches->npkts = 0;
 	for (i = 0; i < batches->nfs_resources; i++) {
 		radeon_bo_unref(batches->fs_resource[i].bo);
 	}
 	batches->nfs_resources = 0;
+	r700_batches_states_default(rdev, batches);
+	batches->npkts = batches->ib->cpkts;
 }
 
 static int r600_batches_flush_locked(struct radeon_device *rdev, struct r600_batches *batches)
@@ -1929,10 +1916,10 @@ static int r600_batches_flush_locked(struct radeon_device *rdev, struct r600_bat
 	}
 	r = radeon_ib_schedule(rdev, batches->ib);
 out_err:
-	r600_batches_clear_locked(rdev, batches);
 	/* FIXME helper function */
 	batches->ib->cpkts = 0;
 	batches->ib->nrelocs = 0;
+	r600_batches_clear_locked(rdev, batches);
 	return r;
 }
 
@@ -2108,7 +2095,11 @@ static int r600_batches_init(struct radeon_device *rdev, struct r600_batches *ba
 	memset(batches, 0 , sizeof(struct r600_batches));
 	INIT_LIST_HEAD(&batches->batches);
 	r = radeon_ib_get(rdev, &batches->ib);
-	return r;
+	if (r)
+		return r;
+	r700_batches_states_default(rdev, batches);
+	batches->npkts = batches->ib->cpkts;
+	return 0;
 }
 
 static void r600_batches_cleanup_locked(struct radeon_device *rdev, struct r600_batches *batches)
@@ -2179,14 +2170,6 @@ void r600_atoms_release(struct radeon_device *rdev, struct r600_atoms *atoms)
 	} while (0)
 void r600_tflat(struct radeon_atom *atom)
 {
-    WPKT(PKT3(PKT3_CONTEXT_CONTROL, 1));
-    WPKT(0x80000000);
-    WPKT(0x80000000);
-    WPKT(PKT3(PKT3_EVENT_WRITE, 0));
-    WPKT(0x00000016);
-    WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
-    WPKT(0x00000010);
-    WPKT(0x00028000);
     WPKT(PKT3(PKT3_SET_CONFIG_REG, 6));
     WPKT(0x00000300);
     WPKT(0x0000000D);
@@ -2195,29 +2178,6 @@ void r600_tflat(struct radeon_atom *atom)
     WPKT(0x00003CBC);
     WPKT(0x00800080);
     WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
-    WPKT(0x000005C5);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
-    WPKT(0x00000363);
-    WPKT(0x00004000);
-    WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
-    WPKT(0x0000060C);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
-    WPKT(0x0000060E);
-    WPKT(0x00420204);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 9));
-    WPKT(0x0000022A);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
     WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
     WPKT(0x0000008C);
     WPKT(0xAAAAAAAA);
@@ -2227,53 +2187,6 @@ void r600_tflat(struct radeon_atom *atom)
     WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
     WPKT(0x00000308);
     WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000001E8);
-    WPKT(0x00000003);
-    WPKT(PKT3(PKT3_SET_LOOP_CONST, 1));
-    WPKT(0x00000020);
-    WPKT(0x0100000F);
-    WPKT(PKT3(PKT3_SET_LOOP_CONST, 1));
-    WPKT(0x00000000);
-    WPKT(0x01000FFF);
-    WPKT(PKT3(PKT3_SET_CTL_CONST, 1));
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CTL_CONST, 1));
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SURFACE_SYNC, 3));
-    WPKT(0x01000000);
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(0x0000000A);
-    WPKT_RELOC("vbo1");
-    WPKT(PKT3(PKT3_SET_RESOURCE, 7));
-    WPKT(0x00000460);
-    WPKT(0x00000000);
-    WPKT(0x0000006F);
-    WPKT(0x03001C00);
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0xC0000000);
-    WPKT_RELOC("vbo1");
-    WPKT(PKT3(PKT3_SURFACE_SYNC, 3));
-    WPKT(0x01000000);
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(0x0000000A);
-    WPKT_RELOC("vbo1");
-    WPKT(PKT3(PKT3_SET_RESOURCE, 7));
-    WPKT(0x00000475);
-    WPKT(0x0000000C);
-    WPKT(0x0000006F);
-    WPKT(0x02301C00);
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0xC0000000);
-    WPKT_RELOC("vbo1");
     WPKT(PKT3(PKT3_SET_CONTEXT_REG, 2));
     WPKT(0x00000094);
     WPKT(0x80000000);
@@ -2289,34 +2202,3 @@ void r600_tflat(struct radeon_atom *atom)
     WPKT(0x00000004);
     WPKT(0x00000002);
 }
-
-static float rvbo1[32] = {
-    0.000000, 0.000000, -1.000000, 0.500000,
-    0.500000, 0.500000, 0.000000, 250.000000,
-    0.000000, -1.000000, 0.500000, 0.500000,
-    0.500000, 0.000000, 250.000000, 250.000000,
-    -1.000000, 0.500000, 0.500000, 0.500000,
-    0.000000, 0.000000, 250.000000, -1.000000,
-    0.500000, 0.500000, 0.500000, 0.000000,
-    0.000000, 0.000000, 0.000000, 0.000000,
-};
-
-int r600_tflat_init(struct radeon *radeon, struct r600_cb *cb)
-{
-	int r = 0;
-
-	cb->vbo1 = radeon_bo_open(radeon->bom, 0, 4096, 0,
-					RADEON_GEM_DOMAIN_GTT, 0);
-	if (cb->vbo1 == NULL) {
-		fprintf(stderr, "Failed to create vbo1 bo\n");
-		r = -ENOMEM;
-		goto out_err;
-	}
-	memset_bo(cb->vbo1, 0);
-	memcpy_bo(cb->vbo1, (u32*)rvbo1, 32);
-	return 0;
-out_err:
-	if (cb->vbo1)
-		radeon_bo_unref(cb->vbo1);
-	return r;
-}
diff --git a/r600_shader.c b/r600_shader.c
index de22654..ddbcbf9 100644
--- a/r600_shader.c
+++ b/r600_shader.c
@@ -220,7 +220,6 @@ int r600_shader_build_fs(struct radeon_device *rdev,
 				break;
 			}
 		}
-printf("elements %d: gpr %d resource id %d\n", i, gpr, rid);
 		/* if vs has no corresponding input skip the elements */
 		if (gpr == -1)
 			continue;
@@ -230,6 +229,5 @@ printf("elements %d: gpr %d resource id %d\n", i, gpr, rid);
 		bytecode[idx++] = 0xCAFEDEAD;
 	}
 	*ndwords = idx;
-	r600_shader_disassemble(bytecode, idx);
 	return 0;
 }
diff --git a/r600d.h b/r600d.h
index 3d1ffee..0f805a7 100644
--- a/r600d.h
+++ b/r600d.h
@@ -574,5 +574,30 @@
 #define   S_008DFC_ALT_CONST(x)                        (((x) & 0x1) << 20)
 #define   G_008DFC_ALT_CONST(x)                        (((x) >> 20) & 0x1)
 #define   C_008DFC_ALT_CONST                           0xFFEFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
 
 #endif
diff --git a/r700_atom.c b/r700_atom.c
index dde5f93..e747930 100644
--- a/r700_atom.c
+++ b/r700_atom.c
@@ -14,10 +14,76 @@
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
+#include "radeon.h"
 #include "radeon_device.h"
+#include "r600d.h"
 
-/* TODO
- *	convert to radeon_atom_init
- *RENDERING SHOULD WORK & num of bo in gem info should show that we did cleanup
- *	add more state ...
- */
+void r700_batches_states_default(struct radeon_device *rdev, struct r600_batches *batches)
+{
+	struct radeon_ib *ib = batches->ib;
+
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_START_3D_CMDBUF, 0);
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
+	ib->ptr[ib->cpkts++] = 0x80000000;
+	ib->ptr[ib->cpkts++] = 0x80000000;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_EVENT_WRITE, 0);
+	ib->ptr[ib->cpkts++] = 0x00000016;
+	/* R_008040_WAIT_UNTIL */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x00000010;
+	ib->ptr[ib->cpkts++] = S_008040_WAIT_3D_IDLE(1) | S_008040_WAIT_3D_IDLECLEAN(1);
+	/* R_009714_VC_ENHANCE */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x000005C5;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	/* R7xx R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x00000363;
+	ib->ptr[ib->cpkts++] = 0x00004000;
+	/* R_009839_DB_DEBUG */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x0000060C;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	/* R_09838_DB_WATERMARK */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x0000060E;
+	ib->ptr[ib->cpkts++] = 0x00420204;
+	/* R_0288A8_SQ_ESGS_RING_ITEMSIZE
+	 * R_0288AC_SQ_GSVS_RING_ITEMSIZE
+	 * R_0288B0_SQ_ESTMP_RING_ITEMSIZE
+	 * R_0288B4_SQ_GSTMP_RING_ITEMSIZE
+	 * R_0288B8_SQ_VSTMP_RING_ITEMSIZE
+	 * R_0288BC_SQ_PSTMP_RING_ITEMSIZE
+	 * R_0288C0_SQ_FBUF_RING_ITEMSIZE
+	 * R_0288C4_SQ_REDUC_RING_ITEMSIZE
+	 * R_0288C8_SQ_GS_VERT_ITEMSIZE
+	 */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 9);
+	ib->ptr[ib->cpkts++] = 0x0000022A;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	/* R7xx R_0287A0_CB_SHADER_CONTROL */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x000001E8;
+	ib->ptr[ib->cpkts++] = 0x00000003;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_LOOP_CONST, 1);
+	ib->ptr[ib->cpkts++] = 0x00000020;
+	ib->ptr[ib->cpkts++] = 0x0100000F;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_LOOP_CONST, 1);
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x01000FFF;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CTL_CONST, 1);
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CTL_CONST, 1);
+	ib->ptr[ib->cpkts++] = 0x00000001;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+}
diff --git a/radeon_atom.h b/radeon_atom.h
index cdeb2bd..9fa762f 100644
--- a/radeon_atom.h
+++ b/radeon_atom.h
@@ -139,5 +139,6 @@ extern int r600_batches_queue(struct radeon_device *rdev,
 				struct drm_r600_batch *batch);
 extern int r600_batches_flush(struct radeon_device *rdev, struct r600_atoms *atoms);
 /* R700 */
+extern void r700_batches_states_default(struct radeon_device *rdev, struct r600_batches *batches);
 
 #endif
diff --git a/radeon_device.c b/radeon_device.c
index fe7c200..6c8bcdf 100644
--- a/radeon_device.c
+++ b/radeon_device.c
@@ -92,6 +92,11 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 	uint64_t chunk_array[2];
 	int r = 0;
 
+#if 1
+	for (r = 0; r < ib->cpkts; r++) {
+		printf("0x%08X\n", ib->ptr[r]);
+	}
+#endif
 	drmib.num_chunks = 2;
 	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
 	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
@@ -102,7 +107,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 	chunks[1].chunk_data = (uint64_t)(uintptr_t)ib->relocs;
 	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
 	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
-#if 1
+#if 0
 	r = drmCommandWriteRead(rdev->fd, DRM_RADEON_CS, &drmib,
 				sizeof(struct drm_radeon_cs));
 #endif
diff --git a/test.c b/test.c
index a20dadc..78040e1 100644
--- a/test.c
+++ b/test.c
@@ -51,27 +51,7 @@ static u32 vsconstants[16] = {
 	0x00000000, 0x00000000, 0x00000000, 0x3F800000,
 };
 
-#if 0
-static u32 vsshaders[64] = {
-    0x0000001C, 0x81000400, 0x00000005, 0x80000000,
-    0x00000007, 0xA04C0000, 0xC001A03C, 0x94000688,
-    0xC0024000, 0x94200688, 0x900000F8, 0x00A80C90,
-    0x00000000, 0x00000000, 0x00200001, 0x006C2810,
-    0x00A00401, 0x206C2800, 0x01200801, 0x406C2800,
-    0x81A00C01, 0x606C2800, 0x00202001, 0x006C2800,
-    0x00A02401, 0x206C2810, 0x01202801, 0x406C2800,
-    0x81A02C01, 0x606C2800, 0x00204001, 0x006C2800,
-    0x00A04401, 0x206C2800, 0x01204801, 0x406C2810,
-    0x81A04C01, 0x606C2800, 0x00206001, 0x006C2800,
-    0x00A06401, 0x206C2800, 0x01206801, 0x406C2800,
-    0x81A06C01, 0x606C2810, 0x00000002, 0x00940C90,
-    0x00000402, 0x20940C90, 0x00000802, 0x40940C90,
-    0x80000C02, 0x60940C90, 0x00000000, 0x00000000,
-    0x7C000000, 0x1C351001, 0x00080000, 0x0BEADEAF,
-    0x7C000300, 0x18ED1002, 0x00080000, 0x0BEADEAF,
-};
-#else
-static u32 vsshaders[64] = {
+static u32 vsshaders[56] = {
     0x00000000, 0x89800000, 0x00000005, 0x80000000,
     0x00000007, 0xA04C0000, 0xC001A03C, 0x94000688,
     0xC0024000, 0x94200688, 0x900000F8, 0x00A80C90,
@@ -86,10 +66,7 @@ static u32 vsshaders[64] = {
     0x81A06C01, 0x606C2810, 0x00000002, 0x00940C90,
     0x00000402, 0x20940C90, 0x00000802, 0x40940C90,
     0x80000C02, 0x60940C90, 0x00000000, 0x00000000,
-    0x7C000000, 0x1C351001, 0x00080000, 0x0BEADEAF,
-    0x7C000300, 0x18ED1002, 0x00080000, 0x0BEADEAF,
 };
-#endif
 
 static u32 psshaders[20] = {
     0x00000003, 0x80000000, 0x00000005, 0xA00C0000,
@@ -110,7 +87,6 @@ static float rvbo1[32] = {
     0.000000, 0.000000, 0.000000, 0.000000,
 };
 
-void r600_shader_disassemble(u32 *bytecode, u32 ndwords);
 int r600_tri_flat(struct radeon *radeon)
 {
 	struct radeon_device *rdev;
@@ -140,7 +116,6 @@ int r600_tri_flat(struct radeon *radeon)
 	memset_bo(vbo1, 0);
 	memcpy_bo(vbo1, (u32*)rvbo1, 32);
 
-//	r600_shader_disassemble(vsshaders, 64);
 	r = radeon_device_init(&rdev, radeon);
 	if (r)
 		return r;
@@ -412,7 +387,7 @@ int r600_tri_flat(struct radeon *radeon)
 	vs_shader.input_semantic[1] = 2;
 	vs_shader.input_gpr[1] = 2;
 	vs_shader.sq_pgm_resources_vs = 0x00000006;
-	vs_shader.ndwords = 64;
+	vs_shader.ndwords = 56;
 	vs_shader.opcodes = vsshaders;
 	atom.type = R600_ATOM_VS_SHADER;
 	atom.id = 0;