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authorJayachandran C <jchandra@broadcom.com>2013-03-23 17:27:54 +0000
committerRalf Baechle <ralf@linux-mips.org>2013-05-08 01:19:04 +0200
commite6904ff6c6992e55e068678b1b6c95376fe328fd (patch)
treeab232a4270afc7319b4b7b15b1fc5e89e3f701db /arch
parent33ff712aef509ff1b116a46084c96179f8da1d49 (diff)
MIPS: Netlogic: Remove unused EIMR/EIRR functions
Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions are now unused after the PIC and IRQ code has been updated to use optimized EIMR/EIRR functions which work on both 32-bit and 64-bit. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5021/ Acked-by: John Crispin <blogic@openwrt.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 69d18a0e0581..f299d31d7c1a 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -38,10 +38,6 @@
/*
* XLR and XLP interrupt request and interrupt mask registers
*/
-#define read_c0_eirr() __read_64bit_c0_register($9, 6)
-#define read_c0_eimr() __read_64bit_c0_register($9, 7)
-#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
-
/*
* NOTE: Do not save/restore flags around write_c0_eimr().
* On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
@@ -125,7 +121,7 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
uint64_t val;
#ifdef CONFIG_64BIT
- val = read_c0_eimr() & read_c0_eirr();
+ val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
#else
__asm__ __volatile__(
".set push\n\t"
@@ -140,7 +136,6 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
".set pop"
: "=r" (val));
#endif
-
return val;
}