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Age	Commit message (Expand)	Author	Files	Lines
2014-12-03	R600/SI: Remove i1 pseudo VALU ops	Matt Arsenault	1	-3/+21
2014-11-23	R600/SI: Fix broken check lines and modernize prefixes	Matt Arsenault	1	-44/+41
2014-11-05	R600/SI: Change all instruction assembly names to lowercase.	Tom Stellard	1	-20/+20
2014-10-01	R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ...	Tom Stellard	1	-15/+15
2014-09-24	R600/SI: Enable selecting SALU inside branches	Tom Stellard	1	-2/+1
2014-07-21	R600/SI: Use VALU for i1 XOR	Tom Stellard	1	-1/+1
2014-06-20	R600/SI: Add a VALU pattern for i64 xor	Tom Stellard	1	-0/+26
2014-06-09	R600/SI: Keep 64-bit not on SALU	Matt Arsenault	1	-0/+40
2014-04-09	R600/SI: Match not instruction.	Matt Arsenault	1	-0/+18
2014-03-21	R600/SI: Move instruction patterns to scalar versions.	Matt Arsenault	1	-0/+18
2013-11-12	R600/SI: Change formatting of printed registers.	Matt Arsenault	1	-7/+7
2013-10-10	R600/SI: Use -verify-machineinstrs for most tests	Tom Stellard	1	-1/+1
2013-09-04	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	1	-7/+7
2013-08-16	R600/SI: Add pattern for xor of i1	Michel Danzer	1	-0/+17
2013-06-25	R600/SI: Expand xor v2i32/v4i32	Aaron Watry	1	-7/+33
2013-05-03	R600: Expand vector or, shl, srl, and xor nodes	Tom Stellard	1	-0/+13