diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 15 | ||||
| -rw-r--r-- | test/CodeGen/X86/jump_sign.ll | 11 |
2 files changed, 25 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4baa1a6bbbc..57f61ab38fc 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8271,7 +8271,13 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, // Otherwise use a regular EFLAGS-setting instruction. switch (Op.getNode()->getOpcode()) { default: llvm_unreachable("unexpected operator!"); - case ISD::SUB: Opcode = X86ISD::SUB; break; + case ISD::SUB: + // If the only use of SUB is EFLAGS, use CMP instead. + if (Op.hasOneUse()) + Opcode = X86ISD::CMP; + else + Opcode = X86ISD::SUB; + break; case ISD::OR: Opcode = X86ISD::OR; break; case ISD::XOR: Opcode = X86ISD::XOR; break; case ISD::AND: Opcode = X86ISD::AND; break; @@ -8297,6 +8303,13 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, DAG.getConstant(0, Op.getValueType())); + if (Opcode == X86ISD::CMP) { + SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0), + Op.getOperand(1)); + DAG.ReplaceAllUsesWith(Op, New); + return SDValue(New.getNode(), 0); + } + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); SmallVector<SDValue, 4> Ops; for (unsigned i = 0; i != NumOperands; ++i) diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll index 94cbe5d1937..d253e15774c 100644 --- a/test/CodeGen/X86/jump_sign.ll +++ b/test/CodeGen/X86/jump_sign.ll @@ -83,3 +83,14 @@ entry: %cond = select i1 %cmp, i32 %sub, i32 0 ret i32 %cond } +; rdar://11540023 +define i32 @n(i32 %x, i32 %y) nounwind { +entry: +; CHECK: n: +; CHECK-NOT: sub +; CHECK: cmp + %sub = sub nsw i32 %x, %y + %cmp = icmp slt i32 %sub, 0 + %y.x = select i1 %cmp, i32 %y, i32 %x + ret i32 %y.x +} |