[x86] Add an explicit SSE3 run to this test and flesh out a bunch of

missing specific checks.

While there is a lot of redundancy here where all-but-one mode use the
same code generation, I'd rather have each variant spelled out and
checked so that readers aren't misled by an omission in the test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217765 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 86 insertions, 0 deletions

diff --git a/test/CodeGen/X86/vector-shuffle-128-v4.ll b/test/CodeGen/X86/vector-shuffle-128-v4.ll
index 601db25748a..76df5c6d30d 100644
--- a/test/CodeGen/X86/vector-shuffle-128-v4.ll
+++ b/test/CodeGen/X86/vector-shuffle-128-v4.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse3 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE3
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=SSE41
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
 
@@ -138,6 +139,10 @@ define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
 ; SSE2:         shufps {{.*}} # xmm0 = xmm0[0,0,2,2]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_0022
+; SSE3:         movsldup {{.*}} # xmm0 = xmm0[0,0,2,2]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_0022
 ; SSE41:         movsldup {{.*}} # xmm0 = xmm0[0,0,2,2]
 ; SSE41-NEXT:    retq
@@ -153,6 +158,10 @@ define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
 ; SSE2:         shufps {{.*}} # xmm0 = xmm0[1,1,3,3]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_1133
+; SSE3:         movshdup {{.*}} # xmm0 = xmm0[1,1,3,3]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_1133
 ; SSE41:         movshdup {{.*}} # xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    retq
@@ -170,6 +179,11 @@ define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,1],xmm1[2,0]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4i32_0124
+; SSE3:         shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[2,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,1],xmm1[2,0]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4i32_0124
 ; SSE41:         insertps {{.*}} # xmm0 = xmm0[0,1,2],xmm1[0]
 ; SSE41-NEXT:    retq
@@ -195,6 +209,18 @@ define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4i32_0412
+; SSE3:         shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm1 = xmm1[2,0],xmm0[1,2]
+; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSE41-LABEL: @shuffle_v4i32_0412
+; SSE41:         shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE41-NEXT:    shufps {{.*}} # xmm1 = xmm1[2,0],xmm0[1,2]
+; SSE41-NEXT:    movaps %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: @shuffle_v4i32_0412
 ; AVX1:         vshufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
 ; AVX1-NEXT:    vshufps {{.*}} # xmm0 = xmm1[2,0],xmm0[1,2]
@@ -209,6 +235,18 @@ define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-NEXT:    movaps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4i32_4012
+; SSE3:         shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm1 = xmm1[0,2],xmm0[1,2]
+; SSE3-NEXT:    movaps %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSE41-LABEL: @shuffle_v4i32_4012
+; SSE41:         shufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE41-NEXT:    shufps {{.*}} # xmm1 = xmm1[0,2],xmm0[1,2]
+; SSE41-NEXT:    movaps %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: @shuffle_v4i32_4012
 ; AVX1:         vshufps {{.*}} # xmm1 = xmm1[0,0],xmm0[0,0]
 ; AVX1-NEXT:    vshufps {{.*}} # xmm0 = xmm1[0,2],xmm0[1,2]
@@ -237,6 +275,16 @@ define <4 x i32> @shuffle_v4i32_4501(<4 x i32> %a, <4 x i32> %b) {
 ; SSE2-NEXT:    movdqa %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4i32_4501
+; SSE3:         punpcklqdq {{.*}} # xmm1 = xmm1[0],xmm0[0]
+; SSE3-NEXT:    movdqa %xmm1, %xmm0
+; SSE3-NEXT:    retq
+;
+; SSE41-LABEL: @shuffle_v4i32_4501
+; SSE41:         punpcklqdq {{.*}} # xmm1 = xmm1[0],xmm0[0]
+; SSE41-NEXT:    movdqa %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
 ; AVX1-LABEL: @shuffle_v4i32_4501
 ; AVX1:         punpcklqdq {{.*}} # xmm0 = xmm1[0],xmm0[0]
 ; AVX1-NEXT:    retq
@@ -259,6 +307,12 @@ define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
 ; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2],[[X]][2,3]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_4zzz
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,0],[[X]][1,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,2],[[X]][2,3]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_4zzz
 ; SSE41:         xorps %[[X:xmm[0-9]+]], %[[X]]
 ; SSE41-NEXT:    blendps {{.*}} # [[X]] = xmm0[0],[[X]][1,2,3]
@@ -280,6 +334,12 @@ define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
 ; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[2,0],[[X]][3,0]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_z4zz
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,0],[[X]][2,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[2,0],[[X]][3,0]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_z4zz
 ; SSE41:         insertps {{.*}} # xmm0 = zero,xmm0[0],zero,zero
 ; SSE41-NEXT:    retq
@@ -299,6 +359,13 @@ define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
 ; SSE2-NEXT:    movaps %[[X]], %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_zz4z
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[0,0],[[X]][0,0]
+; SSE3-NEXT:    shufps {{.*}} # [[X]] = [[X]][0,0],xmm0[0,2]
+; SSE3-NEXT:    movaps %[[X]], %xmm0
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_zz4z
 ; SSE41:         insertps {{.*}} # xmm0 = zero,zero,xmm0[0],zero
 ; SSE41-NEXT:    retq
@@ -317,6 +384,12 @@ define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
 ; SSE2-NEXT:    movaps %[[X]], %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_zuu4
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # [[X]] = [[X]][0,1],xmm0[2,0]
+; SSE3-NEXT:    movaps %[[X]], %xmm0
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_zuu4
 ; SSE41:         insertps {{.*}} # xmm0 = zero,zero,zero,xmm0[0]
 ; SSE41-NEXT:    retq
@@ -336,6 +409,13 @@ define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) {
 ; SSE2-NEXT:    movaps %[[X]], %xmm0
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_zzz7
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[3,0],[[X]][2,0]
+; SSE3-NEXT:    shufps {{.*}} # [[X]] = [[X]][0,1],xmm0[2,0]
+; SSE3-NEXT:    movaps %[[X]], %xmm0
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_zzz7
 ; SSE41:         xorps %[[X:xmm[0-9]+]], %[[X]]
 ; SSE41-NEXT:    blendps {{.*}} # [[X]] = [[X]][0,1,2],xmm0[3]
@@ -357,6 +437,12 @@ define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
 ; SSE2-NEXT:    shufps {{.*}} # xmm0 = xmm0[2,0],[[X]][2,3]
 ; SSE2-NEXT:    retq
 ;
+; SSE3-LABEL: @shuffle_v4f32_z6zz
+; SSE3:         xorps %[[X:xmm[0-9]+]], %[[X]]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[2,0],[[X]][0,0]
+; SSE3-NEXT:    shufps {{.*}} # xmm0 = xmm0[2,0],[[X]][2,3]
+; SSE3-NEXT:    retq
+;
 ; SSE41-LABEL: @shuffle_v4f32_z6zz
 ; SSE41:         insertps {{.*}} # xmm0 = zero,xmm0[2],zero,zero
 ; SSE41-NEXT:    retq