diff options
| author | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
| commit | 6a7770b7ae43d784dec6f4d3c73ffed6166f3882 (patch) | |
| tree | 289f5949305117ae55c95f997e9f6e50b28b5ece /test/CodeGen/X86/gather-addresses.ll | |
| parent | c622824ccbb74ac726c656ebc98647810d152cce (diff) | |
Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.
Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.
On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.
Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.
The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.
Unit tests are updated so they don't depend on SD scheduling heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/gather-addresses.ll')
| -rw-r--r-- | test/CodeGen/X86/gather-addresses.ll | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll index 72a50961b2f..5f48b1e32b1 100644 --- a/test/CodeGen/X86/gather-addresses.ll +++ b/test/CodeGen/X86/gather-addresses.ll @@ -1,21 +1,35 @@ -; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN +; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN ; rdar://7398554 ; When doing vector gather-scatter index calculation with 32-bit indices, ; bounce the vector off of cache rather than shuffling each individual ; element out of the index vector. -; CHECK: andps ([[H:%rdx|%r8]]), %xmm0 -; CHECK: movaps %xmm0, {{(-24)?}}(%rsp) -; CHECK: movslq {{(-24)?}}(%rsp), %rax -; CHECK: movsd ([[P:%rdi|%rcx]],%rax,8), %xmm0 -; CHECK: movslq {{-20|4}}(%rsp), %rax -; CHECK: movhpd ([[P]],%rax,8), %xmm0 -; CHECK: movslq {{-16|8}}(%rsp), %rax -; CHECK: movsd ([[P]],%rax,8), %xmm1 -; CHECK: movslq {{-12|12}}(%rsp), %rax -; CHECK: movhpd ([[P]],%rax,8), %xmm1 +; CHECK: foo: +; LIN: movaps (%rsi), %xmm0 +; LIN: andps (%rdx), %xmm0 +; LIN: movaps %xmm0, -24(%rsp) +; LIN: movslq -24(%rsp), %[[REG1:r.+]] +; LIN: movslq -20(%rsp), %[[REG2:r.+]] +; LIN: movslq -16(%rsp), %[[REG3:r.+]] +; LIN: movslq -12(%rsp), %[[REG4:r.+]] +; LIN: movsd (%rdi,%[[REG1]],8), %xmm0 +; LIN: movhpd (%rdi,%[[REG2]],8), %xmm0 +; LIN: movsd (%rdi,%[[REG3]],8), %xmm1 +; LIN: movhpd (%rdi,%[[REG4]],8), %xmm1 + +; WIN: movaps (%rdx), %xmm0 +; WIN: andps (%r8), %xmm0 +; WIN: movaps %xmm0, (%rsp) +; WIN: movslq (%rsp), %[[REG1:r.+]] +; WIN: movslq 4(%rsp), %[[REG2:r.+]] +; WIN: movslq 8(%rsp), %[[REG3:r.+]] +; WIN: movslq 12(%rsp), %[[REG4:r.+]] +; WIN: movsd (%rcx,%[[REG1]],8), %xmm0 +; WIN: movhpd (%rcx,%[[REG2]],8), %xmm0 +; WIN: movsd (%rcx,%[[REG3]],8), %xmm1 +; WIN: movhpd (%rcx,%[[REG4]],8), %xmm1 define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind { %a = load <4 x i32>* %i |