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authorTom Stellard <thomas.stellard@amd.com>2015-01-06 18:00:21 +0000
committerTom Stellard <thomas.stellard@amd.com>2015-01-06 18:00:21 +0000
commit1f996fa36b28f264b02c76b4bab3ac15c5a54bf4 (patch)
tree2d10ba47b93a3fcb8290e2cee7e5d0b176a8edca /test/CodeGen/R600/si-lod-bias.ll
parenta31ae5e0b0e16c6fdfa8241f9d30928b988605a8 (diff)
R600/SI: Add a stub GCNTargetMachine
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/si-lod-bias.ll')
-rw-r--r--test/CodeGen/R600/si-lod-bias.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/R600/si-lod-bias.ll b/test/CodeGen/R600/si-lod-bias.ll
index 5ef77228a31..2e2f2ce5fec 100644
--- a/test/CodeGen/R600/si-lod-bias.ll
+++ b/test/CodeGen/R600/si-lod-bias.ll
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
; This shader has the potential to generated illegal VGPR to SGPR copies if
; the wrong register class is used for the REG_SEQUENCE instructions.