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| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-04-22 11:18:40 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-04-22 11:18:40 +0000 |
| commit | fed867f0f804464edfcdd1bb159fc57d4138d127 (patch) | |
| tree | f26d2df46d369c08cf82fa56b65655c21d3946ac /test/CodeGen/Mips | |
| parent | c1499f823251b9b2ddd8229e4c9c765f6d8db346 (diff) | |
[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: http://reviews.llvm.org/D19354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267137 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
| -rw-r--r-- | test/CodeGen/Mips/brconlt.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/seteq.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/Mips/setltk.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/Mips/setne.ll | 2 |
4 files changed, 10 insertions, 2 deletions
diff --git a/test/CodeGen/Mips/brconlt.ll b/test/CodeGen/Mips/brconlt.ll index 487018c22f2..3fc937d4ec8 100644 --- a/test/CodeGen/Mips/brconlt.ll +++ b/test/CodeGen/Mips/brconlt.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 @@ -13,6 +14,7 @@ entry: br i1 %cmp, label %if.end, label %if.then ; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]] ; 16: $[[LABEL]]: diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll index 76f9bb3ebf9..532dd3b311f 100644 --- a/test/CodeGen/Mips/seteq.ll +++ b/test/CodeGen/Mips/seteq.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}} ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1 +; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1 ; 16: move ${{[0-9]+}}, $24 ret void } diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll index 79d25b1f130..32414afd365 100644 --- a/test/CodeGen/Mips/setltk.ll +++ b/test/CodeGen/Mips/setltk.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @j = global i32 -5, align 4 @k = global i32 10, align 4 @@ -14,7 +15,8 @@ entry: %cmp = icmp slt i32 %0, 10 %conv = zext i1 %cmp to i32 store i32 %conv, i32* @r1, align 4 -; 16: slti $[[REGISTER:[0-9]+]], 10 -; 16: move $[[REGISTER]], $24 +; 16: slti $[[REGISTER:[0-9]+]], 10 +; MM32R6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10 +; 16: move $[[REGISTER]], $24 ret void } diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll index 02692bf9e63..9b0e6e65fca 100644 --- a/test/CodeGen/Mips/setne.ll +++ b/test/CodeGen/Mips/setne.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 @@ -15,6 +16,7 @@ entry: store i32 %conv, i32* @r1, align 4 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, $[[REGISTER]] +; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, $24 ret void } |