diff options
| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-04-22 13:19:22 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-04-22 13:19:22 +0000 |
| commit | ad461d606700d143dc153df43ecc7703a1564df1 (patch) | |
| tree | d07fc0ce1249e6a834528c10a7ed8888db196146 /test/CodeGen/Mips | |
| parent | 47534d9ca659380b32ab91a1a5089e9495243372 (diff) | |
[mips] Fix select patterns for MIPS64
When targetting MIPS64R6 some of the patterns for select were guarded by a
broken predicate. The predicate was supposed to test if a constant value
could fit in a 16 bit zero-extended field. Instead the value was tested to
fit in a 16 bit sign-extended field. For negative constants of native word
width this resulted in wrong code generation.
Reviewers: vkalintiris, dsanders
Differential Review: http://reviews.llvm.org/D19378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267151 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/select-int.ll | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/select-int.ll b/test/CodeGen/Mips/llvm-ir/select-int.ll index 87f2ca4b8a1..d179446b2c3 100644 --- a/test/CodeGen/Mips/llvm-ir/select-int.ll +++ b/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -160,3 +160,53 @@ entry: %r = select i1 %s, i64 %x, i64 %y ret i64 %r } + +define i8* @tst_select_word_cst(i8* %a, i8* %b) { + ; ALL-LABEL: tst_select_word_cst: + + ; M2: addiu $1, $zero, -1 + ; M2: xor $1, $5, $1 + ; M2: sltu $1, $zero, $1 + ; M2: bnez $1, $[[BB0:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: move $2, $4 + ; M2: $[[BB0]]: + ; M2: jr $ra + + ; M3: daddiu $1, $zero, -1 + ; M3: xor $1, $5, $1 + ; M3: sltu $1, $zero, $1 + ; M3: bnez $1, $[[BB0:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $4 + ; M3: $[[BB0]]: + ; M3: jr $ra + + ; CMOV-32: addiu $1, $zero, -1 + ; CMOV-32: xor $1, $5, $1 + ; CMOV-32: movn $4, $zero, $1 + ; CMOV-32: jr $ra + ; CMOV-32: move $2, $4 + + ; SEL-32: addiu $1, $zero, -1 + ; SEL-32: xor $1, $5, $1 + ; SEL-32: sltu $1, $zero, $1 + ; SEL-32: jr $ra + ; SEL-32: seleqz $2, $4, $1 + + ; CMOV-64: daddiu $1, $zero, -1 + ; CMOV-64: xor $1, $5, $1 + ; CMOV-64: movn $4, $zero, $1 + ; CMOV-64: move $2, $4 + + ; SEL-64: daddiu $1, $zero, -1 + ; SEL-64: xor $1, $5, $1 + ; SEL-64: sltu $1, $zero, $1 + ; FIXME: This shift is redundant. + ; SEL-64: sll $1, $1, 0 + ; SEL-64: seleqz $2, $4, $1 + + %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*) + %r = select i1 %cmp, i8* %a, i8* null + ret i8* %r +} |