[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions

Differential Revision: http://reviews.llvm.org/D17989


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267693 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 112 insertions, 4 deletions

diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll
index 901fef850ba..066fcbd321b 100644
--- a/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -37,6 +37,10 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -53,7 +57,9 @@ entry:
 ; ALL-LABEL: ashr_i8:
 
   ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 255
+  ; GP32:       andi    $[[T0:[0-9]+]], $5, 255
+  ; GP64:       andi    $[[T0:[0-9]+]], $5, 255
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 255
   ; ALL:        srav    $2, $4, $[[T0]]
 
   %r = ashr i8 %a, %b
@@ -65,7 +71,9 @@ entry:
 ; ALL-LABEL: ashr_i16:
 
   ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 65535
+  ; GP32:       andi    $[[T0:[0-9]+]], $5, 65535
+  ; GP64:       andi    $[[T0:[0-9]+]], $5, 65535
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 65535
   ; ALL:        srav    $2, $4, $[[T0]]
 
   %r = ashr i16 %a, %b
@@ -133,6 +141,32 @@ entry:
 
   ; GP64:       dsrav     $2, $4, $5
 
+  ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       srav      $[[T5:[0-9]+]], $4, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       sra       $[[T8:[0-9]+]], $4, 31
+  ; MMR3:       movn      $2, $[[T8]], $[[T6]]
+
+  ; MMR6:       srav      $[[T0:[0-9]+]], $4, $7
+  ; MMR6:       andi16    $[[T1:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+  ; MMR6:       sra       $[[T3:[0-9]+]], $4, 31
+  ; MMR6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
+  ; MMR6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
+  ; MMR6:       srlv      $[[T6:[0-9]+]], $5, $7
+  ; MMR6:       not       $[[T7:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T8:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; MMR6:       or16      $[[T10:[0-9]+]], $[[T6]]
+  ; MMR6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
+  ; MMR6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
+  ; MMR6:       or        $3, $[[T12]], $[[T11]]
+
   %r = ashr i64 %a, %b
   ret i64 %r
 }
@@ -192,6 +226,8 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
+  ; MM:             lw        $25, %call16(__ashrti3)($2)
+
   %r = ashr i128 %a, %b
   ret i128 %r
 }
diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 0e637eba9e2..9c61aeb98ef 100644
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -37,6 +37,10 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -53,7 +57,9 @@ entry:
 ; ALL-LABEL: lshr_i8:
 
   ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 255
+  ; GP32:       andi    $2, $[[T0]], 255
+  ; GP64:       andi    $2, $[[T0]], 255
+  ; MM:         andi16  $2, $[[T0]], 255
 
   %r = lshr i8 %a, %b
   ret i8 %r
@@ -64,7 +70,9 @@ entry:
 ; ALL-LABEL: lshr_i16:
 
   ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 65535
+  ; GP32:       andi    $2, $[[T0]], 65535
+  ; GP64:       andi    $2, $[[T0]], 65535
+  ; MM:         andi16  $2, $[[T0]], 65535
 
   %r = lshr i16 %a, %b
   ret i16 %r
@@ -127,6 +135,29 @@ entry:
 
   ; GP64:         dsrlv   $2, $4, $5
 
+  ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       srlv      $[[T5:[0-9]+]], $4, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       lui       $[[T8:[0-9]+]], 0
+  ; MMR3:       movn      $2, $[[T8]], $[[T6]]
+
+  ; MMR6:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR6:       not       $[[T1:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T2:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+  ; MMR6:       srlv      $[[T7:[0-9]+]], $4, $7
+  ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+  ; MMR6:       or        $3, $[[T8]], $[[T6]]
+  ; MMR6:       seleqz    $2, $[[T7]], $[[T5]]
+
   %r = lshr i64 %a, %b
   ret i64 %r
 }
@@ -182,6 +213,8 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
+  ; MM:             lw        $25, %call16(__lshrti3)($2)
+
   %r = lshr i128 %a, %b
   ret i128 %r
 }
diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index f15ff9ad2c0..1e022c91192 100644
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -37,6 +37,10 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -61,6 +65,10 @@ entry:
   ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; R2-R6:      seb     $2, $[[T1]]
 
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 255
+  ; MM:         sllv    $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MM:         seb     $2, $[[T1]]
+
   %r = shl i8 %a, %b
   ret i8 %r
 }
@@ -78,6 +86,10 @@ entry:
   ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; R2-R6:      seh     $2, $[[T1]]
 
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 65535
+  ; MM:         sllv    $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MM:         seh     $2, $[[T1]]
+
   %r = shl i16 %a, %b
   ret i16 %r
 }
@@ -139,6 +151,29 @@ entry:
 
   ; GP64:       dsllv     $2, $4, $5
 
+  ; MMR3:       sllv      $[[T0:[0-9]+]], $4, $7
+  ; MMR3:       srl16     $[[T1:[0-9]+]], $5, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       sllv      $[[T5:[0-9]+]], $5, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       lui       $[[T8:[0-9]+]], 0
+  ; MMR3:       movn      $3, $[[T8]], $[[T6]]
+
+  ; MMR6:       sllv      $[[T0:[0-9]+]], $4, $7
+  ; MMR6:       not       $[[T1:[0-9]+]], $7
+  ; MMR6:       srl16     $[[T2:[0-9]+]], $5, 1
+  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+  ; MMR6:       sllv      $[[T7:[0-9]+]], $5, $7
+  ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+  ; MMR6:       or        $2, $[[T8]], $[[T6]]
+  ; MMR6:       seleqz    $3, $[[T7]], $[[T5]]
+
   %r = shl i64 %a, %b
   ret i64 %r
 }
@@ -194,6 +229,8 @@ entry:
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
+  ; MM:             lw        $25, %call16(__ashlti3)($2)
+
   %r = shl i128 %a, %b
   ret i128 %r
 }
diff --git a/test/CodeGen/Mips/micromips-shift.ll b/test/CodeGen/Mips/micromips-shift.ll
index ed1bcbbf083..a4f8ffe9408 100644
--- a/test/CodeGen/Mips/micromips-shift.ll
+++ b/test/CodeGen/Mips/micromips-shift.ll
@@ -1,5 +1,7 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @a = global i32 10, align 4
 @b = global i32 0, align 4