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authorSanjay Patel <spatel@rotateright.com>2016-05-20 22:08:40 +0000
committerSanjay Patel <spatel@rotateright.com>2016-05-20 22:08:40 +0000
commit85b08a7199b55f691dad3eda141b4d553e6cfa59 (patch)
tree2f225b9da543dd1c5be6b2fbc570ab1c0eea7c63
parent45022fd14b90536a685d61de7554097989ebf480 (diff)
add test vector sdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270285 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/Transforms/InstCombine/div.ll15
1 files changed, 15 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index a3befb0146e..e4fd3324777 100644
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -369,6 +369,21 @@ define i32 @test36(i32 %A) {
ret i32 %mul
}
+; FIXME: Vector should get same transform as scalar.
+
+define <2 x i32> @test36vec(<2 x i32> %A) {
+; CHECK-LABEL: @test36vec(
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> <i32 1, i32 1>, %A
+; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]]
+; CHECK-NEXT: ret <2 x i32> [[MUL]]
+;
+ %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+ %shl = shl nsw <2 x i32> <i32 1, i32 1>, %A
+ %mul = sdiv exact <2 x i32> %and, %shl
+ ret <2 x i32> %mul
+}
+
define i32 @test37(i32* %b) {
; CHECK-LABEL: @test37(
; CHECK-NEXT: entry: