diff options
| author | Tang Yuantian <Yuantian.Tang@freescale.com> | 2015-12-16 13:43:50 +0800 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2015-12-16 10:24:35 -0500 |
| commit | e3a6dadc6dca64f464238f8a36876c610400eef9 (patch) | |
| tree | f9eebe97b8aeda0692aba16c45302aeb31e8ce3f /drivers/ata | |
| parent | ef0cc7fef4721aa19663da7475c8b862f0a35e0b (diff) | |
ahci: qoriq: Update the default Rx watermark value
The PTC[RXWM] sets the watermark value for Rx FIFO. The default
value 0x20 might be insufficient for some hard drives. If the
watermark value is too small, a single-cycle overflow may occur
and is reported as a CRC or internal error in the PxSERR register.
Updated the value to 0x29 according to the validation test.
All LS platforms are affected.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/ahci_qoriq.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index 4d613f8cb966..256d9114a194 100644 --- a/drivers/ata/ahci_qoriq.c +++ b/drivers/ata/ahci_qoriq.c @@ -38,7 +38,7 @@ #define AHCI_PORT_PHY_3_CFG 0x0e081004 #define AHCI_PORT_PHY_4_CFG 0x00480811 #define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define LS1043A_PORT_PHY2 0x28184d1f #define LS1043A_PORT_PHY3 0x0e081509 @@ -169,6 +169,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) case AHCI_LS2080A: writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); break; } |