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authorPierre Tardy <pierre.tardy@intel.com>2011-01-06 16:23:29 +0100
committerIngo Molnar <mingo@elte.hu>2011-01-10 09:36:49 +0100
commit4aed89d6b515b9185351706ca95cd712c9d8d6a3 (patch)
tree7f991c337a8949b04be4d52475ecbd31fe82f2d1 /arch/x86/kernel/amd_nb.c
parent9adcc4a127be6c979eae1ae34083261f2ec5dfec (diff)
x86, lapic-timer: Increase the max_delta to 31 bits
Latest atom socs(penwell) does not have hpet timer. As their local APIC timer is clocked at 400KHZ, and the current code limit their Initial Counter register to 23 bits, they cannot sleep more than 1.34 seconds which leads to ~2 spurious wakeup per second (1 per thread) These SOCs support 32bit timer so we change the max_delta to at least 31bits. So we can at least sleep for 300 seconds. We could not find any previous chip errata where lapic would only have 23 bit precision As powertop is suggesting to activate HPET to "sleep longer", this could mean this problem is already known. Problem is here since very first implementation of lapic timer as a clock event e9e2cdb [PATCH] clockevents: i386 drivers. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Pierre Tardy <pierre.tardy@intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Adrian Bunk <bunk@stusta.de> Cc: H. Peter Anvin <hpa@linux.intel.com> Cc: john stultz <johnstul@us.ibm.com> Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Andi Kleen <ak@suse.de> LKML-Reference: <1294327409-19426-1-git-send-email-pierre.tardy@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/amd_nb.c')
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