summaryrefslogtreecommitdiff
path: root/tests/tcg/xtensa/test_loop.S
blob: 5755578d01912e80c375def15aa2c05c2238991d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
#include "macros.inc"

test_suite loop

test loop
    movi    a2, 0
    movi    a3, 5
    loop    a3, 1f
    addi    a2, a2, 1
1:
    assert  eqi, a2, 5
test_end

test loop0
    movi    a2, 0
    loop    a2, 1f
    rsr     a2, lcount
    assert  eqi, a2, -1
    j       1f
1:
test_end

test loop_jump
    movi    a2, 0
    movi    a3, 5
    loop    a3, 1f
    addi    a2, a2, 1
    j       1f
1:
    assert  eqi, a2, 1
test_end

test loop_branch
    movi    a2, 0
    movi    a3, 5
    loop    a3, 1f
    addi    a2, a2, 1
    beqi    a2, 3, 1f
1:
    assert  eqi, a2, 3
test_end

test loop_manual
    movi    a2, 0
    movi    a3, 5
    movi    a4, 1f
    movi    a5, 2f
    wsr     a3, lcount
    wsr     a4, lbeg
    wsr     a5, lend
    isync
    j       1f
.align 4
1:
    addi    a2, a2, 1
2:
    assert  eqi, a2, 6
test_end

test loop_excm
    movi    a2, 0
    movi    a3, 5
    rsr     a4, ps
    movi    a5, 0x10
    or      a4, a4, a5
    wsr     a4, ps
    isync
    loop    a3, 1f
    addi    a2, a2, 1
1:
    xor     a4, a4, a5
    isync
    wsr     a4, ps
    assert  eqi, a2, 1
test_end

test lbeg_invalidation
    movi    a2, 0
    movi    a3, 1
    movi    a4, 1f
    movi    a5, 3f
    wsr     a3, lcount
    wsr     a4, lbeg
    wsr     a5, lend
    isync
    j       1f
.align 4
1:
    addi    a2, a2, 1
    j       2f
.align 4
2:
    addi    a2, a2, 2
    movi    a3, 2b
    wsr     a3, lbeg
    isync
    nop
3:
    assert  eqi, a2, 5
test_end

test lend_invalidation
    movi    a2, 0
    movi    a3, 5
    movi    a4, 1f
    movi    a5, 2f
    wsr     a3, lcount
    wsr     a4, lbeg
    wsr     a5, lend
    isync
    j       1f
.align 4
1:
    addi    a2, a2, 1
2:
    beqi    a3, 3, 1f
    assert  eqi, a2, 6
    movi    a3, 3
    wsr     a3, lcount
    wsr     a4, lend
    isync
    j       1b
1:
    assert  eqi, a2, 7
test_end

test loopnez
    movi    a2, 0
    movi    a3, 5
    loopnez a3, 1f
    addi    a2, a2, 1
1:
    assert  eqi, a2, 5

    movi    a2, 0
    movi    a3, 0
    loopnez a3, 1f
    test_fail
1:
test_end

test loopgtz
    movi    a2, 0
    movi    a3, 5
    loopgtz a3, 1f
    addi    a2, a2, 1
1:
    assert  eqi, a2, 5

    movi    a2, 0
    movi    a3, 0
    loopgtz a3, 1f
    test_fail
1:

    movi    a2, 0
    movi    a3, 0x80000000
    loopgtz a3, 1f
    test_fail
1:
test_end

test_suite_end