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2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson1-9/+4
2018-05-14target/openrisc: Convert dec_floatRichard Henderson2-230/+149
2018-05-14target/openrisc: Convert dec_compiRichard Henderson2-58/+70
2018-05-14target/openrisc: Convert dec_compRichard Henderson2-62/+73
2018-05-14target/openrisc: Convert dec_MRichard Henderson2-28/+16
2018-05-14target/openrisc: Convert dec_logicRichard Henderson2-36/+32
2018-05-14target/openrisc: Convert dec_macRichard Henderson2-33/+27
2018-05-14target/openrisc: Convert dec_calcRichard Henderson2-169/+229
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2-153/+141
2018-05-14target/openrisc: Convert memory insnsRichard Henderson2-139/+160
2018-05-14target/openrisc: Convert branch insnsRichard Henderson2-78/+84
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson3-43/+78
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson3-252/+126
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota1-84/+79
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota1-47/+46
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk1-4/+4
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée2-1/+1
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-3/+2
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier3-8/+8
2017-12-27target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée1-5/+1
2017-12-18misc: remove duplicated includesPhilippe Mathieu-Daudé1-1/+0
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2-46/+26
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov2-46/+26
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-3/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+1
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne4-5/+5
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne1-2/+3
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-0/+6
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2-8/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-2/+2
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne5-1/+28
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne2-28/+5
2017-05-04target/openrisc: Implement full vmstate serializationStafford Horne1-2/+71
2017-05-04target/openrisc: implement shadow registersStafford Horne6-10/+33
2017-05-04target/openrisc: add numcores and coreid supportStafford Horne1-0/+6
2017-05-04target/openrisc: Fixes for memory debuggingStafford Horne1-4/+20
2017-04-21target/openrisc: Implement EPH bitTim 'mithro' Ansell1-0/+3
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell4-1/+21
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson3-23/+66
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson5-35/+25
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson6-55/+39
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson1-1/+5
2017-02-14target/openrisc: Fix maddRichard Henderson4-61/+30