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AgeCommit message (Expand)AuthorFilesLines
2008-10-07CRIS: Fix brk 8 and add S-flag emulation.edgar_igl1-1/+1
2008-09-15SH4: Privilege check for instructionsaurel321-1/+4
2008-07-17Support for address maskingblueswir11-2/+3
2008-07-08Fix r4641 (invalid token "=<" in a preprocessor expression)blueswir11-1/+1
2008-07-03Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.ths1-3/+3
2008-06-30Spelling fixes, spotted by Stuart Brady.ths1-1/+1
2008-06-29Add instruction counter.pbrook1-30/+63
2008-06-27More efficient target register / TC accesses.ths1-1/+1
2008-06-09CRIS: Emulate NMIs.edgar_igl1-1/+9
2008-06-07Multithreaded locking fixes.pbrook1-14/+11
2008-06-06CRIS: Add the P flag to the tb dependent flags.edgar_igl1-1/+1
2008-06-04reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworke...bellard1-44/+45
2008-06-02Restore ARM signal handler compilation on glibc < 2.5 (Blue Swirl).balrog1-0/+4
2008-05-29Remove unused (for now) reg_REGWPTR (original patch by Glauber Costa)blueswir11-13/+0
2008-05-28SVM reworkbellard1-1/+0
2008-05-27removed unused codebellard1-7/+0
2008-05-27CRIS: Re-add the X flag to the tb flags, it allows for better code generation...edgar_igl1-1/+1
2008-05-27Move non-op functions from op_helper.c to helper.c and vice versa.blueswir11-2/+3
2008-05-19Fix Sparc32 compilation broken by r4484blueswir11-1/+1
2008-05-18Fix Sparc64 host signal handlingblueswir11-5/+10
2008-05-17Improved workaround for the annoying glibc global register mangling bugblueswir11-47/+11
2008-05-15Always process real timers regardless of singlestep mode (Jason Wessel).edgar_igl1-1/+1
2008-05-14Fix compilation on Sparc host, implement ld and stblueswir11-5/+0
2008-05-13CRIS: Improve TLB management and handle delayslots at page boundaries.edgar_igl1-0/+1
2008-05-12use new helper namebellard1-1/+1
2008-05-12the double/triple fault handling was not tested in user mode.bellard1-0/+2
2008-05-10initial global prologue/epilogue implementationbellard1-62/+3
2008-05-10Fix compiler warnings in common filesblueswir11-1/+1
2008-05-09Debugger single step without interrupts (Jason Wessel).edgar_igl1-1/+1
2008-05-07CRIS: Remove X flag from tb flags.edgar_igl1-1/+1
2008-05-06Fix signal handler compilation on __arm__.balrog1-1/+1
2008-05-04Fix crash due to invalid env->current_tb (Adam Lackorzynski, Paul Brook, me)blueswir11-24/+44
2008-05-03CRIS: Reduce the number of tb dependent flags.edgar_igl1-1/+1
2008-05-02CRIS updates:edgar_igl1-1/+1
2008-04-13x86: Introduce CPU_INTERRUPT_NMIaurel321-0/+6
2008-04-12HPPA (PA-RISC) host supportaurel321-0/+29
2008-04-11Fix compiler warningsaurel321-0/+4
2008-03-14* Add a model of the ETRAX interrupt controller.edgar_igl1-5/+0
2008-02-01reverted -translation option supportbellard1-62/+1
2008-02-01use the TCG code generatorbellard1-2/+2
2008-01-23Add option to disable TB cache, by Herve Poussineau.ths1-1/+61
2007-12-11 Partial fix to Sparc32 Linux host global register mangling problemblueswir11-22/+52
2007-12-11 Fix code generation buffer overflow reported by TeLeManblueswir11-1/+1
2007-12-02SH4: system emulator interrupt update, by Magnus Damm.ths1-1/+4
2007-12-02SH4 delay slot code update, by Magnus Damm.ths1-2/+2
2007-11-23Fix TB chaining for exceptions.pbrook1-35/+17
2007-11-11consistent types for cpu_x86_fsave and cpu_x86_frstorbellard1-4/+4
2007-11-11removed warningbellard1-2/+2
2007-11-11ARMv7 support.pbrook1-1/+12
2007-11-08removed obsolete x86 code copy supportbellard1-121/+5
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