diff options
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/helper.h | 4 | ||||
| -rw-r--r-- | target-sparc/op.c | 22 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 21 | ||||
| -rw-r--r-- | target-sparc/translate.c | 8 |
4 files changed, 29 insertions, 26 deletions
diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 65f22a9d5b..6ad0f20a77 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -8,6 +8,10 @@ target_ulong TCG_HELPER_PROTO helper_rdpsr(void); void TCG_HELPER_PROTO helper_wrpstate(target_ulong new_state); void TCG_HELPER_PROTO helper_done(void); void TCG_HELPER_PROTO helper_retry(void); +target_ulong TCG_HELPER_PROTO helper_rdccr(void); +void TCG_HELPER_PROTO helper_wrccr(target_ulong new_ccr); +target_ulong TCG_HELPER_PROTO helper_rdcwp(void); +void TCG_HELPER_PROTO helper_wrcwp(target_ulong new_cwp); target_ulong TCG_HELPER_PROTO helper_array8(target_ulong pixel_addr, target_ulong cubesize); target_ulong TCG_HELPER_PROTO helper_alignaddr(target_ulong addr, diff --git a/target-sparc/op.c b/target-sparc/op.c index bf62224dc9..e9e735a9ea 100644 --- a/target-sparc/op.c +++ b/target-sparc/op.c @@ -258,28 +258,6 @@ void OPPROTO op_restore(void) FORCE_RET(); } #else -void OPPROTO op_rdccr(void) -{ - T0 = GET_CCR(env); -} - -void OPPROTO op_wrccr(void) -{ - PUT_CCR(env, T0); -} - -// CWP handling is reversed in V9, but we still use the V8 register -// order. -void OPPROTO op_rdcwp(void) -{ - T0 = GET_CWP64(env); -} - -void OPPROTO op_wrcwp(void) -{ - PUT_CWP64(env, T0); -} - /* XXX: use another pointer for %iN registers to avoid slow wrapping handling ? */ void OPPROTO op_save(void) diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 18a01f5d75..b47e50e52e 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -1636,6 +1636,27 @@ target_ulong helper_rdpsr(void) } #else +target_ulong helper_rdccr(void) +{ + return GET_CCR(env); +} + +void helper_wrccr(target_ulong new_ccr) +{ + PUT_CCR(env, new_ccr); +} + +// CWP handling is reversed in V9, but we still use the V8 register +// order. +target_ulong helper_rdcwp(void) +{ + return GET_CWP64(env); +} + +void helper_wrcwp(target_ulong new_cwp) +{ + PUT_CWP64(env, new_cwp); +} // This function uses non-native bit order #define GET_FIELD(X, FROM, TO) \ diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 7032dab115..fce4de086d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2023,7 +2023,7 @@ static void disas_sparc_insn(DisasContext * dc) break; #ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ - gen_op_rdccr(); + tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]); gen_movl_T0_reg(rd); break; case 0x3: /* V9 rdasi */ @@ -2205,7 +2205,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp - gen_op_rdcwp(); + tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]); break; case 10: // cansave gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); @@ -3113,7 +3113,7 @@ static void disas_sparc_insn(DisasContext * dc) #else case 0x2: /* V9 wrccr */ gen_op_xor_T1_T0(); - gen_op_wrccr(); + tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]); break; case 0x3: /* V9 wrasi */ gen_op_xor_T1_T0(); @@ -3322,7 +3322,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp - gen_op_wrcwp(); + tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]); break; case 10: // cansave gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); |