diff options
| -rw-r--r-- | hw/arm-misc.h | 2 | ||||
| -rw-r--r-- | hw/arm_boot.c | 8 | ||||
| -rw-r--r-- | hw/exynos4_boards.c | 3 | ||||
| -rw-r--r-- | hw/realview.c | 12 | ||||
| -rw-r--r-- | hw/vexpress.c | 6 |
5 files changed, 18 insertions, 13 deletions
diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 5e5204bbf5..306013aeeb 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -37,7 +37,7 @@ struct arm_boot_info { */ target_phys_addr_t smp_loader_start; target_phys_addr_t smp_bootreg_addr; - target_phys_addr_t smp_priv_base; + target_phys_addr_t gic_cpu_if_addr; int nb_cpus; int board_id; int (*atag_board)(const struct arm_boot_info *info, void *p); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 34a8739e71..2ef25ca9dd 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -43,16 +43,16 @@ static uint32_t bootloader[] = { * location for the kernel secondary CPU entry point. */ static uint32_t smpboot[] = { - 0xe59f201c, /* ldr r2, privbase */ + 0xe59f201c, /* ldr r2, gic_cpu_if */ 0xe59f001c, /* ldr r0, startaddr */ 0xe3a01001, /* mov r1, #1 */ - 0xe5821100, /* str r1, [r2, #256] */ + 0xe5821000, /* str r1, [r2] */ 0xe320f003, /* wfi */ 0xe5901000, /* ldr r1, [r0] */ 0xe1110001, /* tst r1, r1 */ 0x0afffffb, /* beq <wfi> */ 0xe12fff11, /* bx r1 */ - 0, /* privbase: Private memory region base address. */ + 0, /* gic_cpu_if: base address of GIC CPU interface */ 0 /* bootreg: Boot register address is held here */ }; @@ -61,7 +61,7 @@ static void default_write_secondary(CPUState *env, { int n; smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; - smpboot[ARRAY_SIZE(smpboot) - 2] = info->smp_priv_base; + smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; for (n = 0; n < ARRAY_SIZE(smpboot); n++) { smpboot[n] = tswap32(smpboot[n]); } diff --git a/hw/exynos4_boards.c b/hw/exynos4_boards.c index 329efbeba4..553a02b910 100644 --- a/hw/exynos4_boards.c +++ b/hw/exynos4_boards.c @@ -112,7 +112,8 @@ static Exynos4210State *exynos4_boards_init_common( exynos4_board_binfo.kernel_filename = kernel_filename; exynos4_board_binfo.initrd_filename = initrd_filename; exynos4_board_binfo.kernel_cmdline = kernel_cmdline; - exynos4_board_binfo.smp_priv_base = EXYNOS4210_SMP_PRIVATE_BASE_ADDR; + exynos4_board_binfo.gic_cpu_if_addr = + EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n" " kernel_filename: %s\n" diff --git a/hw/realview.c b/hw/realview.c index bcf982fac5..ae1bbcdac3 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -222,21 +222,23 @@ static void realview_init(ram_addr_t ram_size, sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); if (is_mpcore) { + target_phys_addr_t periphbase; dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); if (is_pb) { - realview_binfo.smp_priv_base = 0x1f000000; + periphbase = 0x1f000000; } else { - realview_binfo.smp_priv_base = 0x10100000; + periphbase = 0x10100000; } - sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base); + sysbus_mmio_map(busdev, 0, periphbase); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } - sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, - NULL); + sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); + /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ + realview_binfo.gic_cpu_if_addr = periphbase + 0x100; } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 43ad206f0f..aae9d81707 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -115,6 +115,7 @@ typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, struct VEDBoardInfo { const target_phys_addr_t *motherboard_map; target_phys_addr_t loader_start; + const target_phys_addr_t gic_cpu_if_addr; DBoardInitFn *init; }; @@ -175,8 +176,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); - vexpress_binfo.smp_priv_base = 0x1e000000; - sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base); + sysbus_mmio_map(busdev, 0, 0x1e000000); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } @@ -214,6 +214,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, static const VEDBoardInfo a9_daughterboard = { .motherboard_map = motherboard_legacy_map, .loader_start = 0x60000000, + .gic_cpu_if_addr = 0x1e000100, .init = a9_daughterboard_init, }; @@ -316,6 +317,7 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, vexpress_binfo.loader_start = daughterboard->loader_start; vexpress_binfo.smp_loader_start = map[VE_SRAM]; vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; + vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; arm_load_kernel(first_cpu, &vexpress_binfo); } |