diff options
| -rw-r--r-- | target-i386/cpu.h | 5 | ||||
| -rw-r--r-- | target-i386/helper.c | 1 | ||||
| -rw-r--r-- | target-i386/kvm.c | 15 | ||||
| -rw-r--r-- | target-i386/machine.c | 21 | ||||
| -rw-r--r-- | target-i386/op_helper.c | 6 |
5 files changed, 48 insertions, 0 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 29412dc523..a08ce9d873 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -300,6 +300,10 @@ #define MSR_IA32_PERF_STATUS 0x198 +#define MSR_IA32_MISC_ENABLE 0x1a0 +/* Indicates good rep/movs microcode on some processors: */ +#define MSR_IA32_MISC_ENABLE_DEFAULT 1 + #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) @@ -691,6 +695,7 @@ typedef struct CPUX86State { uint64_t tsc_deadline; uint64_t mcg_status; + uint64_t msr_ia32_misc_enable; /* exception/interrupt handling */ int error_code; diff --git a/target-i386/helper.c b/target-i386/helper.c index 5df40d4661..6c6a1675df 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -98,6 +98,7 @@ void cpu_reset(CPUX86State *env) env->mxcsr = 0x1f80; env->pat = 0x0007040600070406ULL; + env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 90a6ffba02..ddd115c53c 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -61,6 +61,7 @@ static bool has_msr_star; static bool has_msr_hsave_pa; static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; +static bool has_msr_misc_enable; static int lm_capable_kernel; static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) @@ -573,6 +574,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_tsc_deadline = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { + has_msr_misc_enable = true; + continue; + } } } @@ -889,6 +894,10 @@ static int kvm_put_msrs(CPUState *env, int level) if (has_msr_tsc_deadline) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); } + if (has_msr_misc_enable) { + kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, + env->msr_ia32_misc_enable); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1138,6 +1147,9 @@ static int kvm_get_msrs(CPUState *env) if (has_msr_tsc_deadline) { msrs[n++].index = MSR_IA32_TSCDEADLINE; } + if (has_msr_misc_enable) { + msrs[n++].index = MSR_IA32_MISC_ENABLE; + } if (!env->tsc_valid) { msrs[n++].index = MSR_IA32_TSC; @@ -1224,6 +1236,9 @@ static int kvm_get_msrs(CPUState *env) case MSR_MCG_CTL: env->mcg_ctl = msrs[i].data; break; + case MSR_IA32_MISC_ENABLE: + env->msr_ia32_misc_enable = msrs[i].data; + break; default: if (msrs[i].index >= MSR_MC0_CTL && msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { diff --git a/target-i386/machine.c b/target-i386/machine.c index 176d372d1d..d6e98ff37b 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -328,6 +328,24 @@ static const VMStateDescription vmstate_msr_tscdeadline = { } }; +static bool misc_enable_needed(void *opaque) +{ + CPUState *env = opaque; + + return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; +} + +static const VMStateDescription vmstate_msr_ia32_misc_enable = { + .name = "cpu/msr_ia32_misc_enable", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(msr_ia32_misc_enable, CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_cpu = { .name = "cpu", .version_id = CPU_SAVE_VERSION, @@ -441,6 +459,9 @@ static const VMStateDescription vmstate_cpu = { }, { .vmsd = &vmstate_msr_tscdeadline, .needed = tscdeadline_needed, + }, { + .vmsd = &vmstate_msr_ia32_misc_enable, + .needed = misc_enable_needed, } , { /* empty */ } diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 3bb5a919ce..c89e4a49db 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -3280,6 +3280,9 @@ void helper_wrmsr(void) case MSR_TSC_AUX: env->tsc_aux = val; break; + case MSR_IA32_MISC_ENABLE: + env->msr_ia32_misc_enable = val; + break; default: if ((uint32_t)ECX >= MSR_MC0_CTL && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { @@ -3413,6 +3416,9 @@ void helper_rdmsr(void) case MSR_MCG_STATUS: val = env->mcg_status; break; + case MSR_IA32_MISC_ENABLE: + val = env->msr_ia32_misc_enable; + break; default: if ((uint32_t)ECX >= MSR_MC0_CTL && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { |