summaryrefslogtreecommitdiff
path: root/tcg
diff options
context:
space:
mode:
authorPranith Kumar <bobby.prani@gmail.com>2016-07-14 16:20:16 -0400
committerRichard Henderson <rth@twiddle.net>2016-09-16 08:12:11 -0700
commit40f191ab8226fdada185efa49c44b60d8f494890 (patch)
treed7886637fa4b69cd6293dd60c43b72c914845acb /tcg
parentc7a59c2a92592e556b9361437c9c4229917bd1e3 (diff)
tcg/arm: Add support for fence
Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-5-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/arm/tcg-target.inc.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 094f3f804d..ffa0d40660 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0x5bf07ff5,
+ INSN_DMB_MCR = 0xba0f07ee,
+
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -1928,6 +1941,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -2002,6 +2019,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};