diff options
| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-23 17:50:49 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-29 14:13:53 +0100 |
| commit | 87860df5511b972f0234a6b2cfaad5227c79b6b4 (patch) | |
| tree | 7bc7928be60e8a453cd56e30fbc950f0c8a20de5 /target | |
| parent | 96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b (diff) | |
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/translate.c | 41 |
1 files changed, 23 insertions, 18 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 3b1dd59382..9d5bf7a4c2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24999,6 +24999,29 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) */ uint32_t opcode = extract32(ctx->opcode, 0, 6); + if (opcode == OPC__MXU_MUL) { + uint32_t rs, rt, rd, op1; + + rs = extract32(ctx->opcode, 21, 5); + rt = extract32(ctx->opcode, 16, 5); + rd = extract32(ctx->opcode, 11, 5); + op1 = MASK_SPECIAL2(ctx->opcode); + + gen_arith(ctx, op1, rd, rs, rt); + + return; + } + + if (opcode == OPC_MXU_S32M2I) { + gen_mxu_s32m2i(ctx); + return; + } + + if (opcode == OPC_MXU_S32I2M) { + gen_mxu_s32i2m(ctx); + return; + } + switch (opcode) { case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ @@ -25010,18 +25033,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_S32MADDU"); generate_exception_end(ctx, EXCP_RI); break; - case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */ - { - uint32_t rs, rt, rd, op1; - - rs = extract32(ctx->opcode, 21, 5); - rt = extract32(ctx->opcode, 16, 5); - rd = extract32(ctx->opcode, 11, 5); - op1 = MASK_SPECIAL2(ctx->opcode); - - gen_arith(ctx, op1, rd, rs, rt); - } - break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; @@ -25173,12 +25184,6 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_S16SDI"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU_S32M2I: - gen_mxu_s32m2i(ctx); - break; - case OPC_MXU_S32I2M: - gen_mxu_s32i2m(ctx); - break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); |