diff options
| author | Richard Henderson <rth@twiddle.net> | 2017-07-18 10:02:40 -1000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-18 23:39:17 +0200 |
| commit | 1e0b21d856d7654ea683e743e964c3b292122081 (patch) | |
| tree | 6972a3768b19e981129fdb0cdab2cdbb68419893 /target/sh4 | |
| parent | 0f73753d621b2dddc87bc3d8889cab8636d41d15 (diff) | |
target/sh4: Merge DREG into fpr64 routines
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-16-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/sh4')
| -rw-r--r-- | target/sh4/translate.c | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index e5b88ac568..40724819e5 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -334,11 +334,17 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } @@ -357,8 +363,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) #define FREG(x) cpu_fregs[(x) ^ ctx->fbank] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -/* Assumes lsb of (x) is always 0 */ -#define DREG(x) ((x) ^ ctx->fbank) #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -1088,8 +1092,8 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp0 = tcg_temp_new_i64(); fp1 = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp0, DREG(B11_8)); - gen_load_fpr64(ctx, fp1, DREG(B7_4)); + gen_load_fpr64(ctx, fp0, B11_8); + gen_load_fpr64(ctx, fp1, B7_4); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); @@ -1110,7 +1114,7 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); return; } - gen_store_fpr64(ctx, fp0, DREG(B11_8)); + gen_store_fpr64(ctx, fp0, B11_8); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); } else { @@ -1689,7 +1693,7 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp = tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { @@ -1703,7 +1707,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } @@ -1725,9 +1729,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fsqrt_DT(fp, cpu_env, fp); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); @@ -1753,7 +1757,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp = tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } return; @@ -1761,7 +1765,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } |