diff options
| author | Chen Gang <gang.chen.5i5j@gmail.com> | 2015-09-26 07:42:54 +0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-10-07 20:03:15 +1100 |
| commit | f723287944c30f1bf230f08b4fb03d6d11a16504 (patch) | |
| tree | 615769e11cc6bd6400a192f9faa7d4169ffecc83 /target-tilegx | |
| parent | 9ff5b57c219f38f025b95ebf4b593b5d4e828b53 (diff) | |
target-tilegx: Let x1 pipe process bpt instruction only
According to the related document, bpt can be only in x1 pipe.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
| -rw-r--r-- | target-tilegx/translate.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index d7e4d526e2..3566b88f27 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -458,8 +458,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, mnemonic = "flushwb"; goto done0; case OE_RR_X1(ILL): + if (dest == 0x1c && srca == 0x25) { + mnemonic = "bpt"; + goto done2; + } + /* Fall through */ case OE_RR_Y1(ILL): - mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill"); + mnemonic = "ill"; + done2: qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic); return TILEGX_EXCP_OPCODE_UNKNOWN; case OE_RR_X1(MF): |