diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-08-24 08:01:52 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-09-15 07:45:34 -0700 |
| commit | 5151c69abcc049a587b894f0b8e19e1c6d72dc1d (patch) | |
| tree | 8dcfa4e85a9cf7fa9a4d0ea293cf369d0b90d57a /target-tilegx | |
| parent | 0583b2332355dadb2d4681fe5a4eca882eb5b889 (diff) | |
target-tilegx: Handle v4int_l/h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx')
| -rw-r--r-- | target-tilegx/translate.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 7fb2ffb8bb..7719132f89 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1148,10 +1148,18 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V4ADDSC, 0, X1): case OE_RRR(V4ADD, 0, X0): case OE_RRR(V4ADD, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V4INT_H, 0, X0): case OE_RRR(V4INT_H, 0, X1): + tcg_gen_shri_tl(tdest, tsrcb, 32); + tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32); + mnemonic = "v4int_h"; + break; case OE_RRR(V4INT_L, 0, X0): case OE_RRR(V4INT_L, 0, X1): + tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32); + mnemonic = "v4int_l"; + break; case OE_RRR(V4PACKSC, 0, X0): case OE_RRR(V4PACKSC, 0, X1): case OE_RRR(V4SHLSC, 0, X0): |