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authorj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-14 07:07:08 +0000
committerj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-14 07:07:08 +0000
commit6ebbf390003270afece028facef4d9834df81a8c (patch)
treeadc8e9a3d586d5b1b550543fceb6ffdaeda03f6a /target-sh4/op_helper.c
parentd0f48074dbc21248f3b0a9fb48126cb0d95991b5 (diff)
Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4/op_helper.c')
-rw-r--r--target-sh4/op_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 292e9b30df..2535b8d6aa 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -42,7 +42,7 @@ void do_raise_exception(void)
#define SHIFT 3
#include "softmmu_template.h"
-void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
+void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
@@ -53,7 +53,7 @@ void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, is_user, 1);
+ ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */