diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-03-21 13:52:34 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-03-24 11:17:34 +1100 |
| commit | 26a7f1291bb5581e51c413d744207d0a5910ff4c (patch) | |
| tree | d1fcc2a2f3462f6ea266a0efceede3bdefde226d /target-ppc | |
| parent | f401dd32cb8e9ef68bc4f0d600479f670c2bf39a (diff) | |
ppc: Create cpu_ppc_set_papr() helper
And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: removed LPCR setting ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 1 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 23 |
2 files changed, 23 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9ce301f189..a7da0d3e95 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1268,6 +1268,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val); void store_booke_tsr (CPUPPCState *env, target_ulong val); void ppc_tlb_invalidate_all (CPUPPCState *env); void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); +void cpu_ppc_set_papr(PowerPCCPU *cpu); #endif #endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 3ecbd85315..4d82e1c756 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8380,8 +8380,29 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } -#endif /* defined (TARGET_PPC64) */ +#if !defined(CONFIG_USER_ONLY) + +void cpu_ppc_set_papr(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + /* PAPR always has exception vectors in RAM not ROM. To ensure this, + * MSR[IP] should never be set. + * + * We also disallow setting of MSR_HV + */ + env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB); + + /* Tell KVM that we're in PAPR mode */ + if (kvm_enabled()) { + kvmppc_set_papr(cpu); + } +} + +#endif /* !defined(CONFIG_USER_ONLY) */ + +#endif /* defined (TARGET_PPC64) */ /*****************************************************************************/ /* Generic CPU instantiation routine */ |