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authorEfimov Vasily <real@ispras.ru>2016-06-22 15:24:54 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2016-06-29 14:03:46 +0200
commitf999c0de05103ccd91b3efff282eaa1c0ea93015 (patch)
tree211a349b0866d56c77c4802d6e992ed0fc81a7f7 /hw/isa
parent35a6b23c824e54055f1a2ab30fa5b051a82cdda6 (diff)
ICH9 LPC: handle GSI as qdev GPIO
The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/isa')
-rw-r--r--hw/isa/lpc_ich9.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 3bdb78d255..59f15a121e 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -599,6 +599,7 @@ static void ich9_lpc_initfn(Object *obj)
static void ich9_lpc_realize(PCIDevice *d, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
+ DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
@@ -626,6 +627,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
memory_region_add_subregion_overlap(pci_address_space_io(d),
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
1);
+
+ qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
}
static bool ich9_rst_cnt_needed(void *opaque)