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authorBen Widawsky <benjamin.widawsky@intel.com>2015-06-17 15:50:11 -0700
committerBen Widawsky <benjamin.widawsky@intel.com>2015-06-24 16:37:12 -0700
commitd1663ccb4c664b0f544ed5d6f0761f3ae2435199 (patch)
treeb8fa69bdf338b806480a6ab80daa84e267035947 /include
parent9f261dc18dba0aa4dc43fc560d343ba9ffd486e9 (diff)
i965/bxt: Add basic Broxton infrastructure
The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: "Lecluse, Philippe" <Philippe.Lecluse@intel.com> Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/pci_ids/i965_pci_ids.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8d757aaa76..8a42599942 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -128,3 +128,6 @@ CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)")
+CHIPSET(0x0A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x1A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x5A84, bxt, "Intel(R) HD Graphics (Broxton)")