summaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2014-06-10drm: Remove DRM_ARRAY_SIZE() for ARRAY_SIZE()Damien Lespiau19-19/+19
2014-06-10drm: Remove spurious ';'Damien Lespiau7-8/+8
2014-06-10Merge tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/lin...Dave Airlie4-0/+113
2014-06-10Merge tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/lin...Dave Airlie23-680/+1398
2014-06-09drm/panel: simple - Add AUO B133XTN01 panel supportStéphane Marchesin1-0/+25
2014-06-09drm/tegra: sor - Remove obsolete commentThierry Reding1-1/+1
2014-06-09drm/tegra: sor - Enable only the necessary number of lanesThierry Reding1-1/+1
2014-06-09drm/tegra: sor - Power on only the necessary lanesThierry Reding1-3/+17
2014-06-09drm/tegra: sor - Do not program interlaced mode registersThierry Reding1-3/+0
2014-06-09drm/tegra: sor - Do not hardcode link speedThierry Reding1-2/+2
2014-06-09drm/tegra: sor - Do not hardcode number of blank symbolsThierry Reding1-3/+23
2014-06-09drm/tegra: sor - Don't hardcode link parametersThierry Reding1-10/+213
2014-06-09drm/tegra: sor - Change power down orderingStéphane Marchesin1-1/+1
2014-06-09drm/tegra: sor - Fix copy/paste errorStéphane Marchesin1-1/+1
2014-06-09drm/tegra: sor - Remove pixel clock roundingStéphane Marchesin1-3/+0
2014-06-06Merge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-i...Dave Airlie20-216/+957
2014-06-06drm/tegra: sor - Make debugfs setup consistentThierry Reding1-6/+5
2014-06-06drm/tegra: sor - Recursively remove debugfs treeThierry Reding1-1/+1
2014-06-05drm/tegra: dp - Mark the connector as hotplug capableThierry Reding1-0/+1
2014-06-05drm/tegra: dp - Implement hotplug detection in work queueThierry Reding1-10/+20
2014-06-05drm/tegra: Add hardware cursor supportThierry Reding2-3/+138
2014-06-05drm/tegra: Remove host1x drm_bus implementationThierry Reding10-96/+52
2014-06-05drm: Add device registration documentationThierry Reding4-62/+75
2014-06-05drm: Introduce drm_dev_set_unique()Thierry Reding2-6/+44
2014-06-05gpu: host1x: Rename internal functions for clarityThierry Reding1-6/+6
2014-06-05drm/tegra: gem - Make tegra_bo_import() staticThierry Reding1-1/+2
2014-06-05drm/tegra: hdmi - Add Tegra124 supportThierry Reding2-0/+89
2014-06-05drm/tegra: sor - Protect CRC debugfs against enable stateThierry Reding1-24/+45
2014-06-05drm/tegra: dsi - Do not needlessly recompute pclkThierry Reding1-1/+0
2014-06-05drm/tegra: dc - Compute shift clock divider in output driversThierry Reding6-41/+82
2014-06-05drm/tegra: dc - Move around shift clock programmingThierry Reding1-9/+10
2014-06-05drm/tegra: dsi - Reset controller on driver unloadThierry Reding1-0/+1
2014-06-05drm/tegra: dsi - Fix typo when disabling controllerThierry Reding1-1/+1
2014-06-05drm/tegra: dsi - Add enable guardThierry Reding1-0/+11
2014-06-05drm/tegra: dsi - Initialize proper packet sequencesThierry Reding1-4/+46
2014-06-05drm/tegra: dsi - Implement VDD supply supportThierry Reding1-0/+17
2014-06-05drm/tegra: dsi - Remove unneeded codeThierry Reding1-85/+0
2014-06-05drm/tegra: dsi - Use internal pixel formatThierry Reding2-1/+43
2014-06-05drm/tegra: hdmi - Fix disable sequenceThierry Reding1-0/+8
2014-06-05drm/tegra: hdmi - Disable LVDS modeThierry Reding2-1/+10
2014-06-05drm/tegra: hdmi - Use proper power-up sequenceThierry Reding1-0/+11
2014-06-05drm/tegra: hdmi - Clean up clock usageThierry Reding1-14/+6
2014-06-05drm/tegra: hdmi - Reverse regulator enable orderingThierry Reding1-12/+12
2014-06-05drm/tegra: hdmi - Remove duplicate codeThierry Reding1-10/+0
2014-06-05drm/tegra: hdmi - Add connector supply supportThierry Reding1-9/+23
2014-06-05drm/tegra: dc - Use proper H/V ref-to-sync valuesThierry Reding1-3/+2
2014-06-05drm/tegra: dc - Do not touch power control registerThierry Reding1-4/+0
2014-06-05drm/tegra: dc - Reshuffle code to get rid of prototypesThierry Reding2-251/+248
2014-06-05drm/tegra: dc - Rename INVERT_V to V_DIRECTIONThierry Reding2-4/+5
2014-06-05drm/tegra: sor - Add CRC debugfs supportThierry Reding2-0/+125
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 02:12:24 +0000