diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx27.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx27.h | 101 |
1 files changed, 17 insertions, 84 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2e5351..eb09ec09dbe5 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -29,7 +29,6 @@ #endif #define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) @@ -52,6 +51,12 @@ #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) @@ -65,11 +70,13 @@ #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) @@ -87,7 +94,6 @@ #define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX27_SAHB1_SIZE SZ_1M #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) @@ -105,7 +111,6 @@ /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) @@ -123,10 +128,8 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) IMX_IO_P2V(x) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx27_setup_weimcs(size_t cs, @@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_EMMAPRP 51 #define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 -#define MX27_INT_USB1 54 -#define MX27_INT_USB2 55 -#define MX27_INT_USB3 56 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 @@ -249,74 +252,4 @@ static inline void mx27_setup_weimcs(size_t cs, extern int mx27_revision(void); #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR -#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR -#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR -#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR -#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR -#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR -#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR -#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR -#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR -#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR -#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR -#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR -#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR -#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR -#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR -#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR -#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR -#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR -#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR -#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR -#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX27_X_MEMC_SIZE -#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR -#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR -#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR -#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR -#define MXC_INT_I2C2 MX27_INT_I2C2 -#define MXC_INT_GPT6 MX27_INT_GPT6 -#define MXC_INT_GPT5 MX27_INT_GPT5 -#define MXC_INT_GPT4 MX27_INT_GPT4 -#define MXC_INT_RTIC MX27_INT_RTIC -#define MXC_INT_SDHC MX27_INT_SDHC -#define MXC_INT_SDHC3 MX27_INT_SDHC3 -#define MXC_INT_ATA MX27_INT_ATA -#define MXC_INT_UART6 MX27_INT_UART6 -#define MXC_INT_UART5 MX27_INT_UART5 -#define MXC_INT_FEC MX27_INT_FEC -#define MXC_INT_VPU MX27_INT_VPU -#define MXC_INT_USB1 MX27_INT_USB1 -#define MXC_INT_USB2 MX27_INT_USB2 -#define MXC_INT_USB3 MX27_INT_USB3 -#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN -#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM -#define MXC_INT_SAHARA MX27_INT_SAHARA -#define MXC_INT_IIM MX27_INT_IIM -#define MXC_INT_CCM MX27_INT_CCM -#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC -#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX -#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV -#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX -#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX -#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX -#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX -#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 -#define DMA_REQ_NFC MX27_DMA_REQ_NFC -#endif - #endif /* ifndef __MACH_MX27_H__ */ |