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| author | Arnd Bergmann <arnd@arndb.de> | 2017-03-02 17:52:44 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-03-02 17:52:44 +0100 |
| commit | d4b80d9aacfa760cf0f363caec33b6d54f3afa2b (patch) | |
| tree | cbc1f1dc0d41e77dfef8f11d8cd1a2f8efdab624 /arch/x86/kernel/cpu/mcheck/mce-internal.h | |
| parent | b2e3c4319d40c9055c3c587cdb82ba69b50e919d (diff) | |
| parent | 3e011039a3f376f246e662b0e3ffb08018e3416e (diff) | |
Merge branch 'next/late' with mainline
* next/late: (25 commits)
arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
ARM64: dts: meson-gxbb-p200: add ADC laddered keys
ARM64: dts: meson: meson-gx: add the SAR ADC
ARM64: dts: meson-gxl: add the pwm_ao_b pin
ARM64: dts: meson-gx: add the missing pwm_AO_ab node
clk: gxbb: fix CLKID_ETH defined twice
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
clk: gxbb: add the SAR ADC clocks and expose them
dt-bindings: amlogic: Add WeTek boards
ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
dt-bindings: vendor-prefix: Add wetek vendor prefix
ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
ARM64: dts: meson-gxbb-vega-s95: Add LED
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck/mce-internal.h')
0 files changed, 0 insertions, 0 deletions