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authorLinus Walleij <linus.walleij@linaro.org>2015-08-03 09:26:41 +0200
committerOlof Johansson <olof@lixom.net>2015-08-06 10:10:34 +0200
commitbf64dd262eaaece2ff560e86fabf94c6725f3b5c (patch)
tree2caea94309f657027e92aa5c87dbc01959a53eb6 /Documentation
parentc1bfa985ded82cacdfc6403e78f329c44e35534a (diff)
ARM: ux500: add an SMP enablement type and move cpu nodes
The "cpus" node cannot be inside the "soc" node, while this works for the CoreSight blocks, the early boot code will look for "cpus" directly under the root node, so this is a hard convention. So move the CPU nodes. Augment the "reg" property to match what is actually in the hardware: 0x300 and 0x301 respectively. Then add an SMP enablement type to be used by the SMP init code, "ste,dbx500-smp". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index d6b794cef0b8..91e6e5c478d0 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -199,6 +199,7 @@ nodes to be present and contain the properties described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"rockchip,rk3066-smp"
+ "ste,dbx500-smp"
- cpu-release-addr
Usage: required for systems that have an "enable-method"