diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 14:54:21 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 12:40:45 +1000 |
| commit | 53e60da43aee440d3f75000cdd269bd1324a8ad4 (patch) | |
| tree | debcc53c945ff6ffa4ca3f886a86387e7bfeec0c | |
| parent | 437b2296ced574eada632b11346e22f6b0103e17 (diff) | |
drm/nouveau/falcon: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
36 files changed, 640 insertions, 771 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h index 43c18abd4034..d0ce89b5be3a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -4,9 +4,8 @@ void gt215_ce_intr(struct nvkm_falcon *, struct nvkm_fifo_chan *); -extern struct nvkm_oclass gt215_ce_oclass; -extern struct nvkm_oclass gf100_ce0_oclass; -extern struct nvkm_oclass gf100_ce1_oclass; +int gt215_ce_new(struct nvkm_device *, int, struct nvkm_engine **); +int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **); extern struct nvkm_oclass gk104_ce0_oclass; extern struct nvkm_oclass gk104_ce1_oclass; extern struct nvkm_oclass gk104_ce2_oclass; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h index cd113fcbfccb..81c0bc66a9f8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h @@ -4,13 +4,9 @@ #include <core/engine.h> struct nvkm_fifo_chan; -struct nvkm_falcon_data { - bool external; -}; - struct nvkm_falcon { - struct nvkm_engine engine; const struct nvkm_falcon_func *func; + struct nvkm_engine engine; u32 addr; u8 version; @@ -32,32 +28,21 @@ struct nvkm_falcon { } data; }; +int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, + int index, bool enable, u32 addr, struct nvkm_engine **); + struct nvkm_falcon_func { + struct { + u32 *data; + u32 size; + } code; + struct { + u32 *data; + u32 size; + } data; + u32 pmc_enable; + void (*init)(struct nvkm_falcon *); void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *); struct nvkm_sclass sclass[]; }; - -#define nv_falcon(priv) ((struct nvkm_falcon *)priv) - -#define nvkm_falcon_create(a,p,e,c,b,d,i,f,r) \ - nvkm_falcon_create_((a), (p), (e), (c), (b), (d), (i), (f), \ - sizeof(**r),(void **)r) -#define nvkm_falcon_destroy(p) \ - nvkm_engine_destroy(&(p)->engine) -#define nvkm_falcon_init(p) ({ \ - struct nvkm_falcon *_falcon = (p); \ - _nvkm_falcon_init(nv_object(_falcon)); \ -}) -#define nvkm_falcon_fini(p,s) ({ \ - struct nvkm_falcon *_falcon = (p); \ - _nvkm_falcon_fini(nv_object(_falcon), (s)); \ -}) - -int nvkm_falcon_create_(const struct nvkm_falcon_func *, - struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32, bool, const char *, - const char *, int, void **); -#define _nvkm_falcon_dtor _nvkm_engine_dtor -int _nvkm_falcon_init(struct nvkm_object *); -int _nvkm_falcon_fini(struct nvkm_object *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h index 54b7672eed9c..08516ca82e04 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h @@ -1,7 +1,8 @@ #ifndef __NVKM_MSPDEC_H__ #define __NVKM_MSPDEC_H__ -#include <core/engine.h> -extern struct nvkm_oclass g98_mspdec_oclass; -extern struct nvkm_oclass gf100_mspdec_oclass; -extern struct nvkm_oclass gk104_mspdec_oclass; +#include <engine/falcon.h> +int g98_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); +int gt215_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); +int gf100_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); +int gk104_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h index c6c69d0a8d01..85fd306021ac 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h @@ -1,6 +1,7 @@ #ifndef __NVKM_MSPPP_H__ #define __NVKM_MSPPP_H__ -#include <core/engine.h> -extern struct nvkm_oclass g98_msppp_oclass; -extern struct nvkm_oclass gf100_msppp_oclass; +#include <engine/falcon.h> +int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); +int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); +int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h index 1f193b7bd6c5..99757ed96f76 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h @@ -1,7 +1,9 @@ #ifndef __NVKM_MSVLD_H__ #define __NVKM_MSVLD_H__ -#include <core/engine.h> -extern struct nvkm_oclass g98_msvld_oclass; -extern struct nvkm_oclass gf100_msvld_oclass; -extern struct nvkm_oclass gk104_msvld_oclass; +#include <engine/falcon.h> +int g98_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); +int gt215_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); +int mcp89_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); +int gf100_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); +int gk104_msvld_new(struct nvkm_device *, int, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h index 44590a2a479d..7317ef4c0207 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h @@ -1,5 +1,5 @@ #ifndef __NVKM_SEC_H__ #define __NVKM_SEC_H__ -#include <core/engine.h> -extern struct nvkm_oclass g98_sec_oclass; +#include <engine/falcon.h> +int g98_sec_new(struct nvkm_device *, int, struct nvkm_engine **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c index 3abab3992e7c..e45c6d703c00 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -22,30 +22,26 @@ * Authors: Ben Skeggs */ #include <engine/ce.h> -#include <engine/falcon.h> #include "fuc/gf100.fuc3.h" #include <nvif/class.h> -static int -gf100_ce_init(struct nvkm_object *object) +static void +gf100_ce_init(struct nvkm_falcon *ce) { - struct nvkm_falcon *ce = (void *)object; struct nvkm_device *device = ce->engine.subdev.device; - const int idx = nv_engidx(&ce->engine) - NVDEV_ENGINE_CE0; - u32 base = idx * 0x1000; - int ret; - - ret = nvkm_falcon_init(ce); - if (ret) - return ret; - - nvkm_wr32(device, 0x104084 + base, idx); - return 0; + const int index = ce->engine.subdev.index - NVDEV_ENGINE_CE0; + nvkm_wr32(device, ce->addr + 0x084, index); } static const struct nvkm_falcon_func -gf100_ce0_func = { +gf100_ce0 = { + .code.data = gf100_ce_code, + .code.size = sizeof(gf100_ce_code), + .data.data = gf100_ce_data, + .data.size = sizeof(gf100_ce_data), + .pmc_enable = 0x00000040, + .init = gf100_ce_init, .intr = gt215_ce_intr, .sclass = { { -1, -1, FERMI_DMA }, @@ -53,30 +49,14 @@ gf100_ce0_func = { } }; -static int -gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_falcon *ce; - int ret; - - ret = nvkm_falcon_create(&gf100_ce0_func, parent, engine, oclass, - 0x104000, true, "PCE0", "ce0", &ce); - *pobject = nv_object(ce); - if (ret) - return ret; - - nv_subdev(ce)->unit = 0x00000040; - nv_falcon(ce)->code.data = gf100_ce_code; - nv_falcon(ce)->code.size = sizeof(gf100_ce_code); - nv_falcon(ce)->data.data = gf100_ce_data; - nv_falcon(ce)->data.size = sizeof(gf100_ce_data); - return 0; -} - static const struct nvkm_falcon_func -gf100_ce1_func = { +gf100_ce1 = { + .code.data = gf100_ce_code, + .code.size = sizeof(gf100_ce_code), + .data.data = gf100_ce_data, + .data.size = sizeof(gf100_ce_data), + .pmc_enable = 0x00000080, + .init = gf100_ce_init, .intr = gt215_ce_intr, .sclass = { { -1, -1, FERMI_DECOMPRESS }, @@ -84,46 +64,17 @@ gf100_ce1_func = { } }; -static int -gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_ce_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *ce; - int ret; - - ret = nvkm_falcon_create(&gf100_ce1_func, parent, engine, oclass, - 0x105000, true, "PCE1", "ce1", &ce); - *pobject = nv_object(ce); - if (ret) - return ret; - - nv_subdev(ce)->unit = 0x00000080; - nv_falcon(ce)->code.data = gf100_ce_code; - nv_falcon(ce)->code.size = sizeof(gf100_ce_code); - nv_falcon(ce)->data.data = gf100_ce_data; - nv_falcon(ce)->data.size = sizeof(gf100_ce_data); - return 0; + if (index == NVDEV_ENGINE_CE0) { + return nvkm_falcon_new_(&gf100_ce0, device, index, true, + 0x104000, pengine); + } else + if (index == NVDEV_ENGINE_CE1) { + return nvkm_falcon_new_(&gf100_ce1, device, index, true, + 0x105000, pengine); + } + return -ENODEV; } - -struct nvkm_oclass -gf100_ce0_oclass = { - .handle = NV_ENGINE(CE0, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_ce0_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gf100_ce_init, - .fini = _nvkm_falcon_fini, - }, -}; - -struct nvkm_oclass -gf100_ce1_oclass = { - .handle = NV_ENGINE(CE1, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_ce1_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gf100_ce_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 35e4d578b153..f8223d696598 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -61,7 +61,12 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) } static const struct nvkm_falcon_func -gt215_ce_func = { +gt215_ce = { + .code.data = gt215_ce_code, + .code.size = sizeof(gt215_ce_code), + .data.data = gt215_ce_data, + .data.size = sizeof(gt215_ce_data), + .pmc_enable = 0x00802000, .intr = gt215_ce_intr, .sclass = { { -1, -1, GT212_DMA }, @@ -69,36 +74,10 @@ gt215_ce_func = { } }; -static int -gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gt215_ce_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - bool enable = (nv_device(parent)->chipset != 0xaf); - struct nvkm_falcon *ce; - int ret; - - ret = nvkm_falcon_create(>215_ce_func, parent, engine, oclass, - 0x104000, enable, "PCE0", "ce0", &ce); - *pobject = nv_object(ce); - if (ret) - return ret; - - nv_subdev(ce)->unit = 0x00802000; - nv_falcon(ce)->code.data = gt215_ce_code; - nv_falcon(ce)->code.size = sizeof(gt215_ce_code); - nv_falcon(ce)->data.data = gt215_ce_data; - nv_falcon(ce)->data.size = sizeof(gt215_ce_data); - return 0; + return nvkm_falcon_new_(>215_ce, device, index, + (device->chipset != 0xaf), 0x104000, pengine); } - -struct nvkm_oclass -gt215_ce_oclass = { - .handle = NV_ENGINE(CE0, 0xa3), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gt215_ce_ctor, - .dtor = _nvkm_falcon_dtor, - .init = _nvkm_falcon_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7f858efb2c44..0556316e27c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1056,10 +1056,10 @@ nv98_chipset = { // .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .sec = g98_sec_new, -// .msvld = g98_msvld_new, -// .msppp = g98_msppp_new, + .mspdec = g98_mspdec_new, + .sec = g98_sec_new, + .msvld = g98_msvld_new, + .msppp = g98_msppp_new, // .disp = g94_disp_new, // .pm = g84_pm_new, }; @@ -1115,15 +1115,15 @@ nva3_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gt215_ce_new, + .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = gt215_mspdec_new, + .msppp = gt215_msppp_new, + .msvld = gt215_msvld_new, // .pm = gt215_pm_new, // .sw = nv50_sw_new, }; @@ -1148,14 +1148,14 @@ nva5_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gt215_ce_new, + .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = gt215_mspdec_new, + .msppp = gt215_msppp_new, + .msvld = gt215_msvld_new, // .pm = gt215_pm_new, // .sw = nv50_sw_new, }; @@ -1180,14 +1180,14 @@ nva8_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gt215_ce_new, + .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = gt215_mspdec_new, + .msppp = gt215_msppp_new, + .msvld = gt215_msvld_new, // .pm = gt215_pm_new, // .sw = nv50_sw_new, }; @@ -1215,11 +1215,11 @@ nvaa_chipset = { // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = g98_mspdec_new, + .msppp = g98_msppp_new, + .msvld = g98_msvld_new, // .pm = g84_pm_new, -// .sec = g98_sec_new, + .sec = g98_sec_new, // .sw = nv50_sw_new, }; @@ -1246,11 +1246,11 @@ nvac_chipset = { // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = g98_mspdec_new, + .msppp = g98_msppp_new, + .msvld = g98_msvld_new, // .pm = g84_pm_new, -// .sec = g98_sec_new, + .sec = g98_sec_new, // .sw = nv50_sw_new, }; @@ -1274,14 +1274,14 @@ nvaf_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gt215_ce_new, + .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, // .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, -// .mspdec = g98_mspdec_new, -// .msppp = g98_msppp_new, -// .msvld = g98_msvld_new, + .mspdec = gt215_mspdec_new, + .msppp = gt215_msppp_new, + .msvld = mcp89_msvld_new, // .pm = gt215_pm_new, // .sw = nv50_sw_new, }; @@ -1308,15 +1308,15 @@ nvc0_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, -// .ce[1] = gf100_ce1_new, + .ce[0] = gf100_ce_new, + .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf100_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1343,14 +1343,14 @@ nvc1_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, + .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf108_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf108_pm_new, // .sw = gf100_sw_new, }; @@ -1377,14 +1377,14 @@ nvc3_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, + .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1411,15 +1411,15 @@ nvc4_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, -// .ce[1] = gf100_ce1_new, + .ce[0] = gf100_ce_new, + .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1446,15 +1446,15 @@ nvc8_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, -// .ce[1] = gf100_ce1_new, + .ce[0] = gf100_ce_new, + .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf110_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1481,15 +1481,15 @@ nvce_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, -// .ce[1] = gf100_ce1_new, + .ce[0] = gf100_ce_new, + .ce[1] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1516,14 +1516,14 @@ nvcf_chipset = { .therm = gt215_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, + .ce[0] = gf100_ce_new, // .disp = gt215_disp_new, // .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf100_pm_new, // .sw = gf100_sw_new, }; @@ -1548,14 +1548,14 @@ nvd7_chipset = { .mxm = nv50_mxm_new, .therm = gf119_therm_new, .timer = nv41_timer_new, -// .ce[0] = gf100_ce0_new, + .ce[0] = gf100_ce_new, // .disp = gf119_disp_new, // .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf117_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf117_pm_new, // .sw = gf100_sw_new, }; @@ -1582,14 +1582,14 @@ nvd9_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gf100_ce0_new, + .ce[0] = gf100_ce_new, // .disp = gf119_disp_new, // .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf119_gr_new, -// .mspdec = gf100_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gf100_msvld_new, + .mspdec = gf100_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gf100_msvld_new, // .pm = gf117_pm_new, // .sw = gf100_sw_new, }; @@ -1616,16 +1616,16 @@ nve4_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk104_disp_new, // .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, }; @@ -1652,16 +1652,16 @@ nve6_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk104_disp_new, // .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, }; @@ -1688,16 +1688,16 @@ nve7_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk104_disp_new, // .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, }; @@ -1748,16 +1748,16 @@ nvf0_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk110_disp_new, // .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .pm = gk110_pm_new, // .sw = gf100_sw_new, }; @@ -1784,16 +1784,16 @@ nvf1_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk110_disp_new, // .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110b_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .pm = gk110_pm_new, // .sw = gf100_sw_new, }; @@ -1820,16 +1820,16 @@ nv106_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk110_disp_new, // .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .sw = gf100_sw_new, }; @@ -1855,16 +1855,16 @@ nv108_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .ce[0] = gk104_ce0_new, -// .ce[1] = gk104_ce1_new, +// .ce[0] = gk104_ce_new, +// .ce[1] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gk110_disp_new, // .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, -// .mspdec = gk104_mspdec_new, -// .msppp = gf100_msppp_new, -// .msvld = gk104_msvld_new, + .mspdec = gk104_mspdec_new, + .msppp = gf100_msppp_new, + .msvld = gk104_msvld_new, // .sw = gf100_sw_new, }; @@ -1889,7 +1889,7 @@ nv117_chipset = { .pmu = gm107_pmu_new, .therm = gm107_therm_new, .timer = gk20a_timer_new, -// .ce[0] = gk104_ce0_new, +// .ce[0] = gk104_ce_new, // .ce[2] = gk104_ce2_new, // .disp = gm107_disp_new, // .dma = gf119_dma_new, @@ -1917,8 +1917,8 @@ nv124_chipset = { .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, -// .ce[0] = gm204_ce0_new, -// .ce[1] = gm204_ce1_new, +// .ce[0] = gm204_ce_new, +// .ce[1] = gm204_ce_new, // .ce[2] = gm204_ce2_new, // .disp = gm204_disp_new, // .dma = gf119_dma_new, @@ -1946,8 +1946,8 @@ nv126_chipset = { .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, -// .ce[0] = gm204_ce0_new, -// .ce[1] = gm204_ce1_new, +// .ce[0] = gm204_ce_new, +// .ce[1] = gm204_ce_new, // .ce[2] = gm204_ce2_new, // .disp = gm204_disp_new, // .dma = gf119_dma_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 1f273e108618..336964a0cd92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -32,11 +32,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -45,11 +40,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -58,10 +48,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -70,11 +56,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -83,10 +64,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -95,10 +72,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; @@ -107,11 +80,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; - device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; @@ -120,10 +88,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; @@ -132,10 +96,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 414ff61873b9..1162c030f4a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -36,9 +36,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: @@ -50,9 +47,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: @@ -64,9 +58,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: @@ -86,9 +77,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: @@ -100,9 +88,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: @@ -114,9 +99,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; case 0x108: device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -127,9 +109,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index c16d9586708b..b7b10ca427b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -42,9 +42,6 @@ gm100_identify(struct nvkm_device *device) #endif device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; #if 0 - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; case 0x124: @@ -63,9 +60,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; #if 0 - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; case 0x126: @@ -84,9 +78,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; #if 0 - device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; case 0x12b: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 7e2a4a93b2a7..bcbf2d8f692a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -101,10 +101,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; @@ -125,10 +121,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; @@ -137,10 +129,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; @@ -150,10 +138,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; @@ -162,10 +146,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; @@ -174,10 +154,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; @@ -186,10 +162,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; - device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; - device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 3d3e73cfb6b0..e51372bdbf54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -54,10 +54,11 @@ nvkm_falcon_cclass = { }; static void -nvkm_falcon_intr(struct nvkm_subdev *subdev) +nvkm_falcon_intr(struct nvkm_engine *engine) { - struct nvkm_falcon *falcon = (void *)subdev; - struct nvkm_device *device = falcon->engine.subdev.device; + struct nvkm_falcon *falcon = nvkm_falcon(engine); + struct nvkm_subdev *subdev = &falcon->engine.subdev; + struct nvkm_device *device = subdev->device; const u32 base = falcon->addr; u32 dest = nvkm_rd32(device, base + 0x01c); u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); @@ -89,6 +90,27 @@ nvkm_falcon_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(device->fifo, flags, &chan); } +static int +nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend) +{ + struct nvkm_falcon *falcon = nvkm_falcon(engine); + struct nvkm_device *device = falcon->engine.subdev.device; + const u32 base = falcon->addr; + + if (!suspend) { + nvkm_memory_del(&falcon->core); + if (falcon->external) { + vfree(falcon->data.data); + vfree(falcon->code.data); + falcon->code.data = NULL; + } + } + + nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); + nvkm_wr32(device, base + 0x014, 0xffffffff); + return 0; +} + static void * vmemdup(const void *src, size_t len) { @@ -99,23 +121,16 @@ vmemdup(const void *src, size_t len) return p; } -int -_nvkm_falcon_init(struct nvkm_object *object) +static int +nvkm_falcon_oneinit(struct nvkm_engine *engine) { - struct nvkm_falcon *falcon = (void *)object; + struct nvkm_falcon *falcon = nvkm_falcon(engine); struct nvkm_subdev *subdev = &falcon->engine.subdev; struct nvkm_device *device = subdev->device; - const struct firmware *fw; - char name[32] = "internal"; const u32 base = falcon->addr; - int ret, i; u32 caps; - /* enable engine, and determine its capabilities */ - ret = nvkm_engine_init_old(&falcon->engine); - if (ret) - return ret; - + /* determine falcon capabilities */ if (device->chipset < 0xa3 || device->chipset == 0xaa || device->chipset == 0xac) { falcon->version = 0; @@ -134,6 +149,19 @@ _nvkm_falcon_init(struct nvkm_object *object) nvkm_debug(subdev, "secret level: %d\n", falcon->secret); nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit); nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit); + return 0; +} + +static int +nvkm_falcon_init(struct nvkm_engine *engine) +{ + struct nvkm_falcon *falcon = nvkm_falcon(engine); + struct nvkm_subdev *subdev = &falcon->engine.subdev; + struct nvkm_device *device = subdev->device; + const struct firmware *fw; + char name[32] = "internal"; + const u32 base = falcon->addr; + int ret, i; /* wait for 'uc halted' to be signalled before continuing */ if (falcon->secret && falcon->version < 4) { @@ -279,56 +307,46 @@ _nvkm_falcon_init(struct nvkm_object *object) nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ + + if (falcon->func->init) + falcon->func->init(falcon); return 0; } -int -_nvkm_falcon_fini(struct nvkm_object *object, bool suspend) +static void * +nvkm_falcon_dtor(struct nvkm_engine *engine) { - struct nvkm_falcon *falcon = (void *)object; - struct nvkm_device *device = falcon->engine.subdev.device; - const u32 base = falcon->addr; - - if (!suspend) { - nvkm_memory_del(&falcon->core); - if (falcon->external) { - vfree(falcon->data.data); - vfree(falcon->code.data); - falcon->code.data = NULL; - } - } - - nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); - nvkm_wr32(device, base + 0x014, 0xffffffff); - - return nvkm_engine_fini_old(&falcon->engine, suspend); + return nvkm_falcon(engine); } static const struct nvkm_engine_func nvkm_falcon = { + .dtor = nvkm_falcon_dtor, + .oneinit = nvkm_falcon_oneinit, + .init = nvkm_falcon_init, + .fini = nvkm_falcon_fini, + .intr = nvkm_falcon_intr, .fifo.sclass = nvkm_falcon_oclass_get, .cclass = &nvkm_falcon_cclass, }; int -nvkm_falcon_create_(const struct nvkm_falcon_func *func, - struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 addr, bool enable, - const char *iname, const char *fname, - int length, void **pobject) +nvkm_falcon_new_(const struct nvkm_falcon_func *func, + struct nvkm_device *device, int index, bool enable, + u32 addr, struct nvkm_engine **pengine) { struct nvkm_falcon *falcon; - int ret; - - ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, - fname, length, pobject); - falcon = *pobject; - if (ret) - return ret; - falcon->engine.subdev.intr = nvkm_falcon_intr; - falcon->engine.func = &nvkm_falcon; + if (!(falcon = kzalloc(sizeof(*falcon), GFP_KERNEL))) + return -ENOMEM; falcon->func = func; falcon->addr = addr; - return 0; + falcon->code.data = func->code.data; + falcon->code.size = func->code.size; + falcon->data.data = func->data.data; + falcon->data.size = func->data.size; + *pengine = &falcon->engine; + + return nvkm_engine_ctor(&nvkm_falcon, device, index, func->pmc_enable, + enable, &falcon->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild index c59c83a67315..1a7151146e9d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild @@ -1,3 +1,5 @@ +nvkm-y += nvkm/engine/mspdec/base.o nvkm-y += nvkm/engine/mspdec/g98.o +nvkm-y += nvkm/engine/mspdec/gt215.o nvkm-y += nvkm/engine/mspdec/gf100.o nvkm-y += nvkm/engine/mspdec/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c new file mode 100644 index 000000000000..80211f76093b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c @@ -0,0 +1,32 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +int +nvkm_mspdec_new_(const struct nvkm_falcon_func *func, + struct nvkm_device *device, int index, + struct nvkm_engine **pengine) +{ + return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c index f14971783270..1f1a99e927b2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c @@ -21,61 +21,31 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ -#include <engine/mspdec.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -g98_mspdec_init(struct nvkm_object *object) +void +g98_mspdec_init(struct nvkm_falcon *mspdec) { - struct nvkm_falcon *mspdec = (void *)object; struct nvkm_device *device = mspdec->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(mspdec); - if (ret) - return ret; - nvkm_wr32(device, 0x085010, 0x0000ffd2); nvkm_wr32(device, 0x08501c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -g98_mspdec_func = { +g98_mspdec = { + .pmc_enable = 0x01020000, + .init = g98_mspdec_init, .sclass = { { -1, -1, G98_MSPDEC }, - { -1, -1, GT212_MSPDEC }, {} - }, + } }; -static int -g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +g98_mspdec_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *mspdec; - int ret; - - ret = nvkm_falcon_create(&g98_mspdec_func, parent, engine, oclass, - 0x085000, true, "PMSPDEC", "mspdec", &mspdec); - *pobject = nv_object(mspdec); - if (ret) - return ret; - - nv_subdev(mspdec)->unit = 0x01020000; - return 0; + return nvkm_mspdec_new_(&g98_mspdec, device, index, pengine); } - -struct nvkm_oclass -g98_mspdec_oclass = { - .handle = NV_ENGINE(MSPDEC, 0x98), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g98_mspdec_ctor, - .dtor = _nvkm_falcon_dtor, - .init = g98_mspdec_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c index 1296f775ea31..371fd6c3c663 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c @@ -21,60 +21,31 @@ * * Authors: Maarten Lankhorst */ -#include <engine/mspdec.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -gf100_mspdec_init(struct nvkm_object *object) +void +gf100_mspdec_init(struct nvkm_falcon *mspdec) { - struct nvkm_falcon *mspdec = (void *)object; struct nvkm_device *device = mspdec->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(mspdec); - if (ret) - return ret; - nvkm_wr32(device, 0x085010, 0x0000fff2); nvkm_wr32(device, 0x08501c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -gf100_mspdec_func = { +gf100_mspdec = { + .pmc_enable = 0x00020000, + .init = gf100_mspdec_init, .sclass = { { -1, -1, GF100_MSPDEC }, {} } }; -static int -gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_mspdec_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *mspdec; - int ret; - - ret = nvkm_falcon_create(&gf100_mspdec_func, parent, engine, oclass, - 0x085000, true, "PMSPDEC", "mspdec", &mspdec); - *pobject = nv_object(mspdec); - if (ret) - return ret; - - nv_subdev(mspdec)->unit = 0x00020000; - return 0; + return nvkm_mspdec_new_(&gf100_mspdec, device, index, pengine); } - -struct nvkm_oclass -gf100_mspdec_oclass = { - .handle = NV_ENGINE(MSPDEC, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_mspdec_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gf100_mspdec_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c index 315da1695c72..de804a15bfd4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c @@ -21,60 +21,23 @@ * * Authors: Ben Skeggs */ -#include <engine/mspdec.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -gk104_mspdec_init(struct nvkm_object *object) -{ - struct nvkm_falcon *mspdec = (void *)object; - struct nvkm_device *device = mspdec->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(mspdec); - if (ret) - return ret; - - nvkm_wr32(device, 0x085010, 0x0000fff2); - nvkm_wr32(device, 0x08501c, 0x0000fff2); - return 0; -} - static const struct nvkm_falcon_func -gk104_mspdec_func = { +gk104_mspdec = { + .pmc_enable = 0x00020000, + .init = gf100_mspdec_init, .sclass = { { -1, -1, GK104_MSPDEC }, {} } }; -static int -gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gk104_mspdec_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *falcon; - int ret; - - ret = nvkm_falcon_create(&gk104_mspdec_func, parent, engine, oclass, - 0x085000, true, "PMSPDEC", "mspdec", &falcon); - *pobject = nv_object(falcon); - if (ret) - return ret; - - nv_subdev(falcon)->unit = 0x00020000; - return 0; + return nvkm_mspdec_new_(&gk104_mspdec, device, index, pengine); } - -struct nvkm_oclass -gk104_mspdec_oclass = { - .handle = NV_ENGINE(MSPDEC, 0xe0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_mspdec_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gk104_mspdec_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c new file mode 100644 index 000000000000..835631713c95 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c @@ -0,0 +1,43 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin + */ +#include "priv.h" + +#include <nvif/class.h> + +static const struct nvkm_falcon_func +gt215_mspdec = { + .pmc_enable = 0x01020000, + .init = g98_mspdec_init, + .sclass = { + { -1, -1, GT212_MSPDEC }, + {} + } +}; + +int +gt215_mspdec_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) +{ + return nvkm_mspdec_new_(>215_mspdec, device, index, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h new file mode 100644 index 000000000000..d518af4bc9de --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h @@ -0,0 +1,11 @@ +#ifndef __NVKM_MSPDEC_PRIV_H__ +#define __NVKM_MSPDEC_PRIV_H__ +#include <engine/mspdec.h> + +int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, + int index, struct nvkm_engine **); + +void g98_mspdec_init(struct nvkm_falcon *); + +void gf100_mspdec_init(struct nvkm_falcon *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild index 4576a9eee39d..3ea7eafb408f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild @@ -1,2 +1,4 @@ +nvkm-y += nvkm/engine/msppp/base.o nvkm-y += nvkm/engine/msppp/g98.o +nvkm-y += nvkm/engine/msppp/gt215.o nvkm-y += nvkm/engine/msppp/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c new file mode 100644 index 000000000000..bfae5e60e925 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c @@ -0,0 +1,31 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +int +nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + int index, struct nvkm_engine **pengine) +{ + return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c index 314736d6aa5b..73f633ae2ee7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -21,61 +21,31 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ -#include <engine/msppp.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -g98_msppp_init(struct nvkm_object *object) +void +g98_msppp_init(struct nvkm_falcon *msppp) { - struct nvkm_falcon *msppp = (void *)object; struct nvkm_device *device = msppp->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(msppp); - if (ret) - return ret; - nvkm_wr32(device, 0x086010, 0x0000ffd2); nvkm_wr32(device, 0x08601c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -g98_msppp_func = { +g98_msppp = { + .pmc_enable = 0x00400002, + .init = g98_msppp_init, .sclass = { { -1, -1, G98_MSPPP }, - { -1, -1, GT212_MSPPP }, {} } }; -static int -g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +g98_msppp_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *msppp; - int ret; - - ret = nvkm_falcon_create(&g98_msppp_func, parent, engine, oclass, - 0x086000, true, "PMSPPP", "msppp", &msppp); - *pobject = nv_object(msppp); - if (ret) - return ret; - - nv_subdev(msppp)->unit = 0x00400002; - return 0; + return nvkm_msppp_new_(&g98_msppp, device, index, pengine); } - -struct nvkm_oclass -g98_msppp_oclass = { - .handle = NV_ENGINE(MSPPP, 0x98), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g98_msppp_ctor, - .dtor = _nvkm_falcon_dtor, - .init = g98_msppp_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c index f977c2adf9d2..c42c0c07e2db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -21,60 +21,31 @@ * * Authors: Maarten Lankhorst */ -#include <engine/msppp.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -gf100_msppp_init(struct nvkm_object *object) +static void +gf100_msppp_init(struct nvkm_falcon *msppp) { - struct nvkm_falcon *msppp = (void *)object; struct nvkm_device *device = msppp->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(msppp); - if (ret) - return ret; - nvkm_wr32(device, 0x086010, 0x0000fff2); nvkm_wr32(device, 0x08601c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -gf100_msppp_func = { +gf100_msppp = { + .pmc_enable = 0x00000002, + .init = gf100_msppp_init, .sclass = { { -1, -1, GF100_MSPPP }, {} } }; -static int -gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_msppp_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *msppp; - int ret; - - ret = nvkm_falcon_create(&gf100_msppp_func, parent, engine, oclass, - 0x086000, true, "PMSPPP", "msppp", &msppp); - *pobject = nv_object(msppp); - if (ret) - return ret; - - nv_subdev(msppp)->unit = 0x00000002; - return 0; + return nvkm_msppp_new_(&gf100_msppp, device, index, pengine); } - -struct nvkm_oclass -gf100_msppp_oclass = { - .handle = NV_ENGINE(MSPPP, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_msppp_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gf100_msppp_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c new file mode 100644 index 000000000000..00e7795f1d51 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c @@ -0,0 +1,43 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin + */ +#include "priv.h" + +#include <nvif/class.h> + +static const struct nvkm_falcon_func +gt215_msppp = { + .pmc_enable = 0x00400002, + .init = g98_msppp_init, + .sclass = { + { -1, -1, GT212_MSPPP }, + {} + } +}; + +int +gt215_msppp_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) +{ + return nvkm_msppp_new_(>215_msppp, device, index, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h new file mode 100644 index 000000000000..37a91f9d9181 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h @@ -0,0 +1,9 @@ +#ifndef __NVKM_MSPPP_PRIV_H__ +#define __NVKM_MSPPP_PRIV_H__ +#include <engine/msppp.h> + +int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, + int index, struct nvkm_engine **); + +void g98_msppp_init(struct nvkm_falcon *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild index 0c9811009e28..28c8ecd27b6d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild @@ -1,3 +1,6 @@ +nvkm-y += nvkm/engine/msvld/base.o nvkm-y += nvkm/engine/msvld/g98.o +nvkm-y += nvkm/engine/msvld/gt215.o +nvkm-y += nvkm/engine/msvld/mcp89.o nvkm-y += nvkm/engine/msvld/gf100.o nvkm-y += nvkm/engine/msvld/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c new file mode 100644 index 000000000000..745bbb653dc0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c @@ -0,0 +1,31 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +int +nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device, + int index, struct nvkm_engine **pengine) +{ + return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 0ee767373f79..47e2929bfaf0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c @@ -21,62 +21,31 @@ * * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin */ -#include <engine/msvld.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -g98_msvld_init(struct nvkm_object *object) +void +g98_msvld_init(struct nvkm_falcon *msvld) { - struct nvkm_falcon *msvld = (void *)object; struct nvkm_device *device = msvld->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(msvld); - if (ret) - return ret; - nvkm_wr32(device, 0x084010, 0x0000ffd2); nvkm_wr32(device, 0x08401c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -g98_msvld_func = { +g98_msvld = { + .pmc_enable = 0x04008000, + .init = g98_msvld_init, .sclass = { { -1, -1, G98_MSVLD }, - { -1, -1, GT212_MSVLD }, - { -1, -1, IGT21A_MSVLD }, {} } }; -static int -g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +g98_msvld_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *msvld; - int ret; - - ret = nvkm_falcon_create(&g98_msvld_func, parent, engine, oclass, - 0x084000, true, "PMSVLD", "msvld", &msvld); - *pobject = nv_object(msvld); - if (ret) - return ret; - - nv_subdev(msvld)->unit = 0x04008000; - return 0; + return nvkm_msvld_new_(&g98_msvld, device, index, pengine); } - -struct nvkm_oclass -g98_msvld_oclass = { - .handle = NV_ENGINE(MSVLD, 0x98), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g98_msvld_ctor, - .dtor = _nvkm_falcon_dtor, - .init = g98_msvld_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index 839d648dcfdf..1ac581ba9f96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c @@ -21,60 +21,31 @@ * * Authors: Maarten Lankhorst */ -#include <engine/msvld.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -gf100_msvld_init(struct nvkm_object *object) +void +gf100_msvld_init(struct nvkm_falcon *msvld) { - struct nvkm_falcon *msvld = (void *)object; struct nvkm_device *device = msvld->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(msvld); - if (ret) - return ret; - nvkm_wr32(device, 0x084010, 0x0000fff2); nvkm_wr32(device, 0x08401c, 0x0000fff2); - return 0; } static const struct nvkm_falcon_func -gf100_msvld_func = { +gf100_msvld = { + .pmc_enable = 0x00008000, + .init = gf100_msvld_init, .sclass = { { -1, -1, GF100_MSVLD }, {} } }; -static int -gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_msvld_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *msvld; - int ret; - - ret = nvkm_falcon_create(&gf100_msvld_func, parent, engine, oclass, - 0x084000, true, "PMSVLD", "msvld", &msvld); - *pobject = nv_object(msvld); - if (ret) - return ret; - - nv_subdev(msvld)->unit = 0x00008000; - return 0; + return nvkm_msvld_new_(&gf100_msvld, device, index, pengine); } - -struct nvkm_oclass -gf100_msvld_oclass = { - .handle = NV_ENGINE(MSVLD, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_msvld_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gf100_msvld_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index 74bdca359d4a..4bba16e0f560 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c @@ -21,60 +21,23 @@ * * Authors: Ben Skeggs */ -#include <engine/msvld.h> -#include <engine/falcon.h> +#include "priv.h" #include <nvif/class.h> -static int -gk104_msvld_init(struct nvkm_object *object) -{ - struct nvkm_falcon *msvld = (void *)object; - struct nvkm_device *device = msvld->engine.subdev.device; - int ret; - - ret = nvkm_falcon_init(msvld); - if (ret) - return ret; - - nvkm_wr32(device, 0x084010, 0x0000fff2); - nvkm_wr32(device, 0x08401c, 0x0000fff2); - return 0; -} - static const struct nvkm_falcon_func -gk104_msvld_func = { +gk104_msvld = { + .pmc_enable = 0x00008000, + .init = gf100_msvld_init, .sclass = { { -1, -1, GK104_MSVLD }, {} } }; -static int -gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gk104_msvld_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *msvld; - int ret; - - ret = nvkm_falcon_create(&gk104_msvld_func, parent, engine, oclass, - 0x084000, true, "PMSVLD", "msvld", &msvld); - *pobject = nv_object(msvld); - if (ret) - return ret; - - nv_subdev(msvld)->unit = 0x00008000; - return 0; + return nvkm_msvld_new_(&gk104_msvld, device, index, pengine); } - -struct nvkm_oclass -gk104_msvld_oclass = { - .handle = NV_ENGINE(MSVLD, 0xe0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_msvld_ctor, - .dtor = _nvkm_falcon_dtor, - .init = gk104_msvld_init, - .fini = _nvkm_falcon_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c new file mode 100644 index 000000000000..e17cb5605b2d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c @@ -0,0 +1,43 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin + */ +#include "priv.h" + +#include <nvif/class.h> + +static const struct nvkm_falcon_func +gt215_msvld = { + .pmc_enable = 0x04008000, + .init = g98_msvld_init, + .sclass = { + { -1, -1, GT212_MSVLD }, + {} + } +}; + +int +gt215_msvld_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) +{ + return nvkm_msvld_new_(>215_msvld, device, index, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c new file mode 100644 index 000000000000..511800f6a43b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c @@ -0,0 +1,43 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin + */ +#include "priv.h" + +#include <nvif/class.h> + +static const struct nvkm_falcon_func +mcp89_msvld = { + .pmc_enable = 0x04008000, + .init = g98_msvld_init, + .sclass = { + { -1, -1, IGT21A_MSVLD }, + {} + } +}; + +int +mcp89_msvld_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) +{ + return nvkm_msvld_new_(&mcp89_msvld, device, index, pengine); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h new file mode 100644 index 000000000000..9dc1da67d929 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h @@ -0,0 +1,11 @@ +#ifndef __NVKM_MSVLD_PRIV_H__ +#define __NVKM_MSVLD_PRIV_H__ +#include <engine/msvld.h> + +int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, + int index, struct nvkm_engine **); + +void g98_msvld_init(struct nvkm_falcon *); + +void gf100_msvld_init(struct nvkm_falcon *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index aae0e85b1075..1ec4f4fde1c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs */ #include <engine/sec.h> -#include <engine/falcon.h> #include <engine/fifo.h> #include "fuc/g98.fuc0s.h" @@ -61,7 +60,12 @@ g98_sec_intr(struct nvkm_falcon *sec, struct nvkm_fifo_chan *chan) } static const struct nvkm_falcon_func -g98_sec_func = { +g98_sec = { + .code.data = g98_sec_code, + .code.size = sizeof(g98_sec_code), + .data.data = g98_sec_data, + .data.size = sizeof(g98_sec_data), + .pmc_enable = 0x00004000, .intr = g98_sec_intr, .sclass = { { -1, -1, G98_SEC }, @@ -69,35 +73,10 @@ g98_sec_func = { } }; -static int -g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +g98_sec_new(struct nvkm_device *device, int index, + struct nvkm_engine **pengine) { - struct nvkm_falcon *sec; - int ret; - - ret = nvkm_falcon_create(&g98_sec_func, parent, engine, oclass, - 0x087000, true, "PSEC", "sec", &sec); - *pobject = nv_object(sec); - if (ret) - return ret; - - nv_subdev(sec)->unit = 0x00004000; - nv_falcon(sec)->code.data = g98_sec_code; - nv_falcon(sec)->code.size = sizeof(g98_sec_code); - nv_falcon(sec)->data.data = g98_sec_data; - nv_falcon(sec)->data.size = sizeof(g98_sec_data); - return 0; + return nvkm_falcon_new_(&g98_sec, device, index, + true, 0x087000, pengine); } - -struct nvkm_oclass -g98_sec_oclass = { - .handle = NV_ENGINE(SEC, 0x98), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g98_sec_ctor, - .dtor = _nvkm_falcon_dtor, - .init = _nvkm_falcon_init, - .fini = _nvkm_falcon_fini, - }, -}; |