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authorVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>2005-10-30 14:59:38 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-30 17:37:12 -0800
commit30037f66ce63b6b7ca1fbfb06605b831f4a60df6 (patch)
tree48645e204613332df510b42f56655d06d9200a33
parentf014a556e714dfb02502e3be6146a39ca625f33c (diff)
[PATCH] x86: when L3 is present show its size in /proc/cpuinfo
The code that prints the cache size assumes that L3 always lives in chipset and is shared across CPUs. Which is not really true. I think all the cachesizes reported by cpuid are in the processor itself. The attached patch changes the code to reflect that. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--arch/i386/kernel/cpu/intel_cacheinfo.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index c802206274c2..7cc84a4a6df9 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
if ( l3 )
printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
- /*
- * This assumes the L3 cache is shared; it typically lives in
- * the northbridge. The L1 caches are included by the L2
- * cache, and so should not be included for the purpose of
- * SMP switching weights.
- */
- c->x86_cache_size = l2 ? l2 : (l1i+l1d);
+ c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
}
return l2;