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authorHongbo Zhang <hongbo.zhang@freescale.com>2014-01-16 14:10:53 +0800
committerVinod Koul <vinod.koul@intel.com>2014-01-20 13:13:22 +0530
commit0ca583a239a854fd403bf8b659cdff8c603372c9 (patch)
treea495b019353c869454da1942965955eb38cdbfc6
parent5f9e685a0d463666af080250b2ece11bc81acacd (diff)
DMA: Freescale: change BWC from 256 bytes to 1024 bytes
Freescale DMA has a feature of BandWidth Control (ab. BWC), which is currently 256 bytes and should be changed to 1024 bytes for best DMA throughput. Changing BWC from 256 to 1024 will improve DMA performance much, in cases whatever one channel is running or multi channels are running simultanously, large or small buffers are copied. And this change doesn't impact memory access performance remarkably, lmbench tests show that for some cases the memory performance are decreased very slightly, while the others are even better. Tested on T4240. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/fsldma.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 1ffc24484d23..d56e83599825 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -41,7 +41,7 @@
* channel is allowed to transfer before the DMA engine pauses
* the current channel and switches to the next channel
*/
-#define FSL_DMA_MR_BWC 0x08000000
+#define FSL_DMA_MR_BWC 0x0A000000
/* Special MR definition for MPC8349 */
#define FSL_DMA_MR_EOTIE 0x00000080