diff options
author | Nicolas Pitre <nico@cam.org> | 2008-04-24 02:04:54 +0200 |
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committer | Lennert Buytenhek <buytenh@marvell.com> | 2008-06-22 22:44:58 +0200 |
commit | 6c386e58aadb90fb5d8b5be979e02d74f8be52fe (patch) | |
tree | 89ddc09277ad4191aa5bfd12db20302544ec2294 /arch/arm/mm/proc-xscale.S | |
parent | 79e90dd5aa95adfdc3117db8a559da3d0195ba58 (diff) |
[ARM] Feroceon: speed up flushing of the entire cache
Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.
This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
0 files changed, 0 insertions, 0 deletions