diff options
Diffstat (limited to 'hw/xfree86/os-support')
| -rw-r--r-- | hw/xfree86/os-support/bus/460gxPCI.c | 42 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/460gxPCI.h | 4 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/e8870PCI.c | 14 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/e8870PCI.h | 4 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/zx1PCI.c | 157 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/zx1PCI.h | 2 | ||||
| -rw-r--r-- | hw/xfree86/os-support/linux/lnx_ia64.c | 45 | ||||
| -rw-r--r-- | hw/xfree86/os-support/shared/ia64Pci.c | 81 | ||||
| -rw-r--r-- | hw/xfree86/os-support/shared/ia64Pci.h | 41 |
9 files changed, 318 insertions, 72 deletions
diff --git a/hw/xfree86/os-support/bus/460gxPCI.c b/hw/xfree86/os-support/bus/460gxPCI.c index 3b16f401a..af4e230e6 100644 --- a/hw/xfree86/os-support/bus/460gxPCI.c +++ b/hw/xfree86/os-support/bus/460gxPCI.c @@ -201,32 +201,46 @@ Get460GXBridgeResources(int bus, * the chipset scan is to be stopped, or FALSE if the scan is to move on to the * next chipset. */ + Bool -xf86PreScan460GX(void) +xorgProbe460GX(scanpciWrapperOpt flags) { pciBusInfo_t *pBusInfo; PCITAG tag; - CARD32 tmp; - int i, devno; /* Bus zero should already be set up */ if (!(pBusInfo = pciBusInfo[0])) { cbn_460gx = -1; return FALSE; } - /* First look for a 460GX's primary host bridge */ tag = PCI_MAKE_TAG(0, 0x10, 0); - if (pciReadLong(tag, PCI_ID_REG) != DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) { - cbn_460gx = -1; - return FALSE; + if (pciReadLong(tag, PCI_ID_REG) == DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) { + return TRUE; } + cbn_460gx = -1; + + return FALSE; +} + +void +xf86PreScan460GX(void) +{ + pciBusInfo_t *pBusInfo; + PCITAG tag; + CARD32 tmp; + int i, devno; + + if (!(pBusInfo = pciBusInfo[0])) + return; + /* Get CBN (Chipset bus number) */ + tag = PCI_MAKE_TAG(0, 0x10, 0); if (!(cbn_460gx = (unsigned int)pciReadByte(tag, CBN))) { /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } if (pciNumBuses <= cbn_460gx) @@ -242,7 +256,7 @@ xf86PreScan460GX(void) if (pciReadLong(tag, PCI_ID_REG) != DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) { /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } /* @@ -257,7 +271,7 @@ xf86PreScan460GX(void) DEVID(VENDOR_INTEL, CHIP_460GX_SAC)) { /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } if (devno == 0x10) @@ -278,7 +292,7 @@ xf86PreScan460GX(void) if (cbdevs_460gx & (1 << devno)) { /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } /* @@ -294,7 +308,7 @@ xf86PreScan460GX(void) if (cbdevs_460gx & (1 << devno)) { /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } /* @@ -310,7 +324,7 @@ xf86PreScan460GX(void) break; /* Sanity check failed */ cbn_460gx = -1; - return TRUE; + return; } } @@ -337,7 +351,7 @@ xf86PreScan460GX(void) break; } - return TRUE; + return; } /* This does some 460GX-related processing after the PCI bus scan */ diff --git a/hw/xfree86/os-support/bus/460gxPCI.h b/hw/xfree86/os-support/bus/460gxPCI.h index 2ae9c3528..9459705d0 100644 --- a/hw/xfree86/os-support/bus/460gxPCI.h +++ b/hw/xfree86/os-support/bus/460gxPCI.h @@ -29,8 +29,10 @@ #define PCI_460GX_H 1 #include <X11/Xdefs.h> +#include <Pci.h> -Bool xf86PreScan460GX(void); +Bool xorgProbe460GX(scanpciWrapperOpt flags); +void xf86PreScan460GX(void); void xf86PostScan460GX(void); #endif diff --git a/hw/xfree86/os-support/bus/e8870PCI.c b/hw/xfree86/os-support/bus/e8870PCI.c index adbd189f1..9eb34a67a 100644 --- a/hw/xfree86/os-support/bus/e8870PCI.c +++ b/hw/xfree86/os-support/bus/e8870PCI.c @@ -34,17 +34,23 @@ #include "Pci.h" Bool -xf86PreScanE8870(void) +xorgProbeE8870(scanpciWrapperOpt flags) { PCITAG tag; /* Look for an E8870's Hub interface */ tag = PCI_MAKE_TAG(0, 0x1E, 0); - if (pciReadLong(tag, PCI_ID_REG) != DEVID(VENDOR_INTEL, CHIP_82801_P2P)) - return FALSE; + if (pciReadLong(tag, PCI_ID_REG) == DEVID(VENDOR_INTEL, CHIP_82801_P2P)) + return TRUE; + + return FALSE; +} +void +xf86PreScanE8870(void) +{ /* XXX Fill me in... */ - return TRUE; + return; } void diff --git a/hw/xfree86/os-support/bus/e8870PCI.h b/hw/xfree86/os-support/bus/e8870PCI.h index b910bcfd8..2d16077ac 100644 --- a/hw/xfree86/os-support/bus/e8870PCI.h +++ b/hw/xfree86/os-support/bus/e8870PCI.h @@ -29,8 +29,10 @@ #define PCI_E8870_H 1 #include <X11/Xdefs.h> +#include <Pci.h> -Bool xf86PreScanE8870(void); +Bool xorgProbeE8870(scanpciWrapperOpt flags); +void xf86PreScanE8870(void); void xf86PostScanE8870(void); #endif diff --git a/hw/xfree86/os-support/bus/zx1PCI.c b/hw/xfree86/os-support/bus/zx1PCI.c index 16640b95b..ce3260c26 100644 --- a/hw/xfree86/os-support/bus/zx1PCI.c +++ b/hw/xfree86/os-support/bus/zx1PCI.c @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.3 2003/07/17 15:08:22 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.8 2004/01/16 15:39:38 tsi Exp $ */ /* * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. * @@ -97,9 +97,10 @@ #define LBA_PORT5_CNTRL 0x1228U #define LBA_PORT6_CNTRL 0x1230U #define LBA_PORT7_CNTRL 0x1238U -#define LBA_ROPE_RESET 0x01UL -#define LBA_CLEAR_ERROR 0x10UL -#define LBA_HARD_FAIL 0x40UL +#define LBA_RESET_FUNCTION 0x0000000001UL +#define LBA_CLEAR_ERROR 0x0000000010UL +#define LBA_HARD_FAIL 0x0000000040UL +#define LBA_RESET_COMPLETE 0x0100000000UL #define ROPE_PAGE_CONTROL 0x1418U @@ -117,8 +118,11 @@ #define IOA_SUBORDINATE_BUS 0x0059U #define IOA_CONTROL 0x0108U -#define IOA_FORWARD_VGA 0x08UL -#define IOA_HARD_FAIL 0x40UL +#define IOA_RESET_FUNCTION 0x0000000001UL +#define IOA_FORWARD_VGA 0x0000000008UL +#define IOA_CLEAR_ERROR 0x0000000010UL +#define IOA_HARD_FAIL 0x0000000040UL +#define IOA_RESET_COMPLETE 0x0100000000UL #define IOA_LMMIO_BASE 0x0200U #define IOA_LMMIO_MASK 0x0208U @@ -134,12 +138,33 @@ #define IOA_ELMMIO_MASK 0x0258U #define IOA_EIOS_BASE 0x0260U #define IOA_EIOS_MASK 0x0268U - +#define IOA_GLOBAL_MASK 0x0270U #define IOA_SLAVE_CONTROL 0x0278U #define IOA_VGA_PEER_ENABLE 0x2000UL #define IOA_MSI_BASE 0x0280U #define IOA_MSI_MASK 0x0288U +#define IOA_DMA_BASE 0x02B0U +#define IOA_DMA_MASK 0x02B8U + +#define IOA_ERROR_CONFIG 0x0680U +#define IOA_ERROR_PIOWRITE 0x0001UL +#define IOA_ERROR_PIOREAD 0x0002UL +#define IOA_ERROR_DMAWRITE 0x0004UL +#define IOA_ERROR_DMAREAD 0x0008UL +#define IOA_ERROR_CONFIG_MASTER 0x0010UL +#define IOA_ERROR_SMART 0x0020UL +#define IOA_ERROR_FATAL_SERR 0x0040UL +#define IOA_ERROR_ASSERT_SERR 0x0080UL +/* ? 0x0100UL */ +#define IOA_ERROR_LOOPBACK 0x0200UL +#define IOA_ERROR_CONFIG_TARGET 0x0400UL +#define IOA_ERROR_IO_MASTER 0x0800UL +#define IOA_ERROR_IO_TARGET 0x1000UL +#define IOA_ERROR_MEM_MASTER 0x2000UL +#define IOA_ERROR_MEM_TARGET 0x4000UL +#define IOA_ERROR_HF_IO_FATAL 0x8000UL + #define RANGE_ENABLE 0x01UL /* In various base registers */ #define IO_MASK ((1UL << 16) - 1UL) @@ -156,10 +181,15 @@ static CARD8 *pZX1mio = NULL, *pZX1ioa = NULL; -static INT8 zx1_ropemap[8]; /* One for each (potential) rope */ -static CARD64 zx1_lbacntl[8]; /* " " " " " */ +/* Per-rope data */ +static INT8 zx1_ropemap[8]; +static CARD32 zx1_pciids[8]; +static CARD64 zx1_lbacntl[8]; static int zx1_busno[8], zx1_subno[8]; +/* Array of Booleans for non-empty buses */ +static INT8 zx1_busnmpt[MAX_PCI_BUSES]; + static pciBusFuncs_t zx1BusFuncs; static int zx1_fakebus = -1; static Bool zx1_hasvga = FALSE; @@ -292,7 +322,8 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value) * SLAVE_CONTROL register. */ tmp1 = MIO_QUAD(VGA_ROUTE); - tmp2 = IOA_QUAD(ropenum, IOA_CONTROL); + tmp2 = IOA_QUAD(ropenum, IOA_CONTROL) & + ~(IOA_RESET_FUNCTION | IOA_CLEAR_ERROR); if ((tmp1 & VGA_ENABLE) && ((tmp1 & 0x07UL) == ropenum)) { current |= PCI_PCI_BRIDGE_VGA_EN; if ((mask & PCI_PCI_BRIDGE_VGA_EN) && @@ -315,8 +346,9 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value) MIO_QUAD(VGA_ROUTE) = 0UL; tmp3 = IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL); if (tmp3 & IOA_FORWARD_VGA) - IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) = - tmp3 & ~IOA_FORWARD_VGA; + IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) = tmp3 & + ~(IOA_RESET_FUNCTION | IOA_FORWARD_VGA | + IOA_CLEAR_ERROR); } if (!(tmp2 & IOA_FORWARD_VGA)) { tmp2 |= IOA_FORWARD_VGA; @@ -329,7 +361,7 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value) /* Move on to master abort failure enablement */ tmp1 = MIO_QUAD((ropenum << 3) + LBA_PORT0_CNTRL) & - ~(LBA_ROPE_RESET | LBA_CLEAR_ERROR); + ~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR); if ((tmp1 & LBA_HARD_FAIL) || (tmp2 & IOA_HARD_FAIL)) { current |= PCI_PCI_BRIDGE_MASTER_ABORT_EN; if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) && @@ -391,14 +423,15 @@ GetZX1BridgeResources(int bus, static CARD32 zx1FakeReadLong(PCITAG tag, int offset) { - FatalError("zx1FakeReadLong(0x%X, 0x%X) called\n", tag, offset); + FatalError("zx1FakeReadLong(0x%lX, 0x%X) called\n", + (unsigned long)tag, offset); } static void zx1FakeWriteLong(PCITAG tag, int offset, CARD32 val) { - FatalError("zx1FakeWriteLong(0x%X, 0x%X, 0x%08X) called\n", - tag, offset, val); + FatalError("zx1FakeWriteLong(0x%lX, 0x%X, 0x%08X) called\n", + (unsigned long)tag, offset, val); } static void @@ -432,25 +465,19 @@ static pciBusInfo_t zx1FakeBus = { NULL, /* bridge -- dynamically set */ }; -/* - * This checks for, and validates, the presence of the ZX1 chipset, and sets - * pZX1mio to a non-NULL pointer accordingly. This function is called before - * the server's PCI bus scan and returns TRUE if the chipset scan is to be - * stopped, or FALSE if the scan is to move on to the next chipset. - */ -Bool +void xf86PreScanZX1(void) { resRange range; unsigned long mapSize = xf86getpagesize(); unsigned long tmp, base, ioaaddr; - unsigned long flagsd = 0, based = 0, lastd = 0, maskd = 0, routed = 0; - unsigned long flags0 = 0, base0 = 0, last0 = 0, mask0 = 0, route0 = 0; - unsigned long flags1 = 0, base1 = 0, last1 = 0, mask1 = 0, route1 = 0; - unsigned long flags2 = 0, base2 = 0, last2 = 0, mask2 = 0, route2 = 0; - unsigned long flags3 = 0, base3 = 0, last3 = 0, mask3 = 0, route3 = 0; - unsigned long flagsg = 0, baseg = 0, lastg = 0, maskg = 0, routeg = 0; - unsigned long flagsl = 0, basel = 0, lastl = 0; + unsigned long flagsd, based, lastd, maskd, routed; + unsigned long flags0, base0, last0, mask0, route0; + unsigned long flags1, base1, last1, mask1, route1; + unsigned long flags2, base2, last2, mask2, route2; + unsigned long flags3, base3, last3, mask3, route3; + unsigned long flagsg, baseg, lastg, maskg, routeg; + unsigned long flagsl, basel, lastl; int i, rope; /* Map mio registers (minimum 8k) */ @@ -458,16 +485,16 @@ xf86PreScanZX1(void) mapSize = MIO_SIZE; if (!(pZX1mio = xf86MapVidMem(-1, VIDMEM_MMIO, MIO_BASE, mapSize))) - return FALSE; + return; - /* Look for ZX1's SBA and IOC */ + /* Look for ZX1's SBA and IOC */ /* XXX What about Dino? */ if ((MIO_LONG(MIO_FUNCTION0 + PCI_ID_REG) != DEVID(VENDOR_HP, CHIP_ZX1_SBA)) || (MIO_LONG(MIO_FUNCTION1 + PCI_ID_REG) != DEVID(VENDOR_HP, CHIP_ZX1_IOC))) { xf86UnMapVidMem(-1, pZX1mio, mapSize); pZX1mio = NULL; - return FALSE; + return; } /* Map rope configuration space */ @@ -477,7 +504,7 @@ xf86PreScanZX1(void) !(pZX1ioa = xf86MapVidMem(-1, VIDMEM_MMIO, ioaaddr, IOA_SIZE))) { xf86UnMapVidMem(-1, pZX1mio, mapSize); pZX1mio = NULL; - return TRUE; + return; } for (i = 0; i < 8; i++) { @@ -519,16 +546,17 @@ xf86PreScanZX1(void) /* Prevent hard-fails */ zx1_lbacntl[i] = MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) & - ~(LBA_ROPE_RESET | LBA_CLEAR_ERROR); + ~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR); if (zx1_lbacntl[i] & LBA_HARD_FAIL) MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) = zx1_lbacntl[i] & ~LBA_HARD_FAIL; /* Poke for an ioa */ - tmp = IOA_LONG(i, PCI_ID_REG); - switch ((CARD32)tmp) { + zx1_pciids[i] = IOA_LONG(i, PCI_ID_REG); + switch (zx1_pciids[i]) { case DEVID(VENDOR_HP, CHIP_ELROY): - case DEVID(VENDOR_HP, CHIP_ZX1_LBA): + case DEVID(VENDOR_HP, CHIP_ZX1_LBA): /* Mercury */ + case DEVID(VENDOR_HP, CHIP_ZX1_AGP8): /* QuickSilver */ /* Expected vendor/device IDs */ zx1_busno[i] = (unsigned int)IOA_BYTE(i, IOA_SECONDARY_BUS); @@ -537,10 +565,10 @@ xf86PreScanZX1(void) break; default: - if ((CARD16)(tmp + 1U) > (CARD16)1U) + if ((CARD16)(zx1_pciids[i] + 1U) > (CARD16)1U) xf86MsgVerb(X_NOTICE, 0, "HP ZX1: Unexpected vendor/device id 0x%08X" - " on rope %d\n", (CARD32)tmp, i); + " on rope %d\n", zx1_pciids[i], i); /* Nobody home, or not the "right" kind of rope guest */ /* @@ -587,6 +615,14 @@ xf86PreScanZX1(void) * ones. */ + flagsd = 0; based = 0; lastd = 0; maskd = 0; routed = 0; + flags0 = 0; base0 = 0; last0 = 0; mask0 = 0; route0 = 0; + flags1 = 0; base1 = 0; last1 = 0; mask1 = 0; route1 = 0; + flags2 = 0; base2 = 0; last2 = 0; mask2 = 0; route2 = 0; + flags3 = 0; base3 = 0; last3 = 0; mask3 = 0; route3 = 0; + flagsg = 0; baseg = 0; lastg = 0; maskg = 0; routeg = 0; + flagsl = 0; basel = 0; lastl = 0; + if ((tmp = MIO_QUAD(IOS_DIST_BASE)) & RANGE_ENABLE) { flagsd = RANGE_ENABLE; maskd = MIO_QUAD(IOS_DIST_MASK); @@ -882,7 +918,7 @@ xf86PreScanZX1(void) nRange = 0; - return TRUE; + return; } /* This is called to finalise the results of a PCI bus scan */ @@ -896,6 +932,9 @@ xf86PostScanZX1(void) if (!pZX1mio) return; + (void)memset(zx1_busnmpt, FALSE, sizeof(zx1_busnmpt)); + pBusInfo = pciBusInfo[0]; + /* * Certain 2.4 & 2.5 Linux kernels add fake PCI devices. Remove them to * prevent any possible interference with our PCI validation. @@ -907,9 +946,11 @@ xf86PostScanZX1(void) ppPCI = ppPCI2 = xf86scanpci(0); /* Recursion is only apparent */ while ((pPCI = *ppPCI2++)) { switch (pPCI->pci_device_vendor) { - case DEVID(VENDOR_HP, CHIP_ZX1_SBA): - case DEVID(VENDOR_HP, CHIP_ZX1_IOC): - case DEVID(VENDOR_HP, CHIP_ZX1_LBA): + case DEVID(VENDOR_HP, CHIP_ELROY): + case DEVID(VENDOR_HP, CHIP_ZX1_SBA): /* Pluto function 0 */ + case DEVID(VENDOR_HP, CHIP_ZX1_IOC): /* Pluto function 1 */ + case DEVID(VENDOR_HP, CHIP_ZX1_LBA): /* Mercury */ + case DEVID(VENDOR_HP, CHIP_ZX1_AGP8): /* QuickSilver */ xfree(pPCI); /* Remove it */ continue; @@ -917,6 +958,8 @@ xf86PostScanZX1(void) *ppPCI++ = pPCI; idx++; + zx1_busnmpt[pPCI->busnum] = TRUE; + if (zx1_hasvga) continue; @@ -941,8 +984,8 @@ xf86PostScanZX1(void) } /* - * Restore hard-fail settings and figure out the actual subordinate bus - * numbers. + * Restore hard-fail settings and figure out the actual secondary and + * subordinate bus numbers. */ for (i = 0; i < 8; i++) { if (zx1_ropemap[i] != i) @@ -956,6 +999,14 @@ xf86PostScanZX1(void) if (zx1_fakebus <= zx1_subno[i]) zx1_fakebus = zx1_subno[i] + 1; + + while (!zx1_busnmpt[zx1_busno[i]]) { + if (zx1_busno[i]) /* Info for bus zero is in static storage */ + xfree(pciBusInfo[zx1_busno[i]]); + pciBusInfo[zx1_busno[i]++] = NULL; + if (zx1_busno[i] > zx1_subno[i]) + break; + } } if (zx1_fakebus >= pciNumBuses) { @@ -965,13 +1016,13 @@ xf86PostScanZX1(void) } /* Set up our extra bus functions */ - zx1BusFuncs = *(pciBusInfo[0]->funcs); + zx1BusFuncs = *(pBusInfo->funcs); zx1BusFuncs.pciControlBridge = ControlZX1Bridge; zx1BusFuncs.pciGetBridgeResources = GetZX1BridgeResources; /* Set up our own fake bus to act as the root segment */ - zx1FakeBus.configMech = pciBusInfo[0]->configMech; - zx1FakeBus.numDevices = pciBusInfo[0]->numDevices; + zx1FakeBus.configMech = pBusInfo->configMech; + zx1FakeBus.numDevices = pBusInfo->numDevices; zx1FakeBus.primary_bus = zx1_fakebus; pciBusInfo[zx1_fakebus] = &zx1FakeBus; @@ -1006,7 +1057,8 @@ xf86PostScanZX1(void) /* Add a fake PCI-to-PCI bridge to represent each active rope */ for (i = 0; i < 8; i++) { - if ((zx1_ropemap[i] != i) || !(pBusInfo = pciBusInfo[zx1_busno[i]])) + if ((zx1_ropemap[i] != i) || (zx1_busno[i] > zx1_subno[i]) || + !(pBusInfo = pciBusInfo[zx1_busno[i]])) continue; if (++idx >= MAX_PCI_DEVICES) @@ -1016,7 +1068,7 @@ xf86PostScanZX1(void) pPCI->devnum = i | 0x10; /* pPCI->funcnum = 0; */ pPCI->tag = PCI_MAKE_TAG(zx1_fakebus, pPCI->devnum, 0); - pPCI->pci_device_vendor = DEVID(VENDOR_HP, CHIP_ZX1_LBA); + pPCI->pci_device_vendor = zx1_pciids[i]; pPCI->pci_base_class = PCI_CLASS_BRIDGE; pPCI->pci_sub_class = PCI_SUBCLASS_BRIDGE_PCI; pPCI->pci_header_type = 1; @@ -1032,6 +1084,9 @@ xf86PostScanZX1(void) /* Plug in chipset routines */ pBusInfo->funcs = &zx1BusFuncs; + /* Set bridge control register for scanpci utility */ + pPCI->pci_bridge_control = ControlZX1Bridge(zx1_busno[i], 0, 0); + #ifdef OLD_FORMAT xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x " "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n", diff --git a/hw/xfree86/os-support/bus/zx1PCI.h b/hw/xfree86/os-support/bus/zx1PCI.h index b1e8a95b5..f46a68a30 100644 --- a/hw/xfree86/os-support/bus/zx1PCI.h +++ b/hw/xfree86/os-support/bus/zx1PCI.h @@ -30,7 +30,7 @@ #include <X11/Xdefs.h> -Bool xf86PreScanZX1(void); +void xf86PreScanZX1(void); void xf86PostScanZX1(void); #endif diff --git a/hw/xfree86/os-support/linux/lnx_ia64.c b/hw/xfree86/os-support/linux/lnx_ia64.c new file mode 100644 index 000000000..8d0976a36 --- /dev/null +++ b/hw/xfree86/os-support/linux/lnx_ia64.c @@ -0,0 +1,45 @@ +/* + * Copyright 2004, Egbert Eich + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * EGBERT EICH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CON- + * NECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Egbert Eich shall not + * be used in advertising or otherwise to promote the sale, use or other deal- + *ings in this Software without prior written authorization from Egbert Eich. + * + */ + +#include <sys/types.h> +#include <sys/stat.h> +#include <unistd.h> + +#include "ia64Pci.h" +#include "Pci.h" + +#if defined OS_PROBE_PCI_CHIPSET +IA64Chipset OS_PROBE_PCI_CHIPSET(scanpciWrapperOpt flags) +{ + struct stat unused; + + if (!stat("/proc/bus/mckinley/zx1",&unused) + || !stat("/proc/bus/mckinley/zx2",&unused)) + return ZX1_CHIPSET; + + return NONE_CHIPSET; +} +#endif diff --git a/hw/xfree86/os-support/shared/ia64Pci.c b/hw/xfree86/os-support/shared/ia64Pci.c new file mode 100644 index 000000000..d0046a7f2 --- /dev/null +++ b/hw/xfree86/os-support/shared/ia64Pci.c @@ -0,0 +1,81 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ia64Pci.c,v 1.3 2003/02/23 20:26:49 tsi Exp $ */ +/* + * Copyright (C) 2002-2003 The XFree86 Project, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the XFree86 Project shall + * not be used in advertising or otherwise to promote the sale, use or other + * dealings in this Software without prior written authorization from the + * XFree86 Project. + */ + +/* + * This file contains the glue needed to support various IA-64 chipsets. + */ + +#include "460gxPCI.h" +#include "e8870PCI.h" +#include "zx1PCI.h" +#include "Pci.h" +#include "ia64Pci.h" + +void +ia64ScanPCIWrapper(scanpciWrapperOpt flags) +{ + static IA64Chipset chipset = NONE_CHIPSET; + + if (flags == SCANPCI_INIT) { + + /* PCI configuration space probes should be done first */ + if (xorgProbe460GX(flags)) { + chipset = I460GX_CHIPSET; + xf86PreScan460GX(); + return; + } else if (xorgProbeE8870(flags)) { + chipset = E8870_CHIPSET; + xf86PreScanE8870(); + return; + } +#ifdef OS_PROBE_PCI_CHIPSET + chipset = OS_PROBE_PCI_CHIPSET(flags); + switch (chipset) { + case ZX1_CHIPSET: + xf86PreScanZX1(); + return; + default: + return; + } +#endif + } else /* if (flags == SCANPCI_TERM) */ { + + switch (chipset) { + case I460GX_CHIPSET: + xf86PostScan460GX(); + return; + case E8870_CHIPSET: + xf86PostScanE8870(); + return; + case ZX1_CHIPSET: + xf86PostScanZX1(); + return; + default: + return; + } + } +} diff --git a/hw/xfree86/os-support/shared/ia64Pci.h b/hw/xfree86/os-support/shared/ia64Pci.h new file mode 100644 index 000000000..1ee2fc091 --- /dev/null +++ b/hw/xfree86/os-support/shared/ia64Pci.h @@ -0,0 +1,41 @@ +/* + * Copyright 2004, Egbert Eich + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * EGBERT EICH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CON- + * NECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Egbert Eich shall not + * be used in advertising or otherwise to promote the sale, use or other deal- + *ings in this Software without prior written authorization from Egbert Eich. + * + */ +#ifndef _IA64_PCI_H +# define _IA64_PCI_H + +#include "Pci.h" + +typedef enum { + NONE_CHIPSET, + I460GX_CHIPSET, + E8870_CHIPSET, + ZX1_CHIPSET +} IA64Chipset; + +# ifdef OS_PROBE_PCI_CHIPSET +extern IA64Chipset OS_PROBE_PCI_CHIPSET(scanpciWrapperOpt flags); +# endif +#endif |