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2015-08-28pmu/gk104: implement a hackish workaround for a hw bugBen Skeggs1-0/+51
Only a handful of machines have this enabled by default, where it's been proven to work. The workaround can be explicitly enabled with a module option also. Still waiting on feedback from NVIDIA for a proper idea of exactly what this fix is doing, and how to implement it properly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28disp/dp: gm1xx appears to have same dp lane ordering as gm2xxBen Skeggs3-10/+7
Fixes 2-lane DP on Quadro K620. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28disp/dp: fix some tx_pu mishandlingBen Skeggs4-6/+7
We only need to mask 0x0f on GM2xx, and want to keep the higher bits on earlier cards. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28bios/dp: use alternate set of drvctl values where necessaryBen Skeggs1-5/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28bios/dcb: accept "maxwell" lane count values for dcb 4.0Ben Skeggs2-27/+25
We previously assumed that the values "2" and "4" were new in DCB 4.1, however, there's at least one GM107 DCB 4.0 board (Quadro K620) that uses the newer values. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28fb/sddr3: add WR/CWL values seen on a GK208Ilia Mirkin1-2/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28nv46: Change mc subdev oclass from nv44 to nv4cHans de Goede1-1/+1
MSI interrupts appear to not work for nv46 based cards. Change the mc subdev oclass for these cards from nv44 to nv4c, the nv4c mc code is identical to the nv44 mc code except that it does not use msi (it does not define a msi_rearm callback). BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=90435 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gf100: only use PBFB_BROADCAST.PM_UNK100 for PBFB signalsSamuel Pitoiset5-54/+19
High level hardware events related to PBFB will monitor all partitions. While we are at it, fix bitfield for this mux. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gf100: remove multiple definitions of GPC_DOM signal 0x0eSamuel Pitoiset1-5/+4
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gf100: remove undefined TEX.PM_UNKC8 muxSamuel Pitoiset1-4/+0
This mux only exists on GF108+ (except for GF110 one), but since it is not used by the userspace we can drop it for now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow zeroed signals to enable sourcesSamuel Pitoiset1-2/+2
Hardware signals index 0x00 are defined for some domains and they have to be allowed to enable sources like the others. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/nv50: TPC[0x3] must be used for PGRAPH muxs on G80Samuel Pitoiset3-20/+28
I thought that using TPC[0x0] like for G84:GT215 was sufficient on G80, but it's actually not the case. According to NVIDIA PerfKit on Windows, we have to configure PGRAPH related muxs on TPC[0x3] for this chipset. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/nv50: fix wrong addr for ZCULL source on G80:GT215Samuel Pitoiset1-1/+1
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28bios: add opcodes 0x73 and 0x77Ilia Mirkin1-0/+37
No known VBIOSes use these, but they are present in the actual VBIOS table parsing logic. No harm in adding these too. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28platform: recognize GM20BAlexandre Courbot1-0/+1
Allow the platform driver to recognize GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28device: recognize GM20BAlexandre Courbot1-0/+20
Recognize GM20B and assign the right engines and subdevs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28gr: add GM20B supportAlexandre Courbot10-6/+217
Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28fifo: add GM20B fifoAlexandre Courbot5-1/+41
GM20B has a 512-channels FIFO similar to GK104. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28gr/gk20a: use same initialization sequence as nvgpuAlexandre Courbot5-30/+421
GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28gr: use NVIDIA-provided external firmwaresAlexandre Courbot2-12/+20
NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gk104: add compute signals/sourcesSamuel Pitoiset3-1/+93
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gk104: re-use gf100_pm_ctor()Samuel Pitoiset3-56/+14
gk104_pm_ctor() is equal to gf100_pm_ctor(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/nv40: rename pcounter domains to 'pc' instead of 'pm'Samuel Pitoiset1-1/+1
This trivial patch makes thing more consistent since hardware signals names are prefixed by 'pcXX'. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: expose name of domainsSamuel Pitoiset2-0/+2
This is going to be very useful for GF100+ because each GPC can have its own domain of counters. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/clk: fix tstate to pstate calculationWei Ni1-1/+1
According to the tstate calculation in nvkm_clk_tstate(), the range of tstate is from -(clk->state_nr - 1) to 0, it mean the tstate is negative value. But in nvkm_pstate_work(), it use (clk->state_nr - 1 - clk->tstate) to limit pstate, it's not correct. This patch fix it to use (clk->state_nr - 1 + clk->tstate) to limit pstate. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: some fixes related to sourcesSamuel Pitoiset1-5/+16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: fix signals/sources for GT200+Samuel Pitoiset2-6/+5
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gf100: add compute signals/sourcesSamuel Pitoiset7-5/+282
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. This commit also adds a new class for GF108 and GF117. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/gf100: allow to share GPC, HUB and PART domainsSamuel Pitoiset4-19/+34
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: stack perfdom class under perfmonBen Skeggs2-21/+43
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: swap perfmon/perfdom code to avoid forward decl in next commitBen Skeggs1-175/+175
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm/nv50: add compute and graphics signals/sourcesSamuel Pitoiset8-11/+485
These signals and sources have been reverse engineered from NVIDIA PerfKit (Windows) and CUPTI (Linux), they will be used to build complex hardware events from the userspace. This commit also adds a new class for GT200. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow the userspace to configure sourcesSamuel Pitoiset3-10/+95
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow to configure domains instead of simple countersSamuel Pitoiset7-170/+293
Configuring counters from the userspace require the kernel to handle some logic related to performance counters. Basically, it has to find a free slot to assign a counter, to handle extra counting modes like B4/B6 and it must return and error when it can't configure a counter. In my opinion, the kernel should not handle all of that logic but it should only write the configuration sent by the userspace without checking anything. In other words, it should overwrite the configuration even if it's already counting and do not return any errors. This patch allows the userspace to configure a domain instead of separate counters. This has the advantage to move all of the logic to the userspace. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow the userspace to schedule hardware countersSamuel Pitoiset3-25/+48
This adds a new method NVIF_PERFCTR_V0_INIT which starts a batch of hardware counters for sampling. This will allow the userspace to start a monitoring session using the INIT method and to stop it with SAMPLE, for example before and after a frame is rendered. This commit temporarily breaks nv_perfmon but this is going to be fixed with the upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: implement NVIF_PERFMON_V0_QUERY_SOURCE methodSamuel Pitoiset2-0/+89
This allows to query the ID, the mask and the user-readable name of sources for each signal. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow to query the number of sources for a signalSamuel Pitoiset2-4/+21
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: add concept of sourcesSamuel Pitoiset3-4/+103
A source (or multiplexer) is a tuple addr+mask+shift which allows to control a block of signals. The maximum number of sources that a signal can define is arbitrary limited to 8 and this should be large enough. This patch allows to define multi-level of sources for a signal. Each different sources are stored to a global list and will be exposed to the userspace through the nvif interface in order to avoid conflicts. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow to monitor hardware signal index 0x00Samuel Pitoiset3-6/+10
This signal index must be always allowed even if it's not clearly defined in a domain in order to monitor a counter like 0x03020100 because it's the default value of signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: use hardware signals indexes instead of user-readable namesSamuel Pitoiset3-46/+23
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: change signal iter to u16Samuel Pitoiset4-11/+12
16 bits is large enough to store the maximum number of signals available for one domain (i.e. 256). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: allow to query signals by domainSamuel Pitoiset3-74/+150
This will allow to configure performance counters with hardware signal indexes instead of user-readable names in an upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: implement NVIF_PERFMON_V0_QUERY_DOMAIN methodSamuel Pitoiset2-1/+96
This allows to query the number of available domains, including the number of hardware counter and the number of signals per domain. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: prevent creating a perfctr object when signals are not foundSamuel Pitoiset1-2/+4
Since a new class has been introduced to query signals, we can now return an error when the userspace wants to monitor unknown signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: reorganize the nvif interfaceSamuel Pitoiset4-24/+57
This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be used in order to query domains, signals and sources. This separates the querying and the counting interface. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: remove unused nvkm_perfsig_wrap() functionSamuel Pitoiset2-24/+0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28pm: remove pmu signalsSamuel Pitoiset8-151/+1
PDAEMON signals don't have to be exposed by the perfmon engine. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28clk/nv50: Enable user reclocking for NVA0Roy Spliet1-1/+2
Tested on a few cards. Probably works quite well for most, given they should all be GDDR3. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28fb/gddr3: Add a few CL and WR entries observed on GTX260Roy Spliet1-4/+4
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28fb/ramnv50: GDDR3 script for NVA0Roy Spliet1-25/+104
This looks surprisingly similar to scripts on earlier cards as well but they don't seem to work just yet. That... and I don't have any, which makes it a tough job to reverse engineer. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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