diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2015-01-16 00:53:53 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2015-01-16 12:39:35 -0800 |
| commit | 127c9724924f9d93652540a9f3ff8306bb1aacd4 (patch) | |
| tree | f752f6da1d739c1377f686079a3ed9eaac5b2488 | |
| parent | faaca237341abc0f784edfb16df50104110365b8 (diff) | |
i965: Fix some oddities in FB_WRITE register width and execution size.
Previously, we generated this for FB writes in SIMD16 mode:
load_payload(16) vgrf5@8+0.0:F, vgrf1:F, vgrf2:F, vgrf3:F, vgrf4:F
fb_write(8) (null):UD, vgrf5@8+0.0:F 1sthalf
The LOAD_PAYLOAD's destination had its register width set to 8, and the
FB_WRITE had its execution size set to 8. This seems wrong, and while
it probably doesn't affect anything, we should fix it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 4f899748e9..8aafbef723 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3460,6 +3460,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1, fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F); load = emit(LOAD_PAYLOAD(payload, sources, length)); payload.reg = virtual_grf_alloc(load->regs_written); + payload.width = dispatch_width; load->dst = payload; write = emit(FS_OPCODE_FB_WRITE, reg_undef, payload); write->base_mrf = -1; @@ -3468,6 +3469,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1, load = emit(LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F), sources, length)); write = emit(FS_OPCODE_FB_WRITE); + write->exec_size = dispatch_width; write->base_mrf = 1; } |