diff options
Diffstat (limited to 'r300reg.xml')
| -rw-r--r-- | r300reg.xml | 6928 |
1 files changed, 6928 insertions, 0 deletions
diff --git a/r300reg.xml b/r300reg.xml new file mode 100644 index 0000000..648adbe --- /dev/null +++ b/r300reg.xml @@ -0,0 +1,6928 @@ +<?xml version="1.0" encoding="UTF-8"?> +<database xmlns="http://nouveau.freedesktop.org/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="rules-ng.xsd"> +<domain name="R300" /> + +<enum name="ENUM0"> + <value value="0" name="NORMAL_OPERATION"><doc>Normal operation.</doc></value> + <value value="1" name="RESOLVE_OPERATION"><doc>Resolve operation.</doc></value> +</enum> +<enum name="ENUM1"> + <value value="0" name="1"><doc>1.0</doc></value> + <value value="1" name="2"><doc>2.2</doc></value> +</enum> +<enum name="ENUM2"> + <value value="0" name="ADD_AND_CLAMP"><doc>Add and Clamp</doc></value> + <value value="1" name="ADD_BUT_NO_CLAMP"><doc>Add but no Clamp</doc></value> + <value value="2" name="SUBTRACT_DST_FROM_SRC"><doc>Subtract Dst from Src, and Clamp</doc></value> + <value value="3" name="SUBTRACT_DST_FROM_SRC"><doc>Subtract Dst from Src, and don`t Clamp</doc></value> + <value value="4" name="MINIMUM_OF_SRC"><doc>Minimum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)</doc></value> + <value value="5" name="MAXIMUM_OF_SRC"><doc>Maximum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)</doc></value> + <value value="6" name="SUBTRACT_SRC_FROM_DST"><doc>Subtract Src from Dst, and Clamp</doc></value> + <value value="7" name="SUBTRACT_SRC_FROM_DST"><doc>Subtract Src from Dst, and don`t Clamp</doc></value> +</enum> +<enum name="ENUM3"> + <value value="1" name="D3D_ZERO"><doc>D3D_ZERO</doc></value> + <value value="2" name="D3D_ONE"><doc>D3D_ONE</doc></value> + <value value="3" name="D3D_SRCCOLOR"><doc>D3D_SRCCOLOR</doc></value> + <value value="4" name="D3D_INVSRCCOLOR"><doc>D3D_INVSRCCOLOR</doc></value> + <value value="5" name="D3D_SRCALPHA"><doc>D3D_SRCALPHA</doc></value> + <value value="6" name="D3D_INVSRCALPHA"><doc>D3D_INVSRCALPHA</doc></value> + <value value="7" name="D3D_DESTALPHA"><doc>D3D_DESTALPHA</doc></value> + <value value="8" name="D3D_INVDESTALPHA"><doc>D3D_INVDESTALPHA</doc></value> + <value value="9" name="D3D_DESTCOLOR"><doc>D3D_DESTCOLOR</doc></value> + <value value="10" name="D3D_INVDESTCOLOR"><doc>D3D_INVDESTCOLOR</doc></value> + <value value="11" name="D3D_SRCALPHASAT"><doc>D3D_SRCALPHASAT</doc></value> + <value value="12" name="D3D_BOTHSRCALPHA"><doc>D3D_BOTHSRCALPHA</doc></value> + <value value="13" name="D3D_BOTHINVSRCALPHA"><doc>D3D_BOTHINVSRCALPHA</doc></value> + <value value="32" name="GL_ZERO"><doc>GL_ZERO</doc></value> + <value value="33" name="GL_ONE"><doc>GL_ONE</doc></value> + <value value="34" name="GL_SRC_COLOR"><doc>GL_SRC_COLOR</doc></value> + <value value="35" name="GL_ONE_MINUS_SRC_COLOR"><doc>GL_ONE_MINUS_SRC_COLOR</doc></value> + <value value="36" name="GL_DST_COLOR"><doc>GL_DST_COLOR</doc></value> + <value value="37" name="GL_ONE_MINUS_DST_COLOR"><doc>GL_ONE_MINUS_DST_COLOR</doc></value> + <value value="38" name="GL_SRC_ALPHA"><doc>GL_SRC_ALPHA</doc></value> + <value value="39" name="GL_ONE_MINUS_SRC_ALPHA"><doc>GL_ONE_MINUS_SRC_ALPHA</doc></value> + <value value="40" name="GL_DST_ALPHA"><doc>GL_DST_ALPHA</doc></value> + <value value="41" name="GL_ONE_MINUS_DST_ALPHA"><doc>GL_ONE_MINUS_DST_ALPHA</doc></value> + <value value="42" name="GL_SRC_ALPHA_SATURATE"><doc>GL_SRC_ALPHA_SATURATE</doc></value> + <value value="43" name="GL_CONSTANT_COLOR"><doc>GL_CONSTANT_COLOR</doc></value> + <value value="44" name="GL_ONE_MINUS_CONSTANT_COLOR"><doc>GL_ONE_MINUS_CONSTANT_COLOR</doc></value> + <value value="45" name="GL_CONSTANT_ALPHA"><doc>GL_CONSTANT_ALPHA</doc></value> + <value value="46" name="GL_ONE_MINUS_CONSTANT_ALPHA"><doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc></value> +</enum> +<enum name="ENUM4"> + <value value="1" name="D3D_ZERO"><doc>D3D_ZERO</doc></value> + <value value="2" name="D3D_ONE"><doc>D3D_ONE</doc></value> + <value value="3" name="D3D_SRCCOLOR"><doc>D3D_SRCCOLOR</doc></value> + <value value="4" name="D3D_INVSRCCOLOR"><doc>D3D_INVSRCCOLOR</doc></value> + <value value="5" name="D3D_SRCALPHA"><doc>D3D_SRCALPHA</doc></value> + <value value="6" name="D3D_INVSRCALPHA"><doc>D3D_INVSRCALPHA</doc></value> + <value value="7" name="D3D_DESTALPHA"><doc>D3D_DESTALPHA</doc></value> + <value value="8" name="D3D_INVDESTALPHA"><doc>D3D_INVDESTALPHA</doc></value> + <value value="9" name="D3D_DESTCOLOR"><doc>D3D_DESTCOLOR</doc></value> + <value value="10" name="D3D_INVDESTCOLOR"><doc>D3D_INVDESTCOLOR</doc></value> + <value value="32" name="GL_ZERO"><doc>GL_ZERO</doc></value> + <value value="33" name="GL_ONE"><doc>GL_ONE</doc></value> + <value value="34" name="GL_SRC_COLOR"><doc>GL_SRC_COLOR</doc></value> + <value value="35" name="GL_ONE_MINUS_SRC_COLOR"><doc>GL_ONE_MINUS_SRC_COLOR</doc></value> + <value value="36" name="GL_DST_COLOR"><doc>GL_DST_COLOR</doc></value> + <value value="37" name="GL_ONE_MINUS_DST_COLOR"><doc>GL_ONE_MINUS_DST_COLOR</doc></value> + <value value="38" name="GL_SRC_ALPHA"><doc>GL_SRC_ALPHA</doc></value> + <value value="39" name="GL_ONE_MINUS_SRC_ALPHA"><doc>GL_ONE_MINUS_SRC_ALPHA</doc></value> + <value value="40" name="GL_DST_ALPHA"><doc>GL_DST_ALPHA</doc></value> + <value value="41" name="GL_ONE_MINUS_DST_ALPHA"><doc>GL_ONE_MINUS_DST_ALPHA</doc></value> + <value value="43" name="GL_CONSTANT_COLOR"><doc>GL_CONSTANT_COLOR</doc></value> + <value value="44" name="GL_ONE_MINUS_CONSTANT_COLOR"><doc>GL_ONE_MINUS_CONSTANT_COLOR</doc></value> + <value value="45" name="GL_CONSTANT_ALPHA"><doc>GL_CONSTANT_ALPHA</doc></value> + <value value="46" name="GL_ONE_MINUS_CONSTANT_ALPHA"><doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc></value> +</enum> +<enum name="ENUM5"> + <value value="0" name="DISABLE"><doc>Disable</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> +</enum> +<enum name="ENUM6"> + <value value="0" name="DISABLED"><doc>Disabled (Use RB3D_BLENDCNTL)</doc></value> + <value value="1" name="ENABLED"><doc>Enabled (Use RB3D_ABLENDCNTL)</doc></value> +</enum> +<enum name="ENUM7"> + <value value="0" name="DISABLE_READS"><doc>Disable reads</doc></value> + <value value="1" name="ENABLE_READS"><doc>Enable reads</doc></value> +</enum> +<enum name="ENUM9"> + <value value="0" name="1_BUFFER"><doc>1 buffer. This is the only mode where the cb processes the end of packet command.</doc></value> + <value value="1" name="2_BUFFERS"><doc>2 buffers</doc></value> + <value value="2" name="3_BUFFERS"><doc>3 buffers</doc></value> + <value value="3" name="4_BUFFERS"><doc>4 buffers</doc></value> +</enum> +<enum name="ENUM10"> + <value value="0" name="DISABLE_COLOR_COMPARE"><doc>Disable color compare.</doc></value> + <value value="1" name="ENABLE_COLOR_COMPARE"><doc>Enable color compare.</doc></value> +</enum> +<enum name="ENUM11"> + <value value="0" name="DISABLE_AA_COMPRESSION"><doc>Disable AA compression</doc></value> + <value value="1" name="ENABLE_AA_COMPRESSION"><doc>Enable AA compression</doc></value> +</enum> +<enum name="ENUM12"> + <value value="0" name="3D_DESTINATION_IS_NOT_MACROTILED"><doc>3D destination is not macrotiled</doc></value> + <value value="1" name="3D_DESTINATION_IS_MACROTILED"><doc>3D destination is macrotiled</doc></value> +</enum> +<enum name="ENUM13"> + <value value="0" name="3D_DESTINATION_IS_NO_MICROTILED"><doc>3D destination is no microtiled</doc></value> + <value value="1" name="3D_DESTINATION_IS_MICROTILED"><doc>3D destination is microtiled</doc></value> + <value value="2" name="3D_DESTINATION_IS_SQUARE_MICROTILED"><doc>3D destination is square microtiled. Only available in 16-bit</doc></value> +</enum> +<enum name="ENUM14"> + <value value="0" name="NO_SWAP"><doc>No swap</doc></value> + <value value="1" name="WORD_SWAP"><doc>Word swap (2 bytes in 16-bit)</doc></value> + <value value="2" name="DWORD_SWAP"><doc>Dword swap (4 bytes in a 32-bit)</doc></value> + <value value="3" name="HALF"><doc>Half-Dword swap (2 16-bit in a 32-bit)</doc></value> +</enum> +<enum name="ENUM16"> + <value value="0" name="DISABLE"><doc>disable</doc></value> + <value value="1" name="ENABLE"><doc>enable</doc></value> +</enum> +<enum name="ENUM17"> + <value value="0" name="TRUNCATE"><doc>Truncate</doc></value> + <value value="1" name="ROUND"><doc>Round</doc></value> + <value value="2" name="LUT_DITHER"><doc>LUT dither</doc></value> +</enum> +<enum name="ENUM22"> + <value value="0" name="AF_NEVER"><doc>AF_NEVER</doc></value> + <value value="1" name="AF_LESS"><doc>AF_LESS</doc></value> + <value value="2" name="AF_EQUAL"><doc>AF_EQUAL</doc></value> + <value value="3" name="AF_LE"><doc>AF_LE</doc></value> + <value value="4" name="AF_GREATER"><doc>AF_GREATER</doc></value> + <value value="5" name="AF_NOTEQUAL"><doc>AF_NOTEQUAL</doc></value> + <value value="6" name="AF_GE"><doc>AF_GE</doc></value> + <value value="7" name="AF_ALWAYS"><doc>AF_ALWAYS</doc></value> +</enum> +<enum name="ENUM23"> + <value value="0" name="DISABLE_ALPHA_FUNCTION"><doc>Disable alpha function.</doc></value> + <value value="1" name="ENABLE_ALPHA_FUNCTION"><doc>Enable alpha function.</doc></value> +</enum> +<enum name="ENUM24"> + <value value="0" name="DISABLE_ALPHA_TO_MASK_FUNCTION"><doc>Disable alpha to mask function.</doc></value> + <value value="1" name="ENABLE_ALPHA_TO_MASK_FUNCTION"><doc>Enable alpha to mask function.</doc></value> +</enum> +<enum name="ENUM25"> + <value value="0" name="2"><doc>2/4 sub-pixel samples.</doc></value> + <value value="1" name="3"><doc>3/6 sub-pixel samples.</doc></value> +</enum> +<enum name="ENUM26"> + <value value="0" name="DISABLE_DITHERING"><doc>Disable Dithering</doc></value> + <value value="1" name="ENABLE_DITHERING"><doc>Enable Dithering.</doc></value> +</enum> +<enum name="ENUM30"> + <value value="0" name="SOLID_FILL_COLOR"><doc>Solid fill color</doc></value> + <value value="1" name="FLAT_SHADING"><doc>Flat shading</doc></value> + <value value="2" name="GOURAUD_SHADING"><doc>Gouraud shading</doc></value> +</enum> +<enum name="ENUM32"> + <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> + <value value="1" name="PREVENTS_TCL_INTERFACE_FROM_DEADLOCKING_ON_GA_SIDE"><doc>Prevents TCL interface from deadlocking on GA side.</doc></value> +</enum> +<enum name="ENUM33"> + <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> + <value value="1" name="ENABLES_HIGH"><doc>Enables high-performance register/primitive switching.</doc></value> +</enum> +<enum name="ENUM34"> + <value value="0" name="HORIZONTAL"><doc>Horizontal</doc></value> + <value value="1" name="VERTICAL"><doc>Vertical</doc></value> + <value value="2" name="SQUARE"><doc>Square (horizontal or vertical depending upon slope)</doc></value> + <value value="3" name="COMPUTED"><doc>Computed (perpendicular to slope)</doc></value> +</enum> +<enum name="ENUM37"> + <value value="0" name="DRAW_POINTS"><doc>Draw points.</doc></value> + <value value="1" name="DRAW_LINES"><doc>Draw lines.</doc></value> + <value value="2" name="DRAW_TRIANGLES"><doc>Draw triangles.</doc></value> + <value value="3" name="7"><doc>7.</doc></value> +</enum> +<enum name="ENUM38"> + <value value="0" name="ROUND_TO_TRUNC"><doc>Round to trunc</doc></value> + <value value="1" name="ROUND_TO_NEAREST"><doc>Round to nearest</doc></value> +</enum> +<enum name="ENUM43"> + <value value="0" name="DISABLE_POINT_TEXTURE_STUFFING"><doc>Disable point texture stuffing.</doc></value> + <value value="1" name="ENABLE_POINT_TEXTURE_STUFFING"><doc>Enable point texture stuffing.</doc></value> +</enum> +<enum name="ENUM44"> + <value value="0" name="DISABLE_LINE_TEXTURE_STUFFING"><doc>Disable line texture stuffing.</doc></value> + <value value="1" name="ENABLE_LINE_TEXTURE_STUFFING"><doc>Enable line texture stuffing.</doc></value> +</enum> +<enum name="ENUM45"> + <value value="0" name="DISABLE_TRIANGLE_TEXTURE_STUFFING"><doc>Disable triangle texture stuffing.</doc></value> + <value value="1" name="ENABLE_TRIANGLE_TEXTURE_STUFFING"><doc>Enable triangle texture stuffing.</doc></value> +</enum> +<enum name="ENUM46"> + <value value="0" name="DISABLE_STENCIL_AUTO_INC"><doc>Disable stencil auto inc/dec (def).</doc></value> + <value value="1" name="ENABLE_STENCIL_AUTO_INC"><doc>Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit.</doc></value> + <value value="2" name="FORCE_0_INTO_DZY_LOW_BIT"><doc>Force 0 into dzy low bit.</doc></value> +</enum> +<enum name="ENUM55"> + <value value="0" name="32_WORDS"><doc>32 words</doc></value> + <value value="1" name="64_WORDS"><doc>64 words</doc></value> + <value value="2" name="128_WORDS"><doc>128 words</doc></value> + <value value="3" name="256_WORDS"><doc>256 words</doc></value> +</enum> +<enum name="ENUM56"> + <value value="0" name="16_WORDS"><doc>16 words</doc></value> + <value value="1" name="32_WORDS"><doc>32 words</doc></value> + <value value="2" name="64_WORDS"><doc>64 words</doc></value> + <value value="3" name="128_WORDS"><doc>128 words</doc></value> +</enum> +<enum name="ENUM57"> + <value value="0" name="64_WORDS"><doc>64 words</doc></value> + <value value="1" name="128_WORDS"><doc>128 words</doc></value> + <value value="2" name="256_WORDS"><doc>256 words</doc></value> + <value value="3" name="512_WORDS"><doc>512 words</doc></value> +</enum> +<enum name="ENUM58"> + <value value="0" name="0_WORDS"><doc>0 words</doc></value> + <value value="1" name="4_WORDS"><doc>4 words</doc></value> + <value value="2" name="8_WORDS"><doc>8 words</doc></value> + <value value="3" name="12_WORDS"><doc>12 words</doc></value> +</enum> +<enum name="ENUM59"> + <value value="0" name="SELECT_C0A"><doc>Select C0A</doc></value> + <value value="1" name="SELECT_C1A"><doc>Select C1A</doc></value> + <value value="2" name="SELECT_C2A"><doc>Select C2A</doc></value> + <value value="3" name="SELECT_C3A"><doc>Select C3A</doc></value> + <value value="4" name="SELECT_1"><doc>Select 1/(1/W)</doc></value> + <value value="5" name="SELECT_Z"><doc>Select Z</doc></value> +</enum> +<enum name="ENUM60"> + <value value="0" name="SELECT_Z"><doc>Select Z</doc></value> + <value value="1" name="SELECT_1"><doc>Select 1/(1/W)</doc></value> +</enum> +<enum name="ENUM61"> + <value value="0" name="SELECT"><doc>Select (1/W)</doc></value> + <value value="1" name="SELECT_1"><doc>Select 1.0</doc></value> +</enum> +<enum name="ENUM62"> + <value value="0" name="TILING_DISABLED"><doc>Tiling disabled.</doc></value> + <value value="1" name="TILING_ENABLED"><doc>Tiling enabled (def).</doc></value> +</enum> +<enum name="ENUM65"> + <value value="0" name="1X1_TILE"><doc>1x1 tile (one 1x1).</doc></value> + <value value="1" name="2_TILES"><doc>2 tiles (two 1x1 : ST-A,B).</doc></value> + <value value="2" name="4_TILES"><doc>4 tiles (one 2x2).</doc></value> + <value value="3" name="8_TILES"><doc>8 tiles (two 2x2 : ST-A,B).</doc></value> + <value value="4" name="16_TILES"><doc>16 tiles (one 4x4).</doc></value> + <value value="5" name="32_TILES"><doc>32 tiles (two 4x4 : ST-A,B).</doc></value> + <value value="6" name="64_TILES"><doc>64 tiles (one 8x8).</doc></value> + <value value="7" name="128_TILES"><doc>128 tiles (two 8x8 : ST-A,B).</doc></value> +</enum> +<enum name="ENUM66"> + <value value="0" name="ST"><doc>ST-A tile.</doc></value> + <value value="1" name="ST"><doc>ST-B tile.</doc></value> +</enum> +<enum name="ENUM67"> + <value value="0" name="SELECT_1"><doc>Select 1/12 subpixel precision.</doc></value> + <value value="1" name="SELECT_1"><doc>Select 1/16 subpixel precision.</doc></value> +</enum> +<enum name="ENUM68"> + <value value="0" name="NO_WRITE"><doc>No write - texture coordinate not valid</doc></value> + <value value="1" name="WRITE"><doc>write - texture valid</doc></value> +</enum> +<enum name="ENUM70"> + <value value="0" name="SAMPLE_TEXTURE_COORDINATES_AT_REAL_PIXEL_CENTERS"><doc>Sample texture coordinates at real pixel centers</doc></value> + <value value="1" name="SAMPLE_TEXTURE_COORDINATES_AT_ADJUSTED_PIXEL_CENTERS"><doc>Sample texture coordinates at adjusted pixel centers</doc></value> +</enum> +<enum name="ENUM72"> + <value value="0" name="FOUR_COMPONENTS"><doc>Four components (R,G,B,A)</doc></value> + <value value="1" name="THREE_COMPONENTS"><doc>Three components (R,G,B,0)</doc></value> + <value value="2" name="THREE_COMPONENTS"><doc>Three components (R,G,B,1)</doc></value> + <value value="4" name="ONE_COMPONENT"><doc>One component (0,0,0,A)</doc></value> + <value value="5" name="ZERO_COMPONENTS"><doc>Zero components (0,0,0,0)</doc></value> + <value value="6" name="ZERO_COMPONENTS"><doc>Zero components (0,0,0,1)</doc></value> + <value value="8" name="ONE_COMPONENT"><doc>One component (1,1,1,A)</doc></value> + <value value="9" name="ZERO_COMPONENTS"><doc>Zero components (1,1,1,0)</doc></value> + <value value="10" name="ZERO_COMPONENTS"><doc>Zero components (1,1,1,1)</doc></value> +</enum> +<enum name="ENUM73"> + <value value="0" name="C"><doc>C</doc></value> + <value value="0" name="1ST_TEXTURE_COMPONENT"><doc>1st texture component</doc></value> + <value value="1" name="C"><doc>C</doc></value> + <value value="1" name="2ND_TEXTURE_COMPONENT"><doc>2nd texture component</doc></value> + <value value="2" name="C"><doc>C</doc></value> + <value value="2" name="3RD_TEXTURE_COMPONENT"><doc>3rd texture component</doc></value> + <value value="3" name="C"><doc>C</doc></value> + <value value="3" name="4TH_TEXTURE_COMPONENT"><doc>4th texture component</doc></value> + <value value="4" name="K"><doc>K</doc></value> + <value value="0" name="THE_VALUE_0"><doc>The value 0.0</doc></value> + <value value="5" name="K"><doc>K</doc></value> + <value value="1" name="THE_VALUE_1"><doc>The value 1.0</doc></value> +</enum> +<enum name="ENUM74"> + <value value="0" name="L"><doc>L-in,R-in,HT-in,HB-in</doc></value> + <value value="1" name="L"><doc>L-in,R-in,HT-in,HB-out</doc></value> + <value value="2" name="L"><doc>L-in,R-in,HT-out,HB-in</doc></value> + <value value="3" name="L"><doc>L-in,R-in,HT-out,HB-out</doc></value> + <value value="4" name="L"><doc>L-in,R-out,HT-in,HB-in</doc></value> + <value value="5" name="L"><doc>L-in,R-out,HT-in,HB-out</doc></value> + <value value="6" name="L"><doc>L-in,R-out,HT-out,HB-in</doc></value> + <value value="7" name="L"><doc>L-in,R-out,HT-out,HB-out</doc></value> + <value value="8" name="L"><doc>L-out,R-in,HT-in,HB-in</doc></value> + <value value="9" name="L"><doc>L-out,R-in,HT-in,HB-out</doc></value> + <value value="10" name="L"><doc>L-out,R-in,HT-out,HB-in</doc></value> + <value value="11" name="L"><doc>L-out,R-in,HT-out,HB-out</doc></value> + <value value="12" name="L"><doc>L-out,R-out,HT-in,HB-in</doc></value> + <value value="13" name="L"><doc>L-out,R-out,HT-in,HB-out</doc></value> + <value value="14" name="L"><doc>L-out,R-out,HT-out,HB-in</doc></value> + <value value="15" name="L"><doc>L-out,R-out,HT-out,HB-out</doc></value> + <value value="16" name="T"><doc>T-in,B-in,VL-in,VR-in</doc></value> + <value value="17" name="T"><doc>T-in,B-in,VL-in,VR-out</doc></value> + <value value="18" name="T"><doc>T-in,B-in,VL,VR-in</doc></value> + <value value="19" name="T"><doc>T-in,B-in,VL-out,VR-out</doc></value> + <value value="20" name="T"><doc>T-out,B-in,VL-in,VR-in</doc></value> + <value value="21" name="T"><doc>T-out,B-in,VL-in,VR-out</doc></value> + <value value="22" name="T"><doc>T-out,B-in,VL-out,VR-in</doc></value> + <value value="23" name="T"><doc>T-out,B-in,VL-out,VR-out</doc></value> + <value value="24" name="T"><doc>T-in,B-out,VL-in,VR-in</doc></value> + <value value="25" name="T"><doc>T-in,B-out,VL-in,VR-out</doc></value> + <value value="26" name="T"><doc>T-in,B-out,VL-out,VR-in</doc></value> + <value value="27" name="T"><doc>T-in,B-out,VL-out,VR-out</doc></value> + <value value="28" name="T"><doc>T-out,B-out,VL-in,VR-in</doc></value> + <value value="29" name="T"><doc>T-out,B-out,VL-in,VR-out</doc></value> + <value value="30" name="T"><doc>T-out,B-out,VL-out,VR-in</doc></value> + <value value="31" name="T"><doc>T-out,B-out,VL-out,VR-out</doc></value> +</enum> +<enum name="ENUM75"> + <value value="0" name="L"><doc>L-in,R-in,HT-in,HB-in</doc></value> + <value value="1" name="L"><doc>L-in,R-in,HT-in,HB-out</doc></value> + <value value="2" name="L"><doc>L-in,R-in,HT-out,HB-in</doc></value> + <value value="3" name="L"><doc>L-in,R-in,HT-out,HB-out</doc></value> + <value value="4" name="L"><doc>L-in,R-out,HT-in,HB-in</doc></value> + <value value="5" name="L"><doc>L-in,R-out,HT-in,HB-out</doc></value> + <value value="6" name="L"><doc>L-in,R-out,HT-out,HB-in</doc></value> + <value value="7" name="L"><doc>L-in,R-out,HT-out,HB-out</doc></value> + <value value="8" name="L"><doc>L-out,R-in,HT-in,HB-in</doc></value> + <value value="9" name="L"><doc>L-out,R-in,HT-in,HB-out</doc></value> + <value value="10" name="L"><doc>L-out,R-in,HT-out,HB-in</doc></value> + <value value="11" name="L"><doc>L-out,R-in,HT-out,HB-out</doc></value> + <value value="12" name="L"><doc>L-out,R-out,HT-in,HB-in</doc></value> + <value value="13" name="L"><doc>L-out,R-out,HT-in,HB-out</doc></value> + <value value="14" name="L"><doc>L-out,R-out,HT-out,HB-in</doc></value> + <value value="15" name="L"><doc>L-out,R-out,HT-out,HB-out</doc></value> + <value value="16" name="T"><doc>T-in,B-in,VL-in,VR-in</doc></value> + <value value="17" name="T"><doc>T-in,B-in,VL-in,VR-out</doc></value> + <value value="18" name="T"><doc>T-in,B-in,VL,VR-in</doc></value> + <value value="19" name="T"><doc>T-in,B-in,VL-out,VR-out</doc></value> + <value value="20" name="T"><doc>T-in,B-out,VL-in,VR-in</doc></value> + <value value="21" name="T"><doc>T-in,B-out,VL-in,VR-out</doc></value> + <value value="22" name="T"><doc>T-in,B-out,VL-out,VR-in</doc></value> + <value value="23" name="T"><doc>T-in,B-out,VL-out,VR-out</doc></value> + <value value="24" name="T"><doc>T-out,B-in,VL-in,VR-in</doc></value> + <value value="25" name="T"><doc>T-out,B-in,VL-in,VR-out</doc></value> + <value value="26" name="T"><doc>T-out,B-in,VL-out,VR-in</doc></value> + <value value="27" name="T"><doc>T-out,B-in,VL-out,VR-out</doc></value> + <value value="28" name="T"><doc>T-out,B-out,VL-in,VR-in</doc></value> + <value value="29" name="T"><doc>T-out,B-out,VL-in,VR-out</doc></value> + <value value="30" name="T"><doc>T-out,B-out,VL-out,VR-in</doc></value> + <value value="31" name="T"><doc>T-out,B-out,VL-out,VR-out</doc></value> +</enum> +<enum name="ENUM136"> + <value value="0" name="WRAP"><doc>Wrap (repeat)</doc></value> + <value value="1" name="MIRROR"><doc>Mirror</doc></value> + <value value="2" name="CLAMP_TO_LAST_TEXEL"><doc>Clamp to last texel (0.0 to 1.0)</doc></value> + <value value="3" name="MIRRORONCE_TO_LAST_TEXEL"><doc>MirrorOnce to last texel (-1.0 to 1.0)</doc></value> + <value value="4" name="CLAMP_HALF_WAY_TO_BORDER_COLOR"><doc>Clamp half way to border color (0.0 to 1.0)</doc></value> + <value value="5" name="MIRRORONCE_HALF_WAY_TO_BORDER_COLOR"><doc>MirrorOnce half way to border color (-1.0 to 1.0)</doc></value> + <value value="6" name="CLAMP_TO_BORDER_COLOR"><doc>Clamp to border color (0.0 to 1.0)</doc></value> + <value value="7" name="MIRRORONCE_TO_BORDER_COLOR"><doc>MirrorOnce to border color (-1.0 to 1.0)</doc></value> +</enum> +<enum name="ENUM137"> + <value value="1" name="POINT"><doc>Point</doc></value> + <value value="2" name="LINEAR"><doc>Linear</doc></value> +</enum> +<enum name="ENUM138"> + <value value="0" name="NONE"><doc>None</doc></value> + <value value="1" name="POINT"><doc>Point</doc></value> + <value value="2" name="LINEAR"><doc>Linear</doc></value> +</enum> +<enum name="ENUM139"> + <value value="0" name="NONE"><doc>None (no filter specifed, select from MIN/MAG filters)</doc></value> + <value value="1" name="POINT"><doc>Point</doc></value> + <value value="2" name="LINEAR"><doc>Linear</doc></value> +</enum> +<enum name="ENUM140"> + <value value="0" name="DISABLE"><doc>Disable</doc></value> + <value value="1" name="CHROMAKEY"><doc>ChromaKey (kill pixel if any sample matches chroma key)</doc></value> + <value value="2" name="CHROMAKEYBLEND"><doc>ChromaKeyBlend (set sample to 0 if it matches chroma key)</doc></value> +</enum> +<enum name="ENUM141"> + <value value="0" name="NORMAL_ROUNDING_ON_ALL_COMPONENTS"><doc>Normal rounding on all components (+0.5)</doc></value> + <value value="1" name="MPEG4_ROUNDING_ON_ALL_COMPONENTS"><doc>MPEG4 rounding on all components (+0.25)</doc></value> +</enum> +<enum name="ENUM142"> + <value value="0" name="DONT_TRUNCATE_COORDINATE_FRACTIONS"><doc>Dont truncate coordinate fractions.</doc></value> + <value value="1" name="TRUNCATE_COORDINATE_FRACTIONS_TO_0"><doc>Truncate coordinate fractions to 0.0 and 0.5 for MPEG</doc></value> +</enum> +<enum name="ENUM143"> + <value value="0" name="NON"><doc>Non-Projected</doc></value> + <value value="1" name="PROJECTED"><doc>Projected</doc></value> +</enum> +<enum name="ENUM144"> + <value value="0" name="USE_TXWIDTH_FOR_IMAGE_ADDRESSING"><doc>Use TXWIDTH for image addressing</doc></value> + <value value="1" name="USE_TXPITCH_FOR_IMAGE_ADDRESSING"><doc>Use TXPITCH for image addressing</doc></value> +</enum> +<enum name="ENUM154"> + <value value="0" name="DISABLE_GAMMA_REMOVAL"><doc>Disable gamma removal</doc></value> + <value value="1" name="ENABLE_GAMMA_REMOVAL"><doc>Enable gamma removal</doc></value> +</enum> +<enum name="ENUM155"> + <value value="0" name="DISABLE_YUV_TO_RGB_CONVERSION"><doc>Disable YUV to RGB conversion</doc></value> + <value value="1" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (with clamp)</doc></value> + <value value="2" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (without clamp)</doc></value> +</enum> +<enum name="ENUM156"> + <value value="0" name="DISABLE_SWAP_YUV_MODE"><doc>Disable swap YUV mode</doc></value> + <value value="1" name="ENABLE_SWAP_YUV_MODE"><doc>Enable swap YUV mode (hw inverts upper bit of U and V)</doc></value> +</enum> +<enum name="ENUM157"> + <value value="0" name="2D"><doc>2D</doc></value> + <value value="1" name="3D"><doc>3D</doc></value> + <value value="2" name="CUBE"><doc>Cube</doc></value> +</enum> +<enum name="ENUM158"> + <value value="0" name="WHOLE"><doc>WHOLE</doc></value> + <value value="2" name="HALF_REGION_0"><doc>HALF_REGION_0</doc></value> + <value value="3" name="HALF_REGION_1"><doc>HALF_REGION_1</doc></value> + <value value="4" name="FOURTH_REGION_0"><doc>FOURTH_REGION_0</doc></value> + <value value="5" name="FOURTH_REGION_1"><doc>FOURTH_REGION_1</doc></value> + <value value="6" name="FOURTH_REGION_2"><doc>FOURTH_REGION_2</doc></value> + <value value="7" name="FOURTH_REGION_3"><doc>FOURTH_REGION_3</doc></value> + <value value="8" name="EIGHTH_REGION_0"><doc>EIGHTH_REGION_0</doc></value> + <value value="9" name="EIGHTH_REGION_1"><doc>EIGHTH_REGION_1</doc></value> + <value value="10" name="EIGHTH_REGION_2"><doc>EIGHTH_REGION_2</doc></value> + <value value="11" name="EIGHTH_REGION_3"><doc>EIGHTH_REGION_3</doc></value> + <value value="12" name="EIGHTH_REGION_4"><doc>EIGHTH_REGION_4</doc></value> + <value value="13" name="EIGHTH_REGION_5"><doc>EIGHTH_REGION_5</doc></value> + <value value="14" name="EIGHTH_REGION_6"><doc>EIGHTH_REGION_6</doc></value> + <value value="15" name="EIGHTH_REGION_7"><doc>EIGHTH_REGION_7</doc></value> + <value value="16" name="SIXTEENTH_REGION_0"><doc>SIXTEENTH_REGION_0</doc></value> + <value value="17" name="SIXTEENTH_REGION_1"><doc>SIXTEENTH_REGION_1</doc></value> + <value value="18" name="SIXTEENTH_REGION_2"><doc>SIXTEENTH_REGION_2</doc></value> + <value value="19" name="SIXTEENTH_REGION_3"><doc>SIXTEENTH_REGION_3</doc></value> + <value value="20" name="SIXTEENTH_REGION_4"><doc>SIXTEENTH_REGION_4</doc></value> + <value value="21" name="SIXTEENTH_REGION_5"><doc>SIXTEENTH_REGION_5</doc></value> + <value value="22" name="SIXTEENTH_REGION_6"><doc>SIXTEENTH_REGION_6</doc></value> + <value value="23" name="SIXTEENTH_REGION_7"><doc>SIXTEENTH_REGION_7</doc></value> + <value value="24" name="SIXTEENTH_REGION_8"><doc>SIXTEENTH_REGION_8</doc></value> + <value value="25" name="SIXTEENTH_REGION_9"><doc>SIXTEENTH_REGION_9</doc></value> + <value value="26" name="SIXTEENTH_REGION_A"><doc>SIXTEENTH_REGION_A</doc></value> + <value value="27" name="SIXTEENTH_REGION_B"><doc>SIXTEENTH_REGION_B</doc></value> + <value value="28" name="SIXTEENTH_REGION_C"><doc>SIXTEENTH_REGION_C</doc></value> + <value value="29" name="SIXTEENTH_REGION_D"><doc>SIXTEENTH_REGION_D</doc></value> + <value value="30" name="SIXTEENTH_REGION_E"><doc>SIXTEENTH_REGION_E</doc></value> + <value value="31" name="SIXTEENTH_REGION_F"><doc>SIXTEENTH_REGION_F</doc></value> +</enum> +<enum name="ENUM159"> + <value value="0" name="NO_SWAP"><doc>No swap</doc></value> + <value value="1" name="16_BIT_SWAP"><doc>16 bit swap</doc></value> + <value value="2" name="32_BIT_SWAP"><doc>32 bit swap</doc></value> + <value value="3" name="HALF"><doc>Half-DWORD swap</doc></value> +</enum> +<enum name="ENUM160"> + <value value="0" name="2KB_PAGE_IS_LINEAR"><doc>2KB page is linear</doc></value> + <value value="1" name="2KB_PAGE_IS_TILED"><doc>2KB page is tiled</doc></value> +</enum> +<enum name="ENUM161"> + <value value="0" name="32_BYTE_CACHE_LINE_IS_LINEAR"><doc>32 byte cache line is linear</doc></value> + <value value="1" name="32_BYTE_CACHE_LINE_IS_TILED"><doc>32 byte cache line is tiled</doc></value> + <value value="2" name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE"><doc>32 byte cache line is tiled square (only applies to 16-bit texel)</doc></value> +</enum> +<enum name="ENUM164"> + <value value="0" name="A"><doc>A: Output to render target A</doc></value> + <value value="1" name="B"><doc>B: Output to render target B</doc></value> + <value value="2" name="C"><doc>C: Output to render target C</doc></value> + <value value="3" name="D"><doc>D: Output to render target D</doc></value> +</enum> +<enum name="ENUM166"> + <value value="0" name="SRC0"><doc>src0.r</doc></value> + <value value="1" name="SRC0"><doc>src0.g</doc></value> + <value value="2" name="SRC0"><doc>src0.b</doc></value> + <value value="3" name="SRC1"><doc>src1.r</doc></value> + <value value="4" name="SRC1"><doc>src1.g</doc></value> + <value value="5" name="SRC1"><doc>src1.b</doc></value> + <value value="6" name="SRC2"><doc>src2.r</doc></value> + <value value="7" name="SRC2"><doc>src2.g</doc></value> + <value value="8" name="SRC2"><doc>src2.b</doc></value> + <value value="9" name="SRC0"><doc>src0.a</doc></value> + <value value="10" name="SRC1"><doc>src1.a</doc></value> + <value value="11" name="SRC2"><doc>src2.a</doc></value> + <value value="12" name="SRCP"><doc>srcp.r</doc></value> + <value value="13" name="SRCP"><doc>srcp.g</doc></value> + <value value="14" name="SRCP"><doc>srcp.b</doc></value> + <value value="15" name="SRCP"><doc>srcp.a</doc></value> + <value value="16" name="0"><doc>0.0</doc></value> + <value value="17" name="1"><doc>1.0</doc></value> + <value value="18" name="0"><doc>0.5</doc></value> +</enum> +<enum name="ENUM167"> + <value value="0" name="NOP"><doc>NOP: Do not modify input</doc></value> + <value value="1" name="NEG"><doc>NEG: Negate input</doc></value> + <value value="2" name="ABS"><doc>ABS: Take absolute value of input</doc></value> + <value value="3" name="NAB"><doc>NAB: Take negative absolute value of input</doc></value> +</enum> +<enum name="ENUM168"> + <value value="0" name="1"><doc>1.0-2.0*A0</doc></value> + <value value="1" name="A1"><doc>A1-A0</doc></value> + <value value="2" name="A1"><doc>A1+A0</doc></value> + <value value="3" name="1"><doc>1.0-A0</doc></value> +</enum> +<enum name="ENUM170"> + <value value="0" name="RESULT"><doc>Result</doc></value> + <value value="1" name="RESULT"><doc>Result *2</doc></value> + <value value="2" name="RESULT"><doc>Result *4</doc></value> + <value value="3" name="RESULT"><doc>Result *8</doc></value> + <value value="4" name="RESULT"><doc>Result / 2</doc></value> + <value value="5" name="RESULT"><doc>Result / 4</doc></value> + <value value="6" name="RESULT"><doc>Result / 8</doc></value> +</enum> +<enum name="ENUM171"> + <value value="0" name="DO_NOT_CLAMP_OUTPUT"><doc>Do not clamp output.</doc></value> + <value value="1" name="CLAMP_OUTPUT_TO_THE_RANGE"><doc>Clamp output to the range [0,1].</doc></value> +</enum> +<enum name="ENUM172"> + <value value="0" name="NONE"><doc>NONE: No not write any output.</doc></value> + <value value="1" name="R"><doc>R: Write the red channel only.</doc></value> + <value value="2" name="G"><doc>G: Write the green channel only.</doc></value> + <value value="3" name="RG"><doc>RG: Write the red and green channels.</doc></value> + <value value="4" name="B"><doc>B: Write the blue channel only.</doc></value> + <value value="5" name="RB"><doc>RB: Write the red and blue channels.</doc></value> + <value value="6" name="GB"><doc>GB: Write the green and blue channels.</doc></value> + <value value="7" name="RGB"><doc>RGB: Write the red, green, and blue channels.</doc></value> +</enum> +<enum name="ENUM173"> + <value value="0" name="SRC0"><doc>src0.rgb</doc></value> + <value value="1" name="SRC0"><doc>src0.rrr</doc></value> + <value value="2" name="SRC0"><doc>src0.ggg</doc></value> + <value value="3" name="SRC0"><doc>src0.bbb</doc></value> + <value value="4" name="SRC1"><doc>src1.rgb</doc></value> + <value value="5" name="SRC1"><doc>src1.rrr</doc></value> + <value value="6" name="SRC1"><doc>src1.ggg</doc></value> + <value value="7" name="SRC1"><doc>src1.bbb</doc></value> + <value value="8" name="SRC2"><doc>src2.rgb</doc></value> + <value value="9" name="SRC2"><doc>src2.rrr</doc></value> + <value value="10" name="SRC2"><doc>src2.ggg</doc></value> + <value value="11" name="SRC2"><doc>src2.bbb</doc></value> + <value value="12" name="SRC0"><doc>src0.aaa</doc></value> + <value value="13" name="SRC1"><doc>src1.aaa</doc></value> + <value value="14" name="SRC2"><doc>src2.aaa</doc></value> + <value value="15" name="SRCP"><doc>srcp.rgb</doc></value> + <value value="16" name="SRCP"><doc>srcp.rrr</doc></value> + <value value="17" name="SRCP"><doc>srcp.ggg</doc></value> + <value value="18" name="SRCP"><doc>srcp.bbb</doc></value> + <value value="19" name="SRCP"><doc>srcp.aaa</doc></value> + <value value="20" name="0"><doc>0.0</doc></value> + <value value="21" name="1"><doc>1.0</doc></value> + <value value="22" name="0"><doc>0.5</doc></value> + <value value="23" name="SRC0"><doc>src0.gbr</doc></value> + <value value="24" name="SRC1"><doc>src1.gbr</doc></value> + <value value="25" name="SRC2"><doc>src2.gbr</doc></value> + <value value="26" name="SRC0"><doc>src0.brg</doc></value> + <value value="27" name="SRC1"><doc>src1.brg</doc></value> + <value value="28" name="SRC2"><doc>src2.brg</doc></value> + <value value="29" name="SRC0"><doc>src0.abg</doc></value> + <value value="30" name="SRC1"><doc>src1.abg</doc></value> + <value value="31" name="SRC2"><doc>src2.abg</doc></value> +</enum> +<enum name="ENUM174"> + <value value="0" name="1"><doc>1.0-2.0*RGB0</doc></value> + <value value="1" name="RGB1"><doc>RGB1-RGB0</doc></value> + <value value="2" name="RGB1"><doc>RGB1+RGB0</doc></value> + <value value="3" name="1"><doc>1.0-RGB0</doc></value> +</enum> +<enum name="ENUM178"> + <value value="0" name="DISABLED"><doc>Disabled</doc></value> + <value value="1" name="ENABLED"><doc>Enabled</doc></value> +</enum> +<enum name="ENUM179"> + <value value="0" name="C4_8"><doc>C4_8 (S/U)</doc></value> + <value value="1" name="C4_10"><doc>C4_10 (U)</doc></value> + <value value="2" name="C4_10_GAMMA"><doc>C4_10_GAMMA - (U)</doc></value> + <value value="3" name="C"><doc>C_</doc></value> + <value value="16" name=""><doc>(S/U)</doc></value> + <value value="4" name="C2"><doc>C2_</doc></value> + <value value="16" name=""><doc>(S/U)</doc></value> + <value value="5" name="C4"><doc>C4_</doc></value> + <value value="16" name=""><doc>(S/U)</doc></value> + <value value="6" name="C_16_MPEG"><doc>C_16_MPEG - (S)</doc></value> + <value value="7" name="C2_16_MPEG"><doc>C2_16_MPEG - (S)</doc></value> + <value value="8" name="C2"><doc>C2_</doc></value> + <value value="4" name=""><doc>(U)</doc></value> + <value value="9" name="C_3_3"><doc>C_3_3_</doc></value> + <value value="2" name=""><doc>(U)</doc></value> + <value value="10" name="C_6_5"><doc>C_6_5_</doc></value> + <value value="6" name=""><doc>(S/U)</doc></value> + <value value="11" name="C_11_11"><doc>C_11_11_</doc></value> + <value value="10" name=""><doc>(S/U)</doc></value> + <value value="12" name="C_10_11"><doc>C_10_11_</doc></value> + <value value="11" name=""><doc>(S/U)</doc></value> + <value value="13" name="C_2_10_10"><doc>C_2_10_10_</doc></value> + <value value="10" name=""><doc>(S/U)</doc></value> + <value value="15" name="UNUSED"><doc>UNUSED - Render target is not used</doc></value> + <value value="16" name="C_16_FP"><doc>C_16_FP - (S10E5)</doc></value> + <value value="17" name="C2_16_FP"><doc>C2_16_FP - (S10E5)</doc></value> + <value value="18" name="C4_16_FP"><doc>C4_16_FP - (S10E5)</doc></value> + <value value="19" name="C_32_FP"><doc>C_32_FP - (S23E8)</doc></value> + <value value="20" name="C2_32_FP"><doc>C2_32_FP - (S23E8)</doc></value> + <value value="21" name="C4_32_FP"><doc>C4_32_FP - (S23E8)</doc></value> +</enum> +<enum name="ENUM180"> + <value value="0" name="ALPHA"><doc>Alpha</doc></value> + <value value="1" name="RED"><doc>Red</doc></value> + <value value="2" name="GREEN"><doc>Green</doc></value> + <value value="3" name="BLUE"><doc>Blue</doc></value> +</enum> +<enum name="ENUM183"> + <value value="0" name="WSRC_US"><doc>WSRC_US - W comes from shader instruction</doc></value> + <value value="1" name="WSRC_RAS"><doc>WSRC_RAS - W comes from rasterizer</doc></value> +</enum> +<enum name="ENUM184"> + <value value="0" name=""><doc>-W < X < W, -W < Y < W, -W < Z < W (OpenGL Definition)</doc></value> + <value value="1" name=""><doc>-W < X < W, -W < Y < W, 0 < Z < W (DirectX Definition)</doc></value> +</enum> +<enum name="ENUM185"> + <value value="0" name=""><doc>(2^n - 1) (i.e. 8-bit -> 0.</doc></value> + <value value="0" name="255"><doc>255.0) 0 1 0.</doc></value> + <value value="0" name="1"><doc>1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.</doc></value> + <value value="0" name="127"><doc>127.0) 1 1 -1.</doc></value> + <value value="0" name="1"><doc>1.0 where n is the number of bits in the associated fixed point value For signed, normalize conversion, since the fixed point range is not evenly distributed around 0, there are 3 different methods supported by R300. See the VAP_PSC_SGN_NORM_CNTL description for details.</doc></value> +</enum> +<enum name="ENUM187"> + <value value="0" name="HIERARCHICAL_Z_DISABLED"><doc>Hierarchical Z Disabled</doc></value> + <value value="1" name="HIERARCHICAL_Z_ENABLED"><doc>Hierarchical Z Enabled</doc></value> +</enum> +<enum name="ENUM188"> + <value value="0" name="UPDATE_HIERARCHICAL_Z_WITH_MAX_VALUE"><doc>Update Hierarchical Z with Max value</doc></value> + <value value="1" name="UPDATE_HIERARCHICAL_Z_WITH_MIN_VALUE"><doc>Update Hierarchical Z with Min value</doc></value> +</enum> +<enum name="ENUM189"> + <value value="0" name="FAST_FILL_DISABLED"><doc>Fast Fill Disabled</doc></value> + <value value="1" name="FAST_FILL_ENABLED"><doc>Fast Fill Enabled (ZB_DEPTHCLEARVALUE )</doc></value> +</enum> +<enum name="ENUM190"> + <value value="0" name="Z_READ_COMPRESSION_DISABLED"><doc>Z Read Compression Disabled</doc></value> + <value value="1" name="Z_READ_COMPRESSION_ENABLED"><doc>Z Read Compression Enabled</doc></value> +</enum> +<enum name="ENUM191"> + <value value="0" name="Z_WRITE_COMPRESSION_DISABLED"><doc>Z Write Compression Disabled</doc></value> + <value value="1" name="Z_WRITE_COMPRESSION_ENABLED"><doc>Z Write Compression Enabled</doc></value> +</enum> +<enum name="ENUM192"> + <value value="0" name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW"><doc>Z unit cache controller does RMW</doc></value> + <value value="1" name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE"><doc>Z unit cache controller does cache-line granular Write only</doc></value> +</enum> +<enum name="ENUM196"> + <value value="0" name="16"><doc>16-bit Integer Z</doc></value> + <value value="1" name="16"><doc>16-bit compressed 13E3</doc></value> + <value value="2" name="24"><doc>24-bit Integer Z, 8 bit Stencil (LSBs)</doc></value> +</enum> +<enum name="ENUM202"> + <value value="0" name="NEVER"><doc>Never</doc></value> + <value value="1" name="LESS"><doc>Less</doc></value> + <value value="2" name="LESS_OR_EQUAL"><doc>Less or Equal</doc></value> + <value value="3" name="EQUAL"><doc>Equal</doc></value> + <value value="4" name="GREATER_OR_EQUAL"><doc>Greater or Equal</doc></value> + <value value="5" name="GREATER_THAN"><doc>Greater Than</doc></value> + <value value="6" name="NOT_EQUAL"><doc>Not Equal</doc></value> + <value value="7" name="ALWAYS"><doc>Always</doc></value> +</enum> +<enum name="ENUM203"> + <value value="0" name="NEVER"><doc>Never</doc></value> + <value value="1" name="LESS"><doc>Less</doc></value> + <value value="2" name="LESS_OR_EQUAL"><doc>Less or Equal</doc></value> + <value value="3" name="EQUAL"><doc>Equal</doc></value> + <value value="4" name="GREATER_OR_EQUAL"><doc>Greater or Equal</doc></value> + <value value="5" name="GREATER"><doc>Greater</doc></value> + <value value="6" name="NOT_EQUAL"><doc>Not Equal</doc></value> + <value value="7" name="ALWAYS"><doc>Always</doc></value> +</enum> +<enum name="ENUM204"> + <value value="0" name="KEEP"><doc>Keep: New value = Old value</doc></value> + <value value="1" name="ZERO"><doc>Zero: New value = 0</doc></value> + <value value="2" name="REPLACE"><doc>Replace: New value = STENCILREF</doc></value> + <value value="3" name="INCREMENT"><doc>Increment: New value++ (clamp)</doc></value> + <value value="4" name="DECREMENT"><doc>Decrement: New value-- (clamp)</doc></value> + <value value="5" name="INVERT_NEW_VALUE"><doc>Invert new value: New value = !Old value</doc></value> + <value value="6" name="INCREMENT"><doc>Increment: New value++ (wrap)</doc></value> + <value value="7" name="DECREMENT"><doc>Decrement: New value-- (wrap)</doc></value> +</enum> +<enum name="ENUM207"> + <value value="0" name=""><doc>>PIO,</doc></value> + <value value="1" name=""><doc>>BM</doc></value> +</enum> +<enum name="ENUM209"> + <value value="0" name="PHYSICAL"><doc>Physical (Default),</doc></value> + <value value="1" name="VIRTUAL"><doc>Virtual</doc></value> +</enum> +<enum name="ENUM216"> + <value value="0" name="FULL_SIZE"><doc>Full size</doc></value> + <value value="1" name="1"><doc>1/2 size</doc></value> + <value value="2" name="1"><doc>1/4 size</doc></value> + <value value="3" name="1"><doc>1/8 size</doc></value> +</enum> +<enum name="ENUM221"> + <value value="0" name="NO_OVERRIDE"><doc>No override</doc></value> + <value value="1" name="STUFF_TEXTURE_0"><doc>Stuff texture 0</doc></value> + <value value="2" name="STUFF_TEXTURE_1"><doc>Stuff texture 1</doc></value> + <value value="3" name="STUFF_TEXTURE_2"><doc>Stuff texture 2</doc></value> + <value value="4" name="STUFF_TEXTURE_3"><doc>Stuff texture 3</doc></value> + <value value="5" name="STUFF_TEXTURE_4"><doc>Stuff texture 4</doc></value> + <value value="6" name="STUFF_TEXTURE_5"><doc>Stuff texture 5</doc></value> + <value value="7" name="STUFF_TEXTURE_6"><doc>Stuff texture 6</doc></value> + <value value="8" name="STUFF_TEXTURE_7"><doc>Stuff texture 7</doc></value> + <value value="9" name="STUFF_TEXTURE_8"><doc>Stuff texture 8/C2</doc></value> + <value value="10" name="STUFF_TEXTURE_9"><doc>Stuff texture 9/C3</doc></value> +</enum> +<enum name="ENUM229"> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES"><doc>Replicate VAP source texture coordinates (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> +</enum> +<enum name="ENUM247"> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING"><doc>Disable cylindrical wrapping.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING"><doc>Enable cylindrical wrapping.</doc></value> +</enum> +<enum name="ENUM248"> + <value value="0" name="DISABLE"><doc>Disable, ARGB = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> +</enum> +<enum name="ENUM249"> + <value value="0" name="FILTER4"><doc>Filter4</doc></value> + <value value="1" name="POINT"><doc>Point</doc></value> + <value value="2" name="LINEAR"><doc>Linear</doc></value> +</enum> +<enum name="ENUM256"> + <value value="0" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component filter should interpret texel data as signed</doc></value> +</enum> +<enum name="ENUM257"> + <value value="0" name="SELECT_TEXTURE_COMPONENT0"><doc>Select Texture Component0.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1"><doc>Select Texture Component1.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2"><doc>Select Texture Component2.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3"><doc>Select Texture Component3.</doc></value> + <value value="4" name="SELECT_THE_VALUE_0"><doc>Select the value 0.</doc></value> + <value value="5" name="SELECT_THE_VALUE_1"><doc>Select the value 1.</doc></value> +</enum> +<enum name="ENUM261"> + <value value="0" name="NONE"><doc>NONE: Do not modify destination address.</doc></value> + <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL to address before write.</doc></value> +</enum> +<enum name="ENUM262"> + <value value="0" name="SRC0"><doc>src0</doc></value> + <value value="1" name="SRC1"><doc>src1</doc></value> + <value value="2" name="SRC2"><doc>src2</doc></value> + <value value="3" name="SRCP"><doc>srcp</doc></value> +</enum> +<enum name="ENUM263"> + <value value="0" name="RED"><doc>Red</doc></value> + <value value="1" name="GREEN"><doc>Green</doc></value> + <value value="2" name="BLUE"><doc>Blue</doc></value> + <value value="3" name="ALPHA"><doc>Alpha</doc></value> + <value value="4" name="ZERO"><doc>Zero</doc></value> + <value value="5" name="HALF"><doc>Half</doc></value> + <value value="6" name="ONE"><doc>One</doc></value> + <value value="7" name="UNUSED"><doc>Unused</doc></value> +</enum> +<enum name="ENUM264"> + <value value="0" name="RESULT"><doc>Result * 1</doc></value> + <value value="1" name="RESULT"><doc>Result * 2</doc></value> + <value value="2" name="RESULT"><doc>Result * 4</doc></value> + <value value="3" name="RESULT"><doc>Result * 8</doc></value> + <value value="4" name="RESULT"><doc>Result / 2</doc></value> + <value value="5" name="RESULT"><doc>Result / 4</doc></value> + <value value="6" name="RESULT"><doc>Result / 8</doc></value> + <value value="7" name="DISABLE_OUTPUT_MODIFIER_AND_CLAMPING"><doc>Disable output modifier and clamping (result is copied exactly; only valid for MIN/MAX/CMP/CND)</doc></value> +</enum> +<enum name="ENUM265"> + <value value="0" name="A"><doc>A: Output to render target A. Predicate == (ALU)</doc></value> + <value value="1" name="B"><doc>B: Output to render target B. Predicate < (ALU)</doc></value> + <value value="2" name="C"><doc>C: Output to render target C. Predicate >= (ALU)</doc></value> + <value value="3" name="D"><doc>D: Output to render target D. Predicate != (ALU)</doc></value> +</enum> +<enum name="ENUM267"> + <value value="0" name="TEMPORARY"><doc>TEMPORARY: Address temporary register or inline constant value.</doc></value> + <value value="1" name="CONSTANT"><doc>CONSTANT: Address constant register.</doc></value> +</enum> +<enum name="ENUM268"> + <value value="0" name="NONE"><doc>NONE: Do not modify source address.</doc></value> + <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL before lookup.</doc></value> +</enum> +<enum name="ENUM274"> + <value value="0" name="NORMAL_PREDICATION"><doc>Normal predication</doc></value> + <value value="1" name="INVERT_THE_VALUE_OF_THE_PREDICATE"><doc>Invert the value of the predicate</doc></value> +</enum> +<enum name="ENUM279"> + <value value="0" name="NONE"><doc>NONE: Do not write any output.</doc></value> + <value value="1" name="R"><doc>R: Write the red channel only.</doc></value> + <value value="2" name="G"><doc>G: Write the green channel only.</doc></value> + <value value="3" name="RG"><doc>RG: Write the red and green channels.</doc></value> + <value value="4" name="B"><doc>B: Write the blue channel only.</doc></value> + <value value="5" name="RB"><doc>RB: Write the red and blue channels.</doc></value> + <value value="6" name="GB"><doc>GB: Write the green and blue channels.</doc></value> + <value value="7" name="RGB"><doc>RGB: Write the red, green, and blue channels.</doc></value> +</enum> +<enum name="ENUM298"> + <value value="0" name="NONE"><doc>NONE: Do not modify source address</doc></value> + <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL before lookup.</doc></value> +</enum> +<enum name="ENUM299"> + <value value="0" name="USE_R_CHANNEL_AS_S_COORDINATE"><doc>Use R channel as S coordinate</doc></value> + <value value="1" name="USE_G_CHANNEL_AS_S_COORDINATE"><doc>Use G channel as S coordinate</doc></value> + <value value="2" name="USE_B_CHANNEL_AS_S_COORDINATE"><doc>Use B channel as S coordinate</doc></value> + <value value="3" name="USE_A_CHANNEL_AS_S_COORDINATE"><doc>Use A channel as S coordinate</doc></value> +</enum> +<enum name="ENUM300"> + <value value="0" name="USE_R_CHANNEL_AS_T_COORDINATE"><doc>Use R channel as T coordinate</doc></value> + <value value="1" name="USE_G_CHANNEL_AS_T_COORDINATE"><doc>Use G channel as T coordinate</doc></value> + <value value="2" name="USE_B_CHANNEL_AS_T_COORDINATE"><doc>Use B channel as T coordinate</doc></value> + <value value="3" name="USE_A_CHANNEL_AS_T_COORDINATE"><doc>Use A channel as T coordinate</doc></value> +</enum> +<enum name="ENUM301"> + <value value="0" name="USE_R_CHANNEL_AS_R_COORDINATE"><doc>Use R channel as R coordinate</doc></value> + <value value="1" name="USE_G_CHANNEL_AS_R_COORDINATE"><doc>Use G channel as R coordinate</doc></value> + <value value="2" name="USE_B_CHANNEL_AS_R_COORDINATE"><doc>Use B channel as R coordinate</doc></value> + <value value="3" name="USE_A_CHANNEL_AS_R_COORDINATE"><doc>Use A channel as R coordinate</doc></value> +</enum> +<enum name="ENUM302"> + <value value="0" name="USE_R_CHANNEL_AS_Q_COORDINATE"><doc>Use R channel as Q coordinate</doc></value> + <value value="1" name="USE_G_CHANNEL_AS_Q_COORDINATE"><doc>Use G channel as Q coordinate</doc></value> + <value value="2" name="USE_B_CHANNEL_AS_Q_COORDINATE"><doc>Use B channel as Q coordinate</doc></value> + <value value="3" name="USE_A_CHANNEL_AS_Q_COORDINATE"><doc>Use A channel as Q coordinate</doc></value> +</enum> +<enum name="ENUM313"> + <value value="12" name=""><doc>[8:0];2</doc></value> + <value value="56" name=""><doc>[7:0])</doc></value> +</enum> +<enum name="ENUM314"> + <value value="12" name=""><doc>[23:15];2</doc></value> + <value value="56" name=""><doc>[22:15])</doc></value> +</enum> + +<group name="rX00_regs" prepend="R300_"> + <reg32 name="RB3D_AARESOLVE_OFFSET" access="rw" offset="0x4E80"> + <doc>Resolve buffer destination address. The cache must be empty before changing this register if the cb is in resolve mode. Unpipelined</doc> + <bitfield name="AARESOLVE_OFFSET" high="31" low="5"> + <doc>256-bit aligned 3D resolve destination offset.</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_AARESOLVE_PITCH" access="rw" offset="0x4E84"> + <doc>Resolve Buffer Pitch and Tiling Control. The cache must be empty before changing this register if the cb is in resolve mode. Unpipelined</doc> + <bitfield name="AARESOLVE_PITCH" high="13" low="1"> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_ABLENDCNTL" access="rw" offset="0x4E08"> + <doc>Alpha Blend Control for Alpha Channel. Pipelined through the blender.</doc> + <bitfield name="COMB_FCN" high="14" low="12"> + <doc>Combine Function , Allows modification of how the SRCBLEND and DESTBLEND are combined.</doc> + <use-enum ref="ENUM2" /> + </bitfield> + <bitfield name="SRCBLEND" high="21" low="16"> + <doc>Source Blend Function , Alpha blending function (SRC).</doc> + <use-enum ref="ENUM3" /> + </bitfield> + <bitfield name="DESTBLEND" high="29" low="24"> + <doc>Destination Blend Function , Alpha blending function (DST).</doc> + <use-enum ref="ENUM4" /> + </bitfield> + </reg32> + <reg32 name="RB3D_CLRCMP_CLR" access="rw" offset="0x4E20"> + <doc>Color Compare Color. Stalls the 2d/3d datapath until it is idle.</doc> + </reg32> + <reg32 name="RB3D_CLRCMP_FLIPE" access="rw" offset="0x4E1C"> + <doc>Color Compare Flip. Stalls the 2d/3d datapath until it is idle.</doc> + </reg32> + <reg32 name="RB3D_CLRCMP_MSK" access="rw" offset="0x4E24"> + <doc>Color Compare Mask. Stalls the 2d/3d datapath until it is idle.</doc> + </reg32> + <stripe offset="0x4E28" stride="0x0004" length="4"> + <reg32 name="RB3D_COLOROFFSET" access="rw" offset="0x0000"> + <doc>Color Buffer Address Offset of multibuffer 0. Unpipelined.</doc> + <bitfield name="COLOROFFSET" high="31" low="5"> + <doc>256-bit aligned 3D destination offset address. The cache must be empty before this is changed.</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="RB3D_DITHER_CTL" access="rw" offset="0x4E50"> + <doc>Dithering control register. Pipelined through the blender.</doc> + <bitfield name="DITHER_MODE" high="1" low="0"> + <doc>Dither mode</doc> + <use-enum ref="ENUM17" /> + </bitfield> + <bitfield name="ALPHA_DITHER_MODE" high="3" low="2"> + <doc></doc> + <use-enum ref="ENUM17" /> + </bitfield> + </reg32> + <reg32 name="RB3D_DSTCACHE_CTLSTAT" access="rw" offset="0x4E4C"> + <doc>Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then a flush or free will not occur upon a write to this register, but a sync will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE are zero but DC_FINISH is one, then a sync will be sent immediately -- the cb will not wait for all the previous operations to complete before sending the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to zero.</doc> + <bitfield name="DC_FLUSH" high="1" low="0"> + <doc>Setting this bit flushes dirty data from the 3D Dst Cache. Unless the DC_FREE bits are also set, the tags in the cache remain valid. A purge is achieved by setting both DC_FLUSH and DC_FREE.</doc> + <value value="0" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="1" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="2" name="FLUSHES_DIRTY_3D_DATA"><doc>Flushes dirty 3D data</doc></value> + <value value="3" name="FLUSHES_DIRTY_3D_DATA"><doc>Flushes dirty 3D data</doc></value> + </bitfield> + <bitfield name="DC_FREE" high="3" low="2"> + <doc>Setting this bit invalidates the 3D Dst Cache tags. Unless the DC_FLUSH bit is also set, the cache lines are not written to memory. A purge is achieved by setting both DC_FLUSH and DC_FREE.</doc> + <value value="0" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="1" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="2" name="FREE_3D_TAGS"><doc>Free 3D tags</doc></value> + <value value="3" name="FREE_3D_TAGS"><doc>Free 3D tags</doc></value> + </bitfield> + <bitfield name="DC_FINISH" high="4" low="4"> + <doc></doc> + <value value="0" name="DO_NOT_SEND_A_FINISH_SIGNAL_TO_THE_CP"><doc>do not send a finish signal to the CP</doc></value> + <value value="1" name="SEND_A_FINISH_SIGNAL_TO_THE_CP_AFTER_THE_END_OF_OPERATION"><doc>send a finish signal to the CP after the end of operation</doc></value> + </bitfield> + </reg32> + <reg32 name="RB3D_ROPCNTL" access="rw" offset="0x4E18"> + <doc>3D ROP Control. Stalls the 2d/3d datapath until it is idle.</doc> + <bitfield name="ROP_ENABLE" high="2" low="2"> + <doc></doc> + <value value="0" name="DISABLE_ROP"><doc>Disable ROP. (Forces ROP2 to be 0xC).</doc></value> + <value value="1" name="ENABLED"><doc>Enabled</doc></value> + </bitfield> + <bitfield name="ROP" high="11" low="8"> + <doc>ROP2 code for 3D fragments. This value is replicated into 2 nibbles to form the equivalent ROP3 code to control the ROP3 logic. These are the GDI ROP2 codes.</doc> + </bitfield> + </reg32> + <reg32 name="FG_DEPTH_SRC" access="rw" offset="0x4BD8"> + <doc>Where does depth come from?</doc> + <bitfield name="DEPTH_SRC" high="0" low="0"> + <doc></doc> + <value value="0" name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE_EQUATION"><doc>Depth comes from scan converter as plane equation.</doc></value> + <value value="1" name="DEPTH_COMES_FROM_SHADER_AS_FOUR_DISCRETE_VALUES"><doc>Depth comes from shader as four discrete values.</doc></value> + </bitfield> + </reg32> + <reg32 name="FG_FOG_BLEND" access="rw" offset="0x4BC0"> + <doc>Fog Blending Enable</doc> + <bitfield name="ENABLE" high="0" low="0"> + <doc>Enable for fog blending</doc> + <value value="0" name="DISABLES_FOG"><doc>Disables fog (output matches input color).</doc></value> + <value value="1" name="ENABLES_FOG"><doc>Enables fog.</doc></value> + </bitfield> + <bitfield name="FN" high="2" low="1"> + <doc>Fog generation function</doc> + <value value="0" name="FOG_FUNCTION_IS_LINEAR"><doc>Fog function is linear</doc></value> + <value value="1" name="FOG_FUNCTION_IS_EXPONENTIAL"><doc>Fog function is exponential</doc></value> + <value value="2" name="FOG_FUNCTION_IS_EXPONENTIAL_SQUARED"><doc>Fog function is exponential squared</doc></value> + <value value="3" name="FOG_IS_DERIVED_FROM_CONSTANT_FOG_FACTOR"><doc>Fog is derived from constant fog factor</doc></value> + </bitfield> + </reg32> + <reg32 name="GA_COLOR_CONTROL" access="rw" offset="0x4278"> + <doc>Specifies per RGB or Alpha shading method.</doc> + <bitfield name="RGB0_SHADING" high="1" low="0"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="ALPHA0_SHADING" high="3" low="2"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="RGB1_SHADING" high="5" low="4"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="ALPHA1_SHADING" high="7" low="6"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="RGB2_SHADING" high="9" low="8"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="ALPHA2_SHADING" high="11" low="10"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="RGB3_SHADING" high="13" low="12"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="ALPHA3_SHADING" high="15" low="14"> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="PROVOKING_VERTEX" high="17" low="16"> + <doc>Specifies, for flat shaded polygons, which vertex holds the polygon color.</doc> + <value value="0" name="PROVOKING_IS_FIRST_VERTEX"><doc>Provoking is first vertex</doc></value> + <value value="1" name="PROVOKING_IS_SECOND_VERTEX"><doc>Provoking is second vertex</doc></value> + <value value="2" name="PROVOKING_IS_THIRD_VERTEX"><doc>Provoking is third vertex</doc></value> + <value value="3" name="PROVOKING_IS_ALWAYS_LAST_VERTEX"><doc>Provoking is always last vertex</doc></value> + </bitfield> + </reg32> + <reg32 name="GA_FOG_OFFSET" access="rw" offset="0x4298"> + <doc>Specifies the offset to apply to fog.</doc> + </reg32> + <reg32 name="GA_FOG_SCALE" access="rw" offset="0x4294"> + <doc>Specifies the scale to apply to fog.</doc> + </reg32> + <reg32 name="GA_LINE_S0" access="rw" offset="0x4264"> + <doc>S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA)</doc> + </reg32> + <reg32 name="GA_LINE_S1" access="rw" offset="0x4268"> + <doc>S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA)</doc> + </reg32> + <reg32 name="GA_LINE_STIPPLE_CONFIG" access="rw" offset="0x4238"> + <doc>Line Stipple configuration information.</doc> + <bitfield name="LINE_RESET" high="1" low="0"> + <doc>Specify type of reset to use for stipple accumulation.</doc> + <value value="0" name="NO_RESETING"><doc>No reseting</doc></value> + <value value="1" name="RESET_PER_LINE"><doc>Reset per line</doc></value> + <value value="2" name="RESET_PER_PACKET"><doc>Reset per packet</doc></value> + </bitfield> + <bitfield name="STIPPLE_SCALE" high="31" low="2"> + <doc>Specifies, in truncated (30b) floating point, scale to apply to generated texture coordinates.</doc> + </bitfield> + </reg32> + <reg32 name="GA_LINE_STIPPLE_VALUE" access="rw" offset="0x4260"> + <doc>Current value of stipple accumulator.</doc> + </reg32> + <reg32 name="GA_POINT_MINMAX" access="rw" offset="0x4230"> + <doc>Specifies maximum and minimum point & sprite sizes for per vertex size specification.</doc> + <bitfield name="MIN_SIZE" high="15" low="0"> + <doc>Minimum point & sprite radius (in subsamples) size to allow.</doc> + </bitfield> + <bitfield name="MAX_SIZE" high="31" low="16"> + <doc>Maximum point & sprite radius (in subsamples) size to allow.</doc> + </bitfield> + </reg32> + <reg32 name="GA_POINT_S0" access="rw" offset="0x4200"> + <doc>S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC)</doc> + </reg32> + <reg32 name="GA_POINT_S1" access="rw" offset="0x4208"> + <doc>S Texture Coordinate of Vertex 2 for Point texture stuffing (URC)</doc> + </reg32> + <reg32 name="GA_POINT_T0" access="rw" offset="0x4204"> + <doc>T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC)</doc> + </reg32> + <reg32 name="GA_POINT_T1" access="rw" offset="0x420C"> + <doc>T Texture Coordinate of Vertex 2 for Point texture stuffing (URC)</doc> + </reg32> + <reg32 name="GA_POLY_MODE" access="rw" offset="0x4288"> + <doc>Polygon Mode</doc> + <bitfield name="POLY_MODE" high="1" low="0"> + <doc>Polygon mode enable.</doc> + <value value="0" name="DISABLE_POLY_MODE"><doc>Disable poly mode (render triangles).</doc></value> + <value value="1" name="DUAL_MODE"><doc>Dual mode (send 2 sets of 3 polys with specified poly type).</doc></value> + </bitfield> + <bitfield name="FRONT_PTYPE" high="6" low="4"> + <doc>Specifies how to render front-facing polygons.</doc> + <use-enum ref="ENUM37" /> + </bitfield> + <bitfield name="BACK_PTYPE" high="9" low="7"> + <doc>Specifies how to render back-facing polygons.</doc> + <use-enum ref="ENUM37" /> + </bitfield> + </reg32> + <reg32 name="GA_TRIANGLE_STIPPLE" access="rw" offset="0x4214"> + <doc>Specifies amount to shift integer position of vertex (screen space) before converting to float for triangle stipple.</doc> + <bitfield name="X_SHIFT" high="3" low="0"> + <doc>Amount to shift x position before conversion to SPFP.</doc> + </bitfield> + <bitfield name="Y_SHIFT" high="19" low="16"> + <doc>Amount to shift y position before conversion to SPFP.</doc> + </bitfield> + </reg32> + <reg32 name="GB_AA_CONFIG" access="rw" offset="0x4020"> + <doc>Specifies the graphics pipeline configuration for antialiasing.</doc> + <bitfield name="AA_ENABLE" high="0" low="0"> + <doc>Enables antialiasing.</doc> + <value value="0" name="ANTIALIASING_DISABLED"><doc>Antialiasing disabled(def)</doc></value> + <value value="1" name="ANTIALIASING_ENABLED"><doc>Antialiasing enabled</doc></value> + </bitfield> + <bitfield name="NUM_AA_SUBSAMPLES" high="2" low="1"> + <doc>Specifies the number of subsamples to use while antialiasing.</doc> + <value value="0" name="2_SUBSAMPLES"><doc>2 subsamples</doc></value> + <value value="1" name="3_SUBSAMPLES"><doc>3 subsamples</doc></value> + <value value="2" name="4_SUBSAMPLES"><doc>4 subsamples</doc></value> + <value value="3" name="6_SUBSAMPLES"><doc>6 subsamples</doc></value> + </bitfield> + </reg32> + <reg32 name="SC_CLIP_0_A" access="rw" offset="0x43B0"> + <doc>OpenGL Clip rectangles</doc> + <bitfield name="XS0" high="12" low="0"> + <doc>Left hand edge of clip rectangle</doc> + </bitfield> + <bitfield name="YS0" high="25" low="13"> + <doc>Upper edge of clip rectangle</doc> + </bitfield> + </reg32> + <reg32 name="SC_CLIP_0_B" access="rw" offset="0x43B4"> + <doc>OpenGL Clip rectangles</doc> + <bitfield name="XS1" high="12" low="0"> + <doc>Right hand edge of clip rectangle</doc> + </bitfield> + <bitfield name="YS1" high="25" low="13"> + <doc>Lower edge of clip rectangle</doc> + </bitfield> + </reg32> + <reg32 name="SC_CLIP_1_A" access="rw" offset="0x43B8" /> + <reg32 name="SC_CLIP_1_B" access="rw" offset="0x43BC" /> + <reg32 name="SC_CLIP_2_A" access="rw" offset="0x43C0" /> + <reg32 name="SC_CLIP_2_B" access="rw" offset="0x43C4" /> + <reg32 name="SC_CLIP_3_A" access="rw" offset="0x43C8" /> + <reg32 name="SC_CLIP_3_B" access="rw" offset="0x43CC" /> + <reg32 name="SC_CLIP_RULE" access="rw" offset="0x43D0"> + <doc>OpenGL Clip boolean function</doc> + <bitfield name="CLIP_RULE" high="15" low="0"> + <doc>OpenGL Clip boolean function. The `inside` flags for each of the four clip rectangles form a 4-bit binary number. The corresponding bit in this 16-bit number specifies whether the pixel is visible.</doc> + </bitfield> + </reg32> + <reg32 name="SC_HYPERZ_EN" access="rw" offset="0x43A4"> + <doc>Hierarchical Z Enable</doc> + <bitfield name="HZ_EN" high="0" low="0"> + <doc>Enable for hierarchical Z.</doc> + <value value="0" name="DISABLES_HYPER"><doc>Disables Hyper-Z.</doc></value> + <value value="1" name="ENABLES_HYPER"><doc>Enables Hyper-Z.</doc></value> + </bitfield> + <bitfield name="HZ_MAX" high="1" low="1"> + <doc>Specifies whether to compute min or max z value</doc> + <value value="0" name="HZ_BLOCK_COMPUTES_MINIMUM_Z_VALUE"><doc>HZ block computes minimum z value</doc></value> + <value value="1" name="HZ_BLOCK_COMPUTES_MAXIMUM_Z_VALUE"><doc>HZ block computes maximum z value</doc></value> + </bitfield> + <bitfield name="HZ_ADJ" high="4" low="2"> + <doc>Specifies adjustment to get added or subtracted from computed z value</doc> + <value value="0" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/256 << ze</doc></value> + <value value="1" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/128 << ze</doc></value> + <value value="2" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/64 << ze</doc></value> + <value value="3" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/32 << ze</doc></value> + <value value="4" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/16 << ze</doc></value> + <value value="5" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/8 << ze</doc></value> + <value value="6" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/4 << ze</doc></value> + <value value="7" name="ADD_OR_SUBTRACT_1"><doc>Add or Subtract 1/2 << ze</doc></value> + </bitfield> + <bitfield name="HZ_Z0MIN" high="5" low="5"> + <doc>Specifies whether vertex 0 z contains minimum z value</doc> + <value value="0" name="VERTEX_0_DOES_NOT_CONTAIN_MINIMUM_Z_VALUE"><doc>Vertex 0 does not contain minimum z value</doc></value> + <value value="1" name="VERTEX_0_DOES_CONTAIN_MINIMUM_Z_VALUE"><doc>Vertex 0 does contain minimum z value</doc></value> + </bitfield> + <bitfield name="HZ_Z0MAX" high="6" low="6"> + <doc>Specifies whether vertex 0 z contains maximum z value</doc> + <value value="0" name="VERTEX_0_DOES_NOT_CONTAIN_MAXIMUM_Z_VALUE"><doc>Vertex 0 does not contain maximum z value</doc></value> + <value value="1" name="VERTEX_0_DOES_CONTAIN_MAXIMUM_Z_VALUE"><doc>Vertex 0 does contain maximum z value</doc></value> + </bitfield> + </reg32> + <reg32 name="SC_SCISSOR0" access="rw" offset="0x43E0"> + <doc>Scissor rectangle specification</doc> + <bitfield name="XS0" high="12" low="0"> + <doc>Left hand edge of scissor rectangle</doc> + </bitfield> + <bitfield name="YS0" high="25" low="13"> + <doc>Upper edge of scissor rectangle</doc> + </bitfield> + </reg32> + <reg32 name="SC_SCISSOR1" access="rw" offset="0x43E4"> + <doc>Scissor rectangle specification</doc> + <bitfield name="XS1" high="12" low="0"> + <doc>Right hand edge of scissor rectangle</doc> + </bitfield> + <bitfield name="YS1" high="25" low="13"> + <doc>Lower edge of scissor rectangle</doc> + </bitfield> + </reg32> + <reg32 name="SC_SCREENDOOR" access="rw" offset="0x43E8"> + <doc>Screen door sample mask</doc> + <bitfield name="SCREENDOOR" high="23" low="0"> + <doc>Screen door sample mask - 1 means sample may be covered, 0 means sample is not covered</doc> + </bitfield> + </reg32> + <reg32 name="SU_CULL_MODE" access="rw" offset="0x42B8"> + <doc>Culling Enables</doc> + <bitfield name="CULL_FRONT" high="0" low="0"> + <doc>Enable for front-face culling.</doc> + <value value="0" name="DO_NOT_CULL_FRONT"><doc>Do not cull front-facing triangles.</doc></value> + <value value="1" name="CULL_FRONT"><doc>Cull front-facing triangles.</doc></value> + </bitfield> + <bitfield name="CULL_BACK" high="1" low="1"> + <doc>Enable for back-face culling.</doc> + <value value="0" name="DO_NOT_CULL_BACK"><doc>Do not cull back-facing triangles.</doc></value> + <value value="1" name="CULL_BACK"><doc>Cull back-facing triangles.</doc></value> + </bitfield> + <bitfield name="FACE" high="2" low="2"> + <doc>X-Ored with cross product sign to determine positive facing</doc> + <value value="0" name="POSITIVE_CROSS_PRODUCT_IS_FRONT"><doc>Positive cross product is front (CCW).</doc></value> + <value value="1" name="NEGATIVE_CROSS_PRODUCT_IS_FRONT"><doc>Negative cross product is front (CW).</doc></value> + </bitfield> + </reg32> + <reg32 name="SU_DEPTH_OFFSET" access="rw" offset="0x42C4"> + <doc>SU Depth Offset value</doc> + </reg32> + <reg32 name="SU_DEPTH_SCALE" access="rw" offset="0x42C0"> + <doc>SU Depth Scale value</doc> + </reg32> + <reg32 name="SU_POLY_OFFSET_BACK_OFFSET" access="rw" offset="0x42B0"> + <doc>Back-Facing Polygon Offset Offset</doc> + </reg32> + <reg32 name="SU_POLY_OFFSET_BACK_SCALE" access="rw" offset="0x42AC"> + <doc>Back-Facing Polygon Offset Scale</doc> + </reg32> + <reg32 name="SU_POLY_OFFSET_ENABLE" access="rw" offset="0x42B4"> + <doc>Enables for polygon offset</doc> + <bitfield name="FRONT_ENABLE" high="0" low="0"> + <doc>Enables front facing polygon`s offset.</doc> + <value value="0" name="DISABLE_FRONT_OFFSET"><doc>Disable front offset.</doc></value> + <value value="1" name="ENABLE_FRONT_OFFSET"><doc>Enable front offset.</doc></value> + </bitfield> + <bitfield name="BACK_ENABLE" high="1" low="1"> + <doc>Enables back facing polygon`s offset.</doc> + <value value="0" name="DISABLE_BACK_OFFSET"><doc>Disable back offset.</doc></value> + <value value="1" name="ENABLE_BACK_OFFSET"><doc>Enable back offset.</doc></value> + </bitfield> + <bitfield name="PARA_ENABLE" high="2" low="2"> + <doc>Forces all parallelograms to have FRONT_FACING for poly offset -- Need to have FRONT_ENABLE also set to have Z offset for parallelograms.</doc> + <value value="0" name="DISABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS"><doc>Disable front offset for parallelograms.</doc></value> + <value value="1" name="ENABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS"><doc>Enable front offset for parallelograms.</doc></value> + </bitfield> + </reg32> + <reg32 name="SU_POLY_OFFSET_FRONT_OFFSET" access="rw" offset="0x42A8"> + <doc>Front-Facing Polygon Offset Offset</doc> + </reg32> + <reg32 name="SU_POLY_OFFSET_FRONT_SCALE" access="rw" offset="0x42A4"> + <doc>Front-Facing Polygon Offset Scale</doc> + </reg32> + <reg32 name="TX_INVALTAGS" access="rw" offset="0x4100"> + <doc>Invalidate texture cache tags</doc> + </reg32> + <reg32 name="VAP_GB_HORZ_CLIP_ADJ" access="rw" offset="0x2228"> + <doc>Horizontal Guard Band Clip Adjust Register</doc> + </reg32> + <reg32 name="VAP_GB_HORZ_DISC_ADJ" access="rw" offset="0x222C"> + <doc>Horizontal Guard Band Discard Adjust Register</doc> + </reg32> + <reg32 name="VAP_GB_VERT_CLIP_ADJ" access="rw" offset="0x2220"> + <doc>Vertical Guard Band Clip Adjust Register</doc> + </reg32> + <reg32 name="VAP_GB_VERT_DISC_ADJ" access="rw" offset="0x2224"> + <doc>Vertical Guard Band Discard Adjust Register</doc> + </reg32> + <reg32 name="VAP_OUT_VTX_FMT_0" access="rw" offset="0x2090"> + <doc>VAP Out/GA Vertex Format Register 0</doc> + <bitfield name="VTX_POS_PRESENT" high="0" low="0"> + <doc>Output the Position Vector</doc> + </bitfield> + <bitfield name="VTX_COLOR_0_PRESENT" high="1" low="1"> + <doc>Output Color 0 Vector</doc> + </bitfield> + <bitfield name="VTX_COLOR_1_PRESENT" high="2" low="2"> + <doc>Output Color 1 Vector</doc> + </bitfield> + <bitfield name="VTX_COLOR_2_PRESENT" high="3" low="3"> + <doc>Output Color 2 Vector</doc> + </bitfield> + <bitfield name="VTX_COLOR_3_PRESENT" high="4" low="4"> + <doc>Output Color 3 Vector</doc> + </bitfield> + <bitfield name="VTX_PT_SIZE_PRESENT" high="16" low="16"> + <doc>Output Point Size Vector</doc> + </bitfield> + </reg32> + <reg32 name="VAP_OUT_VTX_FMT_1" access="rw" offset="0x2094"> + <doc>VAP Out/GA Vertex Format Register 1</doc> + <bitfield name="TEX_0_COMP_CNT" high="2" low="0"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_1_COMP_CNT" high="5" low="3"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_2_COMP_CNT" high="8" low="6"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_3_COMP_CNT" high="11" low="9"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_4_COMP_CNT" high="14" low="12"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_5_COMP_CNT" high="17" low="15"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_6_COMP_CNT" high="20" low="18"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + <bitfield name="TEX_7_COMP_CNT" high="23" low="21"> + <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = 2 components 3 = 3 components 4 = 4 components</doc> + </bitfield> + </reg32> + <stripe offset="0x2000" stride="0x0004" length="16"> + <reg32 name="VAP_PORT_DATA" access="w" offset="0x0000"> + <doc>Setup Engine Data Port 0 through 15.</doc> + </reg32> + </stripe> + <reg32 name="VAP_PORT_DATA_IDX_128" access="w" offset="0x20B8"> + <doc>128-bit Data Port for Indexed Primitives.</doc> + </reg32> + <stripe offset="0x2040" stride="0x0004" length="16"> + <reg32 name="VAP_PORT_IDX" access="w" offset="0x0000"> + <doc>Setup Engine Index Port 0 through 15.</doc> + </reg32> + </stripe> + <stripe offset="0x21E0" stride="0x0004" length="8"> + <reg32 name="VAP_PROG_STREAM_CNTL_EXT" access="rw" offset="0x0000"> + <doc>Programmable Stream Control Extension Word 0</doc> + <bitfield name="SWIZZLE_SELECT_X_0" high="2" low="0"> + <doc>X-Component Swizzle Select 0 = SELECT_X 1 = SELECT_Y 2 = SELECT_Z 3 = SELECT_W 4 = SELECT_FP_ZERO (Floating Point 0.0) 5 = SELECT_FP_ONE (Floating Point 1.0) 6,7 RESERVED</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_Y_0" high="5" low="3"> + <doc>Y-Component Swizzle Select (See Above)</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_Z_0" high="8" low="6"> + <doc>Z-Component Swizzle Select (See Above)</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_W_0" high="11" low="9"> + <doc>W-Component Swizzle Select (See Above)</doc> + </bitfield> + <bitfield name="WRITE_ENA_0" high="15" low="12"> + <doc>4-bit write enable. Bit 0 maps to X Bit 1 maps to Y Bit 2 maps to Z Bit 3 maps to W</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_X_1" high="18" low="16"> + <doc>See SWIZZLE_SELECT_X_0</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_Y_1" high="21" low="19"> + <doc>See SWIZZLE_SELECT_Y_0</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_Z_1" high="24" low="22"> + <doc>See SWIZZLE_SELECT_Z_0</doc> + </bitfield> + <bitfield name="SWIZZLE_SELECT_W_1" high="27" low="25"> + <doc>See SWIZZLE_SELECT_W_0</doc> + </bitfield> + <bitfield name="WRITE_ENA_1" high="31" low="28"> + <doc>See WRITE_ENA_0</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_PSC_SGN_NORM_CNTL" access="rw" offset="0x21DC"> + <doc>Programmable Stream Control Signed Normalize Control</doc> + <bitfield name="SGN_NORM_METHOD_0" high="1" low="0"> + <doc>There are 3 methods of normalizing signed numbers:</doc> + <value value="0" name="SGN_NORM_ZERO"><doc>SGN_NORM_ZERO : value / (2^(n-1)-1), so - 128/127 will be less that -1.0, -127/127 will yeild -1.0, 0/127 will yield 0, and 127/127 will yield 1.0 for 8-bit numbers.</doc></value> + <value value="1" name="SGN_NORM_ZERO_CLAMP_MINUS_ONE"><doc>SGN_NORM_ZERO_CLAMP_MINUS_ONE: Same as SGN_NORM_ZERO except -128/127 will yield -1.0 for 8-bit numbers.</doc></value> + <value value="2" name="SGN_NORM_NO_ZERO"><doc>SGN_NORM_NO_ZERO: (2 * value + 1)/2^n, so - 128 will yield -255/255 = -1.0, 127 will yield 255/255 = 1.0, but 0 will yield 1/255 != 0.</doc></value> + </bitfield> + <bitfield name="SGN_NORM_METHOD_1" high="3" low="2"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_2" high="5" low="4"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_3" high="7" low="6"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_4" high="9" low="8"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_5" high="11" low="10"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_6" high="13" low="12"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_7" high="15" low="14"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_8" high="17" low="16"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_9" high="19" low="18"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_10" high="21" low="20"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_11" high="23" low="22"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_12" high="25" low="24"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_13" high="27" low="26"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_14" high="29" low="28"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + <bitfield name="SGN_NORM_METHOD_15" high="31" low="30"> + <doc>See SGN_NORM_METHOD_0</doc> + </bitfield> + </reg32> + <reg32 name="VAP_PVS_CODE_CNTL_0" access="rw" offset="0x22D0"> + <doc>Programmable Vertex Shader Code Control Register 0</doc> + <bitfield name="PVS_FIRST_INST" high="9" low="0"> + <doc>First Instruction to Execute in PVS.</doc> + </bitfield> + <bitfield name="PVS_XYZW_VALID_INST" high="19" low="10"> + <doc>The PVS Instruction which updates the clip coordinate position for the last time. This value is used to lower the processing priority while trivial clip and back-face culling decisions are made. This field must be set to valid instruction.</doc> + </bitfield> + <bitfield name="PVS_LAST_INST" high="29" low="20"> + <doc>Last Instruction (Inclusive) for the PVS to execute.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_PVS_CODE_CNTL_1" access="rw" offset="0x22D8"> + <doc>Programmable Vertex Shader Code Control Register 1</doc> + <bitfield name="PVS_LAST_VTX_SRC_INST" high="9" low="0"> + <doc>The PVS Instruction which uses the Input Vertex Memory for the last time. This value is used to free up the Input Vertex Slots ASAP. This field must be set to a valid instruction.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_PVS_CONST_CNTL" access="rw" offset="0x22D4"> + <doc>Programmable Vertex Shader Constant Control Register</doc> + <bitfield name="PVS_CONST_BASE_OFFSET" high="7" low="0"> + <doc>Vector Offset into PVS constant memory to the start of the constants for the current shader</doc> + </bitfield> + <bitfield name="PVS_MAX_CONST_ADDR" high="23" low="16"> + <doc>The maximum constant address which should be generated by the shader (Inst Const Addr + Addr Register). If the address which is generated by the shader is outside the range of 0 to PVS_MAX_CONST_ADDR, then (0,0,0,0) is returned as the source operand data.</doc> + </bitfield> + </reg32> + <stripe offset="0x2230" stride="0x0004" length="16"> + <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS" access="rw" offset="0x0000"> + <doc>Programmable Vertex Shader Flow Control Addresses Register 0</doc> + <bitfield name="PVS_FC_ACT_ADRS_0" high="7" low="0"> + <doc>This field defines the last PVS instruction to execute prior to the control flow redirection. JUMP - The last instruction executed prior to the jump LOOP - The last instruction executed prior to the loop (init loop counter/inc) JSR - The last instruction executed prior to the jump to the subroutine.</doc> + </bitfield> + <bitfield name="PVS_FC_LOOP_CNT_JMP_INST_0" high="15" low="8"> + <doc>This field has multiple definitions as follows: JUMP - The instruction address to jump to. LOOP - The loop count. *Note loop count of 0 must be replaced by a jump. JSR - The instruction address to jump to (first inst of subroutine).</doc> + </bitfield> + <bitfield name="PVS_FC_LAST_INST_0" high="23" low="16"> + <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - The last instruction of the loop. JSR - The last instruction of the subroutine.</doc> + </bitfield> + <bitfield name="PVS_FC_RTN_INST_0" high="31" low="24"> + <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS + 1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1)</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_PVS_FLOW_CNTL_OPC" access="rw" offset="0x22DC"> + <doc>Programmable Vertex Shader Flow Control Opcode Register</doc> + <bitfield name="PVS_FC_OPC_0" high="1" low="0"> + <doc>This opcode field determines what type of control flow instruction to execute. 0 = NO_OP 1 = JUMP 2 = LOOP 3 = JSR (Jump to Subroutine)</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_1" high="3" low="2"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_2" high="5" low="4"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_3" high="7" low="6"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_4" high="9" low="8"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_5" high="11" low="10"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_6" high="13" low="12"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_7" high="15" low="14"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_8" high="17" low="16"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_9" high="19" low="18"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_10" high="21" low="20"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_11" high="23" low="22"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_12" high="25" low="24"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_13" high="27" low="26"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_14" high="29" low="28"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + <bitfield name="PVS_FC_OPC_15" high="31" low="30"> + <doc>See PVS_FC_OPC_0.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_PVS_STATE_FLUSH_REG" access="rw" offset="0x2284" /> + <reg32 name="VAP_PVS_VECTOR_DATA_REG" access="rw" offset="0x2204" /> + <reg32 name="VAP_PVS_VECTOR_DATA_REG_128" access="w" offset="0x2208" /> + <reg32 name="VAP_PVS_VECTOR_INDX_REG" access="rw" offset="0x2200"> + <doc></doc> + <bitfield name="OCTWORD_OFFSET" high="10" low="0"> + <doc>Octword offset to begin writing.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_PVS_VTX_TIMEOUT_REG" access="rw" offset="0x2288" /> + <reg32 name="VAP_VF_MAX_VTX_INDX" access="rw" offset="0x2134"> + <doc>Maximum Vertex Indx Clamp</doc> + <bitfield name="MAX_INDX" high="23" low="0"> + <doc>If index to be fetched is larger than this value, the fetch indx is set to MAX_INDX</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VF_MIN_VTX_INDX" access="rw" offset="0x2138"> + <doc>Minimum Vertex Indx Clamp</doc> + <bitfield name="MIN_INDX" high="23" low="0"> + <doc>If index to be fetched is smaller than this value, the fetch indx is set to MIN_INDX</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VPORT_XOFFSET" access="rw" offset="0x209C"> + <doc>Viewport Transform X Offset</doc> + </reg32> + <reg32 name="VAP_VPORT_XSCALE" access="rw" offset="0x2098"> + <doc>Viewport Transform X Scale Factor</doc> + </reg32> + <reg32 name="VAP_VPORT_YOFFSET" access="rw" offset="0x20A4"> + <doc>Viewport Transform Y Offset</doc> + </reg32> + <reg32 name="VAP_VPORT_YSCALE" access="rw" offset="0x20A0"> + <doc>Viewport Transform Y Scale Factor</doc> + </reg32> + <reg32 name="VAP_VPORT_ZOFFSET" access="rw" offset="0x20AC"> + <doc>Viewport Transform Z Offset</doc> + </reg32> + <reg32 name="VAP_VPORT_ZSCALE" access="rw" offset="0x20A8"> + <doc>Viewport Transform Z Scale Factor</doc> + </reg32> + <reg32 name="VAP_VTE_CNTL" access="rw" offset="0x20B0"> + <doc>Viewport Transform Engine Control</doc> + <bitfield name="VPORT_X_SCALE_ENA" high="0" low="0"> + <doc>Viewport Transform Scale Enable for X component</doc> + </bitfield> + <bitfield name="VPORT_X_OFFSET_ENA" high="1" low="1"> + <doc>Viewport Transform Offset Enable for X component</doc> + </bitfield> + <bitfield name="VPORT_Y_SCALE_ENA" high="2" low="2"> + <doc>Viewport Transform Scale Enable for Y component</doc> + </bitfield> + <bitfield name="VPORT_Y_OFFSET_ENA" high="3" low="3"> + <doc>Viewport Transform Offset Enable for Y component</doc> + </bitfield> + <bitfield name="VPORT_Z_SCALE_ENA" high="4" low="4"> + <doc>Viewport Transform Scale Enable for Z component</doc> + </bitfield> + <bitfield name="VPORT_Z_OFFSET_ENA" high="5" low="5"> + <doc>Viewport Transform Offset Enable for Z component</doc> + </bitfield> + <bitfield name="VTX_XY_FMT" high="8" low="8"> + <doc>Indicates that the incoming X, Y have already been multiplied by 1/W0. If OFF, the Setup Engine will bultiply the X, Y coordinates by 1/W0.,</doc> + </bitfield> + <bitfield name="VTX_Z_FMT" high="9" low="9"> + <doc>Indicates that the incoming Z has already been multiplied by 1/W0. If OFF, the Setup Engine will multiply the Z coordinate by 1/W0.</doc> + </bitfield> + <bitfield name="VTX_W0_FMT" high="10" low="10"> + <doc>Indicates that the incoming W0 is not 1/W0. If ON, the Setup Engine will perform the reciprocal to get 1/W0.</doc> + </bitfield> + <bitfield name="SERIAL_PROC_ENA" high="11" low="11"> + <doc>If set, x,y,z viewport transform are performed serially through a single pipeline instead of in parallel. Used to mimic RL300 design.</doc> + </bitfield> + </reg32> + <stripe offset="0x20C8" stride="0x0005" length="16"> + <reg32 name="VAP_VTX_AOS_ADDR" access="rw" offset="0x0000"> + <doc>Array-of-Structures Address 0</doc> + <bitfield name="VTX_AOS_ADDR0" high="31" low="2"> + <doc>Base Address of the Array of Structures.</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x20C4" stride="0x0000" length="1415"> + <reg32 name="VAP_VTX_AOS_ATTR" access="rw" offset="0x0000"> + <doc>Array-of-Structures Attributes 0 & 1</doc> + <bitfield name="VTX_AOS_COUNT0" high="6" low="0"> + <doc>Number of dwords in this structure.</doc> + </bitfield> + <bitfield name="VTX_AOS_STRIDE0" high="14" low="8"> + <doc>Number of dwords from one array element to the next.</doc> + </bitfield> + <bitfield name="VTX_AOS_COUNT1" high="22" low="16"> + <doc>Number of dwords in this structure.</doc> + </bitfield> + <bitfield name="VTX_AOS_STRIDE1" high="30" low="24"> + <doc>Number of dwords from one array element to the next.</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_VTX_SIZE" access="rw" offset="0x20B4"> + <doc>Vertex Size Specification Register</doc> + <bitfield name="DWORDS_PER_VTX" high="6" low="0"> + <doc>This field specifies the number of DWORDS per vertex to expect when VAP_VF_CNTL.PRIM_WALK is set to Vertex Data (vertex data embedded in command stream). This field is not used for any other PRIM_WALK settings. This field replaces the usage of the VAP_VTX_FMT_0/1 for this purpose in prior implementations.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_DEPTHCLEARVALUE" access="rw" offset="0x4F28"> + <doc>Z Buffer Clear Value</doc> + </reg32> + <reg32 name="ZB_DEPTHOFFSET" access="rw" offset="0x4F20"> + <doc>Z Buffer Address Offset</doc> + <bitfield name="DEPTHOFFSET" high="31" low="5"> + <doc>2K aligned Z buffer address offset for macro tiles.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_DEPTHPITCH" access="rw" offset="0x4F24"> + <doc>Z Buffer Pitch and Endian Control</doc> + <bitfield name="DEPTHPITCH" high="13" low="2"> + <doc>Z buffer pitch in multiples of 4 pixels.</doc> + </bitfield> + <bitfield name="DEPTHMACROTILE" high="16" low="16"> + <doc>Specifies whether Z buffer is macro-tiled. macro-tiles are 2K aligned</doc> + <value value="0" name="MACRO_TILING_DISABLED"><doc>macro tiling disabled</doc></value> + <value value="1" name="MACRO_TILING_ENABLED"><doc>macro tiling enabled</doc></value> + </bitfield> + <bitfield name="DEPTHMICROTILE" high="18" low="17"> + <doc>Specifies whether Z buffer is micro-tiled. micro-tiles is 32 bytes</doc> + <value value="0" name="32_BYTE_CACHE_LINE_IS_LINEAR"><doc>32 byte cache line is linear</doc></value> + <value value="1" name="32_BYTE_CACHE_LINE_IS_TILED"><doc>32 byte cache line is tiled</doc></value> + <value value="2" name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE"><doc>32 byte cache line is tiled square (only applies to 16-bit pixels)</doc></value> + </bitfield> + <bitfield name="DEPTHENDIAN" high="20" low="19"> + <doc>Specifies endian control for the Z buffer.</doc> + <value value="0" name="NO_SWAP"><doc>No swap</doc></value> + <value value="1" name="WORD_SWAP"><doc>Word swap</doc></value> + <value value="2" name="DWORD_SWAP"><doc>Dword swap</doc></value> + <value value="3" name="HALF_DWORD_SWAP"><doc>Half Dword swap</doc></value> + </bitfield> + </reg32> + <reg32 name="ZB_DEPTHXY_OFFSET" access="rw" offset="0x4F60"> + <doc>Depth buffer X and Y coordinate offset</doc> + <bitfield name="DEPTHX_OFFSET" high="11" low="1"> + <doc>X coordinate offset. multiple of 32 . Bits 4:0 have to be zero</doc> + </bitfield> + <bitfield name="DEPTHY_OFFSET" high="27" low="17"> + <doc>Y coordinate offset. multiple of 32 . Bits 4:0 have to be zero</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_DWORD" access="rw" offset="0x4F4C"> + <doc>Hierarchical Z Data</doc> + </reg32> + <reg32 name="ZB_HIZ_PITCH" access="rw" offset="0x4F54"> + <doc>Hierarchical Z Pitch</doc> + <bitfield name="HIZ_PITCH" high="13" low="4"> + <doc>Pitch used in HiZ address computation.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_STENCILREFMASK" access="rw" offset="0x4F08"> + <doc>Stencil Reference Value and Mask</doc> + <bitfield name="STENCILREF" high="7" low="0"> + <doc>Specifies the reference stencil value.</doc> + </bitfield> + <bitfield name="STENCILMASK" high="15" low="8"> + <doc>This value is ANDed with both the reference and the current stencil value prior to the stencil test.</doc> + </bitfield> + <bitfield name="STENCILWRITEMASK" high="23" low="16"> + <doc>Specifies the write mask for the stencil planes.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_ZCACHE_CTLSTAT" access="rw" offset="0x4F18"> + <doc>Z Buffer Cache Control/Status</doc> + <bitfield name="ZC_FLUSH" high="0" low="0"> + <doc>Setting this bit flushes the dirty data from the Z cache. Unless ZC_FREE bit is also set, the tags in the cache remain valid. A purge is achieved by setting both ZC_FLUSH and ZC_FREE. This is a sticky bit and it clears itself at the end of the operation.</doc> + <value value="0" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="1" name="FLUSH_AND_FREE_Z_CACHE_LINES"><doc>Flush and Free Z cache lines</doc></value> + </bitfield> + <bitfield name="ZC_FREE" high="1" low="1"> + <doc>Setting this bit invalidates the Z cache tags. Unless ZC_FLUSH bit is also set, the cachelines are not written to memory. A purge is achieved by setting both ZC_FLUSH and ZC_FREE. This is a sticky bit that clears itself at the end of the operation.</doc> + <value value="0" name="NO_EFFECT"><doc>No effect</doc></value> + <value value="1" name="FREE_Z_CACHE_LINES"><doc>Free Z cache lines (invalidate)</doc></value> + </bitfield> + <bitfield name="ZC_BUSY" high="31" low="31"> + <doc>This bit is unused ...</doc> + <value value="0" name="IDLE"><doc>Idle</doc></value> + <value value="1" name="BUSY"><doc>Busy</doc></value> + </bitfield> + </reg32> + <reg32 name="ZB_ZPASS_ADDR" access="rw" offset="0x4F5C"> + <doc>Z Buffer Z Pass Counter Address</doc> + <bitfield name="ZPASS_ADDR" high="31" low="2"> + <doc>Writing this location with a DWORD address causes the value in ZB_ZPASS_DATA to be written to main memory at the location pointed to by this address. NOTE: R300 has 2 pixel pipes. Broadcasting this address causes both pipes to write their ZPASS value to the same address. There is no guarantee which pipe will write last. So when writing to this register, the GA needs to be programmed to send the write command to pipe 0. Then a different address needs to be written to pipe 1. Then both pipes should be enabled for further register writes.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_ZPASS_DATA" access="rw" offset="0x4F58"> + <doc>Z Buffer Z Pass Counter Data</doc> + </reg32> + <reg32 name="ZB_ZTOP" access="rw" offset="0x4F14"> + <doc></doc> + <bitfield name="ZTOP" high="0" low="0"> + <doc></doc> + <value value="0" name="Z_IS_AT_THE_BOTTOM_OF_THE_PIPE"><doc>Z is at the bottom of the pipe, after the fog unit.</doc></value> + <value value="1" name="Z_IS_AT_THE_TOP_OF_THE_PIPE"><doc>Z is at the top of the pipe, after the scan unit.</doc></value> + </bitfield> + </reg32> +</group> + +<group name="r300_regs" prepend="R300_"> + <reg32 name="RB3D_AARESOLVE_CTL" access="rw" offset="0x4E88"> + <doc>Resolve Buffer Control. Unpipelined</doc> + <bitfield name="AARESOLVE_MODE" high="0" low="0"> + <doc>Specifies if the color buffer is in resolve mode. The cache must be empty before changing this register.</doc> + <use-enum ref="ENUM0" /> + </bitfield> + <bitfield name="AARESOLVE_GAMMA" high="1" low="1"> + <doc>Specifies the gamma and degamma to be applied to the samples before and after filtering, respectively.</doc> + <use-enum ref="ENUM1" /> + </bitfield> + </reg32> + <reg32 name="RB3D_BLENDCNTL" access="rw" offset="0x4E04"> + <doc>Alpha Blend Control for Color Channels. Pipelined through the blender.</doc> + <bitfield name="ALPHA_BLEND_ENABLE" high="0" low="0"> + <doc>Allow alpha blending with the destination.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="SEPARATE_ALPHA_ENABLE" high="1" low="1"> + <doc>Enables use of RB3D_ABLENDCNTL</doc> + <use-enum ref="ENUM6" /> + </bitfield> + <bitfield name="READ_ENABLE" high="2" low="2"> + <doc>When blending is enabled, this enables memory reads. Memory reads will still occur when this is disabled if they are for reasons not related to blending.</doc> + <use-enum ref="ENUM7" /> + </bitfield> + <bitfield name="DISCARD_SRC_PIXELS" high="5" low="3"> + <doc>Discard pixels when blending is enabled based on the src color.</doc> + <value value="0" name="DISABLE"><doc>Disable</doc></value> + <value value="1" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha == 0</doc></value> + <value value="2" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color == 0</doc></value> + <value value="3" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 0) && (src color == 0)</doc></value> + <value value="4" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha == 1</doc></value> + <value value="5" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color == 1</doc></value> + <value value="6" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 1) && (src color == 1)</doc></value> + </bitfield> + <bitfield name="COMB_FCN" high="14" low="12"> + <doc>Combine Function , Allows modification of how the SRCBLEND and DESTBLEND are combined.</doc> + <use-enum ref="ENUM2" /> + </bitfield> + <bitfield name="SRCBLEND" high="21" low="16"> + <doc>Source Blend Function , Alpha blending function (SRC).</doc> + <use-enum ref="ENUM3" /> + </bitfield> + <bitfield name="DESTBLEND" high="29" low="24"> + <doc>Destination Blend Function , Alpha blending function (DST).</doc> + <use-enum ref="ENUM4" /> + </bitfield> + </reg32> + <reg32 name="RB3D_CCTL" access="rw" offset="0x4E00"> + <doc>Unpipelined.</doc> + <bitfield name="NUM_MULTIWRITES" high="6" low="5"> + <doc>A quad is replicated and written to this many buffers.</doc> + <use-enum ref="ENUM9" /> + </bitfield> + <bitfield name="CLRCMP_FLIPE_ENABLE" high="7" low="7"> + <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. This is used to ensure 3D data does not get chromakeyed away by logic in the backend.</doc> + <use-enum ref="ENUM10" /> + </bitfield> + <bitfield name="AA_COMPRESSION_ENABLE" high="9" low="9"> + <doc>Enables AA color compression. The cache must be empty before this is changed.</doc> + <use-enum ref="ENUM11" /> + </bitfield> + <bitfield name="Reserved" high="10" low="10"> + <doc>Set to 0</doc> + </bitfield> + </reg32> + <stripe offset="0x4E38" stride="0x0004" length="4"> + <reg32 name="RB3D_COLORPITCH" access="rw" offset="0x0000"> + <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> + <bitfield name="COLORPITCH" high="13" low="1"> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + </bitfield> + <bitfield name="COLORTILE" high="16" low="16"> + <doc>Denotes whether the 3D destination is in macrotiled format.</doc> + <use-enum ref="ENUM12" /> + </bitfield> + <bitfield name="COLORMICROTILE" high="18" low="17"> + <doc>Denotes whether the 3D destination is in microtiled format.</doc> + <use-enum ref="ENUM13" /> + </bitfield> + <bitfield name="COLORENDIAN" high="20" low="19"> + <doc>Specifies endian control for the color buffer.</doc> + <use-enum ref="ENUM14" /> + </bitfield> + <bitfield name="COLORFORMAT" high="24" low="21"> + <doc>3D destination color format.</doc> + <value value="3" name="ARGB1555"><doc>ARGB1555</doc></value> + <value value="4" name="RGB565"><doc>RGB565</doc></value> + <value value="6" name="ARGB8888"><doc>ARGB8888</doc></value> + <value value="7" name="ARGB32323232"><doc>ARGB32323232</doc></value> + <value value="9" name="I8"><doc>I8</doc></value> + <value value="10" name="ARGB16161616"><doc>ARGB16161616</doc></value> + <value value="11" name="YUV422_PACKED"><doc>YUV422 packed (VYUY)</doc></value> + <value value="12" name="YUV422_PACKED"><doc>YUV422 packed (YVYU)</doc></value> + <value value="13" name="UV88"><doc>UV88</doc></value> + <value value="15" name="ARGB4444"><doc>ARGB4444</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="RB3D_COLOR_CHANNEL_MASK" access="rw" offset="0x4E0C"> + <doc>3D Color Channel Mask. If all the channels used in the current color format are disabled, then the cb will discard all the incoming quads. Pipelined through the blender.</doc> + <bitfield name="BLUE_MASK" high="0" low="0"> + <doc>mask bit for blue channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="GREEN_MASK" high="1" low="1"> + <doc>mask bit for green channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="RED_MASK" high="2" low="2"> + <doc>mask bit for red channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="ALPHA_MASK" high="3" low="3"> + <doc>mask bit for alpha channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + </reg32> + <reg32 name="RB3D_COLOR_CLEAR_VALUE" access="rw" offset="0x4E14"> + <doc>Clear color that is used when the color mask is set to 00. Unpipelined.</doc> + </reg32> + <reg32 name="RB3D_CONSTANT_COLOR" access="rw" offset="0x4E10"> + <doc>Constant color used by the blender. Pipelined through the blender.</doc> + <bitfield name="BLUE" high="7" low="0"> + <doc>blue constant color</doc> + </bitfield> + <bitfield name="GREEN" high="15" low="8"> + <doc>green constant color</doc> + </bitfield> + <bitfield name="RED" high="23" low="16"> + <doc>red constant color</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="24"> + <doc>alpha constant color</doc> + </bitfield> + </reg32> + <reg32 name="FG_ALPHA_FUNC" access="rw" offset="0x4BD4"> + <doc>Alpha Function</doc> + <bitfield name="AF_VAL" high="7" low="0"> + <doc>Specifies the alpha compare value.</doc> + </bitfield> + <bitfield name="AF_FUNC" high="10" low="8"> + <doc>Specifies the alpha compare function.</doc> + <use-enum ref="ENUM22" /> + </bitfield> + <bitfield name="AF_EN" high="11" low="11"> + <doc>Enables/Disables alpha compare function.</doc> + <use-enum ref="ENUM23" /> + </bitfield> + <bitfield name="AM_EN" high="16" low="16"> + <doc>Enables/Disables alpha-to-mask function.</doc> + <use-enum ref="ENUM24" /> + </bitfield> + <bitfield name="AM_CFG" high="17" low="17"> + <doc>Specfies number of sub-pixel samples for alpha-to-mask function.</doc> + <use-enum ref="ENUM25" /> + </bitfield> + <bitfield name="DITH_EN" high="20" low="20"> + <doc>Enables/Disables RGB Dithering.</doc> + <use-enum ref="ENUM26" /> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_B" access="rw" offset="0x4BD0"> + <doc>Blue Component of Fog Color</doc> + <bitfield name="BLUE" high="9" low="0"> + <doc>Blue component of fog color; (0.9) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_G" access="rw" offset="0x4BCC"> + <doc>Green Component of Fog Color</doc> + <bitfield name="GREEN" high="9" low="0"> + <doc>Green component of fog color; (0.9) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_R" access="rw" offset="0x4BC8"> + <doc>Red Component of Fog Color</doc> + <bitfield name="RED" high="9" low="0"> + <doc>Red component of fog color; (0.9) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_FACTOR" access="rw" offset="0x4BC4"> + <doc>Constant Factor for Fog Blending</doc> + <bitfield name="FACTOR" high="9" low="0"> + <doc>Constant fog factor; fixed (0.9) format.</doc> + </bitfield> + </reg32> + <reg32 name="GA_ENHANCE" access="rw" offset="0x4274"> + <doc>GA Enhancement Register</doc> + <bitfield name="DEADLOCK_CNTL" high="0" low="0"> + <doc>TCL/GA Deadlock control.</doc> + <use-enum ref="ENUM32" /> + </bitfield> + <bitfield name="FASTSYNC_CNTL" high="1" low="1"> + <doc>Enables Fast register/primitive switching</doc> + <use-enum ref="ENUM33" /> + </bitfield> + </reg32> + <reg32 name="GA_LINE_CNTL" access="rw" offset="0x4234"> + <doc>Line control</doc> + <bitfield name="WIDTH" high="15" low="0"> + <doc>1/2 width of line, in subpixels; (16.0) fixed format.</doc> + </bitfield> + <bitfield name="END_TYPE" high="17" low="16"> + <doc>Specifies how ends of lines should be drawn.</doc> + <use-enum ref="ENUM34" /> + </bitfield> + </reg32> + <reg32 name="GA_OFFSET" access="rw" offset="0x4290"> + <doc>Specifies x & y offsets for vertex data after conversion to FP.</doc> + <bitfield name="X_OFFSET" high="15" low="0"> + <doc>Specifies X offset in S15 format (subpixels).</doc> + </bitfield> + <bitfield name="Y_OFFSET" high="31" low="16"> + <doc>Specifies Y offset in S15 format (subpixels).</doc> + </bitfield> + </reg32> + <reg32 name="GA_POINT_SIZE" access="rw" offset="0x421C"> + <doc>Dimensions for Points</doc> + <bitfield name="HEIGHT" high="15" low="0"> + <doc>1/2 Height of point; fixed (16.0), subpixel format.</doc> + </bitfield> + <bitfield name="WIDTH" high="31" low="16"> + <doc>1/2 Width of point; fixed (16.0), subpixel format.</doc> + </bitfield> + </reg32> + <reg32 name="GA_ROUND_MODE" access="rw" offset="0x428C"> + <doc>Specifies the rouding mode for geometry & color SPFP to FP conversions.</doc> + <bitfield name="GEOMETRY_ROUND" high="1" low="0"> + <doc>Trunc (0) or round to nearest (1) for geometry (XY).</doc> + <use-enum ref="ENUM38" /> + </bitfield> + <bitfield name="COLOR_ROUND" high="3" low="2"> + <doc>Trunc (0) or round to nearest (1) for colors (RGBA).</doc> + <use-enum ref="ENUM38" /> + </bitfield> + <bitfield name="RGB_CLAMP" high="4" low="4"> + <doc>Specifies SPFP color clamp range of [0,1] or [-8,8] for RGB.</doc> + <value value="0" name="CLAMP_TO"><doc>Clamp to [0,1.0] for RGB</doc></value> + <value value="1" name="CLAMP_TO"><doc>Clamp to [-7.9999, 7.9999] for RGB</doc></value> + </bitfield> + <bitfield name="ALPHA_CLAMP" high="5" low="5"> + <doc>Specifies SPFP alpha clamp range of [0,1] or [-8,8].</doc> + <value value="0" name="CLAMP_TO"><doc>Clamp to [0,1.0] for Alpha</doc></value> + <value value="1" name="CLAMP_TO"><doc>Clamp to [-7.9999, 7.9999] for Alpha</doc></value> + </bitfield> + </reg32> + <reg32 name="GA_SOFT_RESET" access="rw" offset="0x429C"> + <doc>Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert.</doc> + <bitfield name="SOFT_RESET_COUNT" high="15" low="0"> + <doc>Count in cycles (def 256).</doc> + </bitfield> + </reg32> + <reg32 name="GA_SOLID_BA" access="rw" offset="0x4280"> + <doc>Specifies blue & alpha components of fill color.</doc> + <bitfield name="COLOR_ALPHA" high="15" low="0"> + <doc>Component alpha value. (S3.12)</doc> + </bitfield> + <bitfield name="COLOR_BLUE" high="31" low="16"> + <doc>Component blue value. (S3.12)</doc> + </bitfield> + </reg32> + <reg32 name="GA_SOLID_RG" access="rw" offset="0x427C"> + <doc>Specifies red & green components of fill color.</doc> + <bitfield name="COLOR_GREEN" high="15" low="0"> + <doc>Component green value (S3.12).</doc> + </bitfield> + <bitfield name="COLOR_RED" high="31" low="16"> + <doc>Component red value (S3.12).</doc> + </bitfield> + </reg32> + <reg32 name="GB_ENABLE" access="rw" offset="0x4008"> + <doc>Specifies top of Raster pipe specific enable controls.</doc> + <bitfield name="POINT_STUFF_ENABLE" high="0" low="0"> + <doc>Specifies if points will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM43" /> + </bitfield> + <bitfield name="LINE_STUFF_ENABLE" high="1" low="1"> + <doc>Specifies if lines will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM44" /> + </bitfield> + <bitfield name="TRIANGLE_STUFF_ENABLE" high="2" low="2"> + <doc>Specifies if triangles will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM45" /> + </bitfield> + <bitfield name="STENCIL_AUTO" high="5" low="4"> + <doc>Specifies if the auto dec/inc stencil mode should be enabled, and how.</doc> + <use-enum ref="ENUM46" /> + </bitfield> + <bitfield name="TEX0_SOURCE" high="17" low="16"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_0"><doc>Replicate VAP source texture coordinates 0 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX1_SOURCE" high="19" low="18"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_1"><doc>Replicate VAP source texture coordinates 1 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX2_SOURCE" high="21" low="20"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_2"><doc>Replicate VAP source texture coordinates 2 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX3_SOURCE" high="23" low="22"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_3"><doc>Replicate VAP source texture coordinates 3 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX4_SOURCE" high="25" low="24"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_4"><doc>Replicate VAP source texture coordinates 4 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX5_SOURCE" high="27" low="26"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_5"><doc>Replicate VAP source texture coordinates 5 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX6_SOURCE" high="29" low="28"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_6"><doc>Replicate VAP source texture coordinates 6 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + <bitfield name="TEX7_SOURCE" high="31" low="30"> + <doc>Specifies the source of the texture coordinates for this texture.</doc> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_7"><doc>Replicate VAP source texture coordinates 7 (S,T,[R,Q]).</doc></value> + <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> + <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> + </bitfield> + </reg32> + <reg32 name="GB_FIFO_SIZE" access="rw" offset="0x4024"> + <doc>Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written</doc> + <bitfield name="SC_IFIFO_SIZE" high="1" low="0"> + <doc>Size of scan converter input FIFO (XYZ)</doc> + <use-enum ref="ENUM55" /> + </bitfield> + <bitfield name="SC_TZFIFO_SIZE" high="3" low="2"> + <doc>Size of scan converter top-of-pipe Z FIFO</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="SC_BFIFO_SIZE" high="5" low="4"> + <doc>Size of scan converter input FIFO (B)</doc> + <use-enum ref="ENUM55" /> + </bitfield> + <bitfield name="RS_TFIFO_SIZE" high="7" low="6"> + <doc>Size of ras input FIFO (Texture)</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="RS_CFIFO_SIZE" high="9" low="8"> + <doc>Size of ras input FIFO (Color)</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="US_RAM_SIZE" high="11" low="10"> + <doc>Size of us RAM</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="US_OFIFO_SIZE" high="13" low="12"> + <doc>Size of us output FIFO (RGBA)</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="US_WFIFO_SIZE" high="15" low="14"> + <doc>Size of us output FIFO (W)</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="RS_HIGHWATER_COL" high="18" low="16"> + <doc>High water mark for RS color FIFO (0-7, default 7)</doc> + </bitfield> + <bitfield name="RS_HIGHWATER_TEX" high="21" low="19"> + <doc>High water mark for RS texture FIFO (0-7, default 7)</doc> + </bitfield> + <bitfield name="US_OFIFO_HIGHWATER" high="23" low="22"> + <doc>High water mark for US output FIFO (0-12, default 4)</doc> + <use-enum ref="ENUM58" /> + </bitfield> + <bitfield name="US_CUBE_FIFO_HIGHWATER" high="27" low="24"> + <doc>High water mark for US texture output FIFO (0-15, default 11)</doc> + </bitfield> + </reg32> + <reg32 name="GB_MSPOS0" access="rw" offset="0x4010"> + <doc>Specifies the position of multisamples 0 through 2</doc> + <bitfield name="MS_X0" high="3" low="0"> + <doc>Specifies the x and y position (in subpixels) of multisample 0</doc> + </bitfield> + <bitfield name="MS_Y0" high="7" low="4"> + <doc>Specifies the x and y position (in subpixels) of multisample 0</doc> + </bitfield> + <bitfield name="MS_X1" high="11" low="8"> + <doc>Specifies the x and y position (in subpixels) of multisample 1</doc> + </bitfield> + <bitfield name="MS_Y1" high="15" low="12"> + <doc>Specifies the x and y position (in subpixels) of multisample 1</doc> + </bitfield> + <bitfield name="MS_X2" high="19" low="16"> + <doc>Specifies the x and y position (in subpixels) of multisample 2</doc> + </bitfield> + <bitfield name="MS_Y2" high="23" low="20"> + <doc>Specifies the x and y position (in subpixels) of multisample 2</doc> + </bitfield> + <bitfield name="MSBD0_Y" high="27" low="24"> + <doc>Specifies the minimum y distance (in subpixels) between the pixel edge and the multisample bounding box. This value is used in the tile scan converter</doc> + </bitfield> + <bitfield name="MSBD0_X" high="31" low="28"> + <doc>msbd0_x[2:0] specifies the minimum x distance (in subpixels) between the pixel edge and the multisample bounding box. This value is used in the tile scan converter. The special case value of 8 is represented by msbd0_x[2:0]=7. msbd0_x[3] is used to force a bounding box based tile scan conversion instead of an intercept based one. This value should always be set to 0.</doc> + </bitfield> + </reg32> + <reg32 name="GB_MSPOS1" access="rw" offset="0x4014"> + <doc>Specifies the position of multisamples 3 through 5</doc> + <bitfield name="MS_X3" high="3" low="0"> + <doc>Specifies the x and y position (in subpixels) of multisample 3</doc> + </bitfield> + <bitfield name="MS_Y3" high="7" low="4"> + <doc>Specifies the x and y position (in subpixels) of multisample 3</doc> + </bitfield> + <bitfield name="MS_X4" high="11" low="8"> + <doc>Specifies the x and y position (in subpixels) of multisample 4</doc> + </bitfield> + <bitfield name="MS_Y4" high="15" low="12"> + <doc>Specifies the x and y position (in subpixels) of multisample 4</doc> + </bitfield> + <bitfield name="MS_X5" high="19" low="16"> + <doc>Specifies the x and y position (in subpixels) of multisample 5</doc> + </bitfield> + <bitfield name="MS_Y5" high="23" low="20"> + <doc>Specifies the x and y position (in subpixels) of multisample 5</doc> + </bitfield> + <bitfield name="MSBD1" high="27" low="24"> + <doc>Specifies the minimum distance (in subpixels) between the pixel edge and the multisample bounding box. This value is used in the quad scan converter</doc> + </bitfield> + </reg32> + <reg32 name="GB_SELECT" access="rw" offset="0x401C"> + <doc>Specifies various polygon specific selects (fog, depth, perspective).</doc> + <bitfield name="FOG_SELECT" high="2" low="0"> + <doc>Specifies source for outgoing (GA to SU) fog value.</doc> + <use-enum ref="ENUM59" /> + </bitfield> + <bitfield name="DEPTH_SELECT" high="3" low="3"> + <doc>Specifies source for outgoing (GA/SU & SU/RAS) depth value.</doc> + <use-enum ref="ENUM60" /> + </bitfield> + <bitfield name="W_SELECT" high="4" low="4"> + <doc>Specifies source for outgoing (1/W) value, used to disable perspective correct colors/textures.</doc> + <use-enum ref="ENUM61" /> + </bitfield> + </reg32> + <reg32 name="GB_TILE_CONFIG" access="rw" offset="0x4018"> + <doc>Specifies the graphics pipeline configuration for rasterization</doc> + <bitfield name="ENABLE" high="0" low="0"> + <doc>Enables tiling, otherwise all tiles receive all polygons.</doc> + <use-enum ref="ENUM62" /> + </bitfield> + <bitfield name="PIPE_COUNT" high="3" low="1"> + <doc>Specifies the number of active pipes and contexts.</doc> + <value value="0" name="RV350"><doc>RV350</doc></value> + <value value="3" name="R300"><doc>R300</doc></value> + </bitfield> + <bitfield name="TILE_SIZE" high="5" low="4"> + <doc>Specifies width & height (square), in pixels.</doc> + <value value="0" name="8_PIXELS"><doc>8 pixels (not supported by zb/cb)</doc></value> + <value value="1" name="16_PIXELS"><doc>16 pixels</doc></value> + <value value="2" name="32_PIXELS"><doc>32 pixels (not supported by zb/cb)</doc></value> + </bitfield> + <bitfield name="SUPER_SIZE" high="8" low="6"> + <doc>Specifies number of tiles and config in super chip configuration.</doc> + <use-enum ref="ENUM65" /> + </bitfield> + <bitfield name="SUPER_X" high="11" low="9"> + <doc>X Location of chip within super tile.</doc> + </bitfield> + <bitfield name="SUPER_Y" high="14" low="12"> + <doc>Y Location of chip within super tile.</doc> + </bitfield> + <bitfield name="SUPER_TILE" high="15" low="15"> + <doc>Tile location of chip in a multi super tile config (Super size of 2,8,32 or 128).</doc> + <use-enum ref="ENUM66" /> + </bitfield> + <bitfield name="SUBPIXEL" high="16" low="16"> + <doc>Specifies the subpixel precision.</doc> + <use-enum ref="ENUM67" /> + </bitfield> + <bitfield name="QUADS_PER_RAS" high="18" low="17"> + <doc>unused</doc> + </bitfield> + <bitfield name="BB_SCAN" high="19" low="19"> + <doc>unused</doc> + </bitfield> + </reg32> + <reg32 name="RS_COUNT" access="rw" offset="0x4300"> + <doc>This register specifies the rasterizer input packet configuration</doc> + <bitfield name="IT_COUNT" high="6" low="0"> + <doc>Specifies the total number of texture address components contained in the rasterizer input packet (0:32).</doc> + </bitfield> + <bitfield name="IC_COUNT" high="10" low="7"> + <doc>Specifies the total number of colors contained in the rasterizer input packet (0:4).</doc> + </bitfield> + <bitfield name="W_COUNT" high="11" low="11"> + <doc>Specifies the total number of w values contained in the rasterizer input packet (0 or 1).</doc> + </bitfield> + <bitfield name="W_ADDR" high="17" low="12"> + <doc>Specifies the relative rasterizer input packet location of w (if w_count==1)</doc> + </bitfield> + <bitfield name="HIRES_EN" high="18" low="18"> + <doc>Enable high resolution texture coordinate output when q is equal to 1</doc> + </bitfield> + </reg32> + <stripe offset="0x4330" stride="0x0004" length="16"> + <reg32 name="RS_INST" access="rw" offset="0x0000"> + <doc>This table specifies what happens during each rasterizer instruction</doc> + <bitfield name="TEX_ID" high="2" low="0"> + <doc>Specifies the index (into the RS_IP table) of the texture address output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="TEX_CN" high="5" low="3"> + <doc>Write enable for texture address</doc> + <use-enum ref="ENUM68" /> + </bitfield> + <bitfield name="TEX_ADDR" high="10" low="6"> + <doc>Specifies the destination address (within the current pixel stack frame) of the texture address output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="COL_ID" high="13" low="11"> + <doc>Specifies the index (into the RS_IP table) of the color output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="COL_CN" high="16" low="14"> + <doc>Write enable for color</doc> + <value value="0" name="NO_WRITE"><doc>No write - color not valid</doc></value> + <value value="1" name="WRITE"><doc>write - color valid</doc></value> + </bitfield> + <bitfield name="COL_ADDR" high="21" low="17"> + <doc>Specifies the destination address (within the current pixel stack frame) of the color output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="TEX_ADJ" high="22" low="22"> + <doc>Specifies whether to sample texture coordinates at the real or adjusted pixel centers</doc> + <use-enum ref="ENUM70" /> + </bitfield> + <bitfield name="COL_BIAS" high="24" low="23"> + <doc>unused</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="RS_INST_COUNT" access="rw" offset="0x4304"> + <doc>This register specifies the number of rasterizer instructions</doc> + <bitfield name="INST_COUNT" high="3" low="0"> + <doc>Number of rasterizer instructions (1:16)</doc> + </bitfield> + <bitfield name="W_EN" high="4" low="4"> + <doc>Specifies that the rasterizer needs to generate w</doc> + </bitfield> + <bitfield name="TX_OFFSET" high="7" low="5"> + <doc>Defines texture coordinate offset (based on min/max coordinate range of triangle) used to minimize or eliminate peroidic errors on texels sampled right on their edges</doc> + <value value="0" name="0"><doc>0.0</doc></value> + <value value="1" name="RANGE"><doc>range/8K</doc></value> + <value value="2" name="RANGE"><doc>range/16K</doc></value> + <value value="3" name="RANGE"><doc>range/32K</doc></value> + <value value="4" name="RANGE"><doc>range/64K</doc></value> + <value value="5" name="RANGE"><doc>range/128K</doc></value> + <value value="6" name="RANGE"><doc>range/256K</doc></value> + <value value="7" name="RANGE"><doc>range/512K</doc></value> + </bitfield> + </reg32> + <stripe offset="0x4310" stride="0x0000" length="8"> + <reg32 name="RS_IP" access="rw" offset="0x0000"> + <doc>This table specifies the source location and format for up to 8 texture addresses (i[0]:i[7]) and four colors (c[0]:c[3])</doc> + <bitfield name="TEX_PTR" high="5" low="0"> + <doc>Specifies the relative rasterizer input packet location of texture address (i[i]).</doc> + </bitfield> + <bitfield name="COL_PTR" high="8" low="6"> + <doc>Specifies the relative rasterizer input packet location of the color (c[i]).</doc> + </bitfield> + <bitfield name="COL_FMT" high="12" low="9"> + <doc>Specifies the format of the color (c[i]).</doc> + <use-enum ref="ENUM72" /> + </bitfield> + <bitfield name="SEL_S" high="15" low="13"> + <doc>Source select for S, T, R, and Q</doc> + <use-enum ref="ENUM73" /> + </bitfield> + <bitfield name="SEL_T" high="18" low="16"> + <doc>Source select for S, T, R, and Q</doc> + <use-enum ref="ENUM73" /> + </bitfield> + <bitfield name="SEL_R" high="21" low="19"> + <doc>Source select for S, T, R, and Q</doc> + <use-enum ref="ENUM73" /> + </bitfield> + <bitfield name="SEL_Q" high="24" low="22"> + <doc>Source select for S, T, R, and Q</doc> + <use-enum ref="ENUM73" /> + </bitfield> + </reg32> + </stripe> + <reg32 name="SC_EDGERULE" access="rw" offset="0x43A8"> + <doc>Edge rules - what happens when an edge falls exactly on a sample point</doc> + <bitfield name="ER_TRI" high="4" low="0"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_POINT" high="9" low="5"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM75" /> + </bitfield> + <bitfield name="ER_LINE_LR" high="14" low="10"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM75" /> + </bitfield> + <bitfield name="ER_LINE_RL" high="19" low="15"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM75" /> + </bitfield> + <bitfield name="ER_LINE_TB" high="24" low="20"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM75" /> + </bitfield> + <bitfield name="ER_LINE_BT" high="29" low="25"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM75" /> + </bitfield> + </reg32> + <reg32 name="SU_REG_DEST" access="rw" offset="0x42C8"> + <doc>SU Raster pipe destination select for registers</doc> + <bitfield name="SELECT" high="3" low="0"> + <doc>Select which of the 2 pipes (enable per pipe) to send register read/write to. b0: P0 enable, b3: P1 enable</doc> + <value value="0" name="P0_ENABLE"><doc>P0 enable, b</doc></value> + <value value="3" name="P1_ENABLE"><doc>P1 enable</doc></value> + </bitfield> + </reg32> + <reg32 name="SU_TEX_WRAP" access="rw" offset="0x42A0"> + <doc>Enables for Cylindrical Wrapping</doc> + <bitfield name="T0C0" high="0" low="0"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0"><doc>Disable cylindrical wrapping for tex 0 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0"><doc>Enable cylindrical wrapping for tex 0 comp 0.</doc></value> + </bitfield> + <bitfield name="T0C1" high="1" low="1"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1"><doc>Disable cylindrical wrapping for tex 0 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1"><doc>Enable cylindrical wrapping for tex 0 comp 1.</doc></value> + </bitfield> + <bitfield name="T0C2" high="2" low="2"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2"><doc>Disable cylindrical wrapping for tex 0 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2"><doc>Enable cylindrical wrapping for tex 0 comp 2.</doc></value> + </bitfield> + <bitfield name="T0C3" high="3" low="3"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3"><doc>Disable cylindrical wrapping for tex 0 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3"><doc>Enable cylindrical wrapping for tex 0 comp 3.</doc></value> + </bitfield> + <bitfield name="T1C0" high="4" low="4"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0"><doc>Disable cylindrical wrapping for tex 1 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0"><doc>Enable cylindrical wrapping for tex 1 comp 0.</doc></value> + </bitfield> + <bitfield name="T1C1" high="5" low="5"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1"><doc>Disable cylindrical wrapping for tex 1 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1"><doc>Enable cylindrical wrapping for tex 1 comp 1.</doc></value> + </bitfield> + <bitfield name="T1C2" high="6" low="6"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2"><doc>Disable cylindrical wrapping for tex 1 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2"><doc>Enable cylindrical wrapping for tex 1 comp 2.</doc></value> + </bitfield> + <bitfield name="T1C3" high="7" low="7"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3"><doc>Disable cylindrical wrapping for tex 1 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3"><doc>Enable cylindrical wrapping for tex 1 comp 3.</doc></value> + </bitfield> + <bitfield name="T2C0" high="8" low="8"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0"><doc>Disable cylindrical wrapping for tex 2 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0"><doc>Enable cylindrical wrapping for tex 2 comp 0.</doc></value> + </bitfield> + <bitfield name="T2C1" high="9" low="9"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1"><doc>Disable cylindrical wrapping for tex 2 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1"><doc>Enable cylindrical wrapping for tex 2 comp 1.</doc></value> + </bitfield> + <bitfield name="T2C2" high="10" low="10"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2"><doc>Disable cylindrical wrapping for tex 2 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2"><doc>Enable cylindrical wrapping for tex 2 comp 2.</doc></value> + </bitfield> + <bitfield name="T2C3" high="11" low="11"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3"><doc>Disable cylindrical wrapping for tex 2 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3"><doc>Enable cylindrical wrapping for tex 2 comp 3.</doc></value> + </bitfield> + <bitfield name="T3C0" high="12" low="12"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0"><doc>Disable cylindrical wrapping for tex 3 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0"><doc>Enable cylindrical wrapping for tex 3 comp 0.</doc></value> + </bitfield> + <bitfield name="T3C1" high="13" low="13"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1"><doc>Disable cylindrical wrapping for tex 3 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1"><doc>Enable cylindrical wrapping for tex 3 comp 1.</doc></value> + </bitfield> + <bitfield name="T3C2" high="14" low="14"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2"><doc>Disable cylindrical wrapping for tex 3 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2"><doc>Enable cylindrical wrapping for tex 3 comp 2.</doc></value> + </bitfield> + <bitfield name="T3C3" high="15" low="15"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3"><doc>Disable cylindrical wrapping for tex 3 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3"><doc>Enable cylindrical wrapping for tex 3 comp 3.</doc></value> + </bitfield> + <bitfield name="T4C0" high="16" low="16"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0"><doc>Disable cylindrical wrapping for tex 4 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0"><doc>Enable cylindrical wrapping for tex 4 comp 0.</doc></value> + </bitfield> + <bitfield name="T4C1" high="17" low="17"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1"><doc>Disable cylindrical wrapping for tex 4 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1"><doc>Enable cylindrical wrapping for tex 4 comp 1.</doc></value> + </bitfield> + <bitfield name="T4C2" high="18" low="18"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2"><doc>Disable cylindrical wrapping for tex 4 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2"><doc>Enable cylindrical wrapping for tex 4 comp 2.</doc></value> + </bitfield> + <bitfield name="T4C3" high="19" low="19"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3"><doc>Disable cylindrical wrapping for tex 4 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3"><doc>Enable cylindrical wrapping for tex 4 comp 3.</doc></value> + </bitfield> + <bitfield name="T5C0" high="20" low="20"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0"><doc>Disable cylindrical wrapping for tex 5 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0"><doc>Enable cylindrical wrapping for tex 5 comp 0.</doc></value> + </bitfield> + <bitfield name="T5C1" high="21" low="21"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1"><doc>Disable cylindrical wrapping for tex 5 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1"><doc>Enable cylindrical wrapping for tex 5 comp 1.</doc></value> + </bitfield> + <bitfield name="T5C2" high="22" low="22"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2"><doc>Disable cylindrical wrapping for tex 5 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2"><doc>Enable cylindrical wrapping for tex 5 comp 2.</doc></value> + </bitfield> + <bitfield name="T5C3" high="23" low="23"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3"><doc>Disable cylindrical wrapping for tex 5 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3"><doc>Enable cylindrical wrapping for tex 5 comp 3.</doc></value> + </bitfield> + <bitfield name="T6C0" high="24" low="24"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0"><doc>Disable cylindrical wrapping for tex 6 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0"><doc>Enable cylindrical wrapping for tex 6 comp 0.</doc></value> + </bitfield> + <bitfield name="T6C1" high="25" low="25"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1"><doc>Disable cylindrical wrapping for tex 6 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1"><doc>Enable cylindrical wrapping for tex 6 comp 1.</doc></value> + </bitfield> + <bitfield name="T6C2" high="26" low="26"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2"><doc>Disable cylindrical wrapping for tex 6 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2"><doc>Enable cylindrical wrapping for tex 6 comp 2.</doc></value> + </bitfield> + <bitfield name="T6C3" high="27" low="27"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3"><doc>Disable cylindrical wrapping for tex 6 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3"><doc>Enable cylindrical wrapping for tex 6 comp 3.</doc></value> + </bitfield> + <bitfield name="T7C0" high="28" low="28"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0"><doc>Disable cylindrical wrapping for tex 7 comp 0.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0"><doc>Enable cylindrical wrapping for tex 7 comp 0.</doc></value> + </bitfield> + <bitfield name="T7C1" high="29" low="29"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1"><doc>Disable cylindrical wrapping for tex 7 comp 1.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1"><doc>Enable cylindrical wrapping for tex 7 comp 1.</doc></value> + </bitfield> + <bitfield name="T7C2" high="30" low="30"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2"><doc>Disable cylindrical wrapping for tex 7 comp 2.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2"><doc>Enable cylindrical wrapping for tex 7 comp 2.</doc></value> + </bitfield> + <bitfield name="T7C3" high="31" low="31"> + <doc></doc> + <value value="0" name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3"><doc>Disable cylindrical wrapping for tex 7 comp 3.</doc></value> + <value value="1" name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3"><doc>Enable cylindrical wrapping for tex 7 comp 3.</doc></value> + </bitfield> + </reg32> + <stripe offset="0x45C0" stride="0x0004" length="16"> + <reg32 name="TX_BORDER_COLOR" access="rw" offset="0x0000"> + <doc>Border Color for Map 0</doc> + </reg32> + </stripe> + <stripe offset="0x4580" stride="0x0004" length="16"> + <reg32 name="TX_CHROMA_KEY" access="rw" offset="0x0000"> + <doc>Texture Chroma Key for Map 0</doc> + </reg32> + </stripe> + <reg32 name="TX_ENABLE" access="rw" offset="0x4104"> + <doc>Texture Enables for Maps 0 to 15</doc> + <bitfield name="TEX_0_ENABLE" high="0" low="0"> + <doc>Texture Map 0 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T0(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_1_ENABLE" high="1" low="1"> + <doc>Texture Map 1 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T1(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_2_ENABLE" high="2" low="2"> + <doc>Texture Map 2 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T2(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_3_ENABLE" high="3" low="3"> + <doc>Texture Map 3 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T3(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_4_ENABLE" high="4" low="4"> + <doc>Texture Map 4 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T4(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_5_ENABLE" high="5" low="5"> + <doc>Texture Map 5 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T5(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_6_ENABLE" high="6" low="6"> + <doc>Texture Map 6 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T6(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_7_ENABLE" high="7" low="7"> + <doc>Texture Map 7 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T7(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_8_ENABLE" high="8" low="8"> + <doc>Texture Map 8 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T8(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_9_ENABLE" high="9" low="9"> + <doc>Texture Map 9 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T9(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_10_ENABLE" high="10" low="10"> + <doc>Texture Map 10 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T10(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_11_ENABLE" high="11" low="11"> + <doc>Texture Map 11 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T11(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_12_ENABLE" high="12" low="12"> + <doc>Texture Map 12 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T12(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_13_ENABLE" high="13" low="13"> + <doc>Texture Map 13 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T13(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_14_ENABLE" high="14" low="14"> + <doc>Texture Map 14 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T14(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + <bitfield name="TEX_15_ENABLE" high="15" low="15"> + <doc>Texture Map 15 Enable.</doc> + <value value="0" name="DISABLE"><doc>Disable, T15(ARGB) = 1,0,0,0</doc></value> + <value value="1" name="ENABLE"><doc>Enable</doc></value> + </bitfield> + </reg32> + <stripe offset="0x4400" stride="0x0004" length="16"> + <reg32 name="TX_FILTER0" access="rw" offset="0x0000"> + <doc>Texture Filter State for Map 0</doc> + <bitfield name="CLAMP_S" high="2" low="0"> + <doc>Clamp mode for first texture coordinate</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="CLAMP_T" high="5" low="3"> + <doc>Clamp mode for second texture coordinate</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="CLAMP_R" high="8" low="6"> + <doc>Clamp mode for third texture coordinate</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="MAG_FILTER" high="10" low="9"> + <doc>Filter used when texture is magnified</doc> + <use-enum ref="ENUM137" /> + </bitfield> + <bitfield name="MIN_FILTER" high="12" low="11"> + <doc>Filter used when texture is minified</doc> + <use-enum ref="ENUM137" /> + </bitfield> + <bitfield name="MIP_FILTER" high="14" low="13"> + <doc>Filter used between mipmap levels</doc> + <use-enum ref="ENUM138" /> + </bitfield> + <bitfield name="VOL_FILTER" high="16" low="15"> + <doc>Filter used between layers of a volume</doc> + <use-enum ref="ENUM139" /> + </bitfield> + <bitfield name="MAX_MIP_LEVEL" high="20" low="17"> + <doc>LOD index of largest (finest) mipmap to use (0 is largest). Ranges from 0 to NUM_LEVELS.</doc> + </bitfield> + <bitfield name="ID" high="31" low="28"> + <doc>Logical id for this physical texture</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4440" stride="0x0004" length="16"> + <reg32 name="TX_FILTER1" access="rw" offset="0x0000"> + <doc>Texture Filter State for Map 0</doc> + <bitfield name="CHROMA_KEY_MODE" high="1" low="0"> + <doc>Chroma Key Mode</doc> + <use-enum ref="ENUM140" /> + </bitfield> + <bitfield name="MC_ROUND" high="2" low="2"> + <doc>Bilinear rounding mode</doc> + <use-enum ref="ENUM141" /> + </bitfield> + <bitfield name="LOD_BIAS" high="12" low="3"> + <doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias measured in mipmap levels. Added to the signed, computed LOD before the LOD is clamped.</doc> + </bitfield> + <bitfield name="MC_COORD_TRUNCATE" high="14" low="14"> + <doc>MPEG coordinate truncation mode</doc> + <use-enum ref="ENUM142" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4480" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT0" access="rw" offset="0x0000"> + <doc>Texture Format State for Map 0</doc> + <bitfield name="TXWIDTH" high="10" low="0"> + <doc>Image width - 1. The largest image is 2048 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc> + </bitfield> + <bitfield name="TXHEIGHT" high="21" low="11"> + <doc>Image height - 1. The largest image is 2048 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc> + </bitfield> + <bitfield name="TXDEPTH" high="25" low="22"> + <doc>LOG2(depth) of volume texture</doc> + </bitfield> + <bitfield name="NUM_LEVELS" high="29" low="26"> + <doc>Number of mipmap levels minus 1. Ranges from 0 to 11. Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc> + </bitfield> + <bitfield name="PROJECTED" high="30" low="30"> + <doc>Specifies whether texture coords are projected.</doc> + <use-enum ref="ENUM143" /> + </bitfield> + <bitfield name="TXPITCH_EN" high="31" low="31"> + <doc>Indicates when TXPITCH should be used instead of TXWIDTH for image addressing</doc> + <use-enum ref="ENUM144" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x44C0" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT1" access="rw" offset="0x0000"> + <doc>Texture Format State for Map 0</doc> + <bitfield name="TXFORMAT" high="4" low="0"> + <doc>Texture Format. Components are numbered right to left. Parenthesis indicate typical uses of each format.</doc> + <value value="0" name="TX_FMT_8"><doc>TX_FMT_8</doc></value> + <value value="1" name="TX_FMT_16"><doc>TX_FMT_16</doc></value> + <value value="2" name="TX_FMT_4_4"><doc>TX_FMT_4_4</doc></value> + <value value="3" name="TX_FMT_8_8"><doc>TX_FMT_8_8</doc></value> + <value value="4" name="TX_FMT_16_16"><doc>TX_FMT_16_16</doc></value> + <value value="5" name="TX_FMT_3_3_2"><doc>TX_FMT_3_3_2</doc></value> + <value value="6" name="TX_FMT_5_6_5"><doc>TX_FMT_5_6_5</doc></value> + <value value="7" name="TX_FMT_6_5_5"><doc>TX_FMT_6_5_5</doc></value> + <value value="8" name="TX_FMT_11_11_10"><doc>TX_FMT_11_11_10</doc></value> + <value value="9" name="TX_FMT_10_11_11"><doc>TX_FMT_10_11_11</doc></value> + <value value="10" name="TX_FMT_4_4_4_4"><doc>TX_FMT_4_4_4_4</doc></value> + <value value="11" name="TX_FMT_1_5_5_5"><doc>TX_FMT_1_5_5_5</doc></value> + <value value="12" name="TX_FMT_8_8_8_8"><doc>TX_FMT_8_8_8_8</doc></value> + <value value="13" name="TX_FMT_2_10_10_10"><doc>TX_FMT_2_10_10_10</doc></value> + <value value="14" name="TX_FMT_16_16_16_16"><doc>TX_FMT_16_16_16_16</doc></value> + <value value="18" name="TX_FMT_Y8"><doc>TX_FMT_Y8</doc></value> + <value value="19" name="TX_FMT_AVYU444"><doc>TX_FMT_AVYU444</doc></value> + <value value="20" name="TX_FMT_VYUY422"><doc>TX_FMT_VYUY422</doc></value> + <value value="21" name="TX_FMT_YVYU422"><doc>TX_FMT_YVYU422</doc></value> + <value value="22" name="TX_FMT_16_MPEG"><doc>TX_FMT_16_MPEG</doc></value> + <value value="23" name="TX_FMT_16_16_MPEG"><doc>TX_FMT_16_16_MPEG</doc></value> + <value value="24" name="TX_FMT_16F"><doc>TX_FMT_16f</doc></value> + <value value="25" name="TX_FMT_16F_16F"><doc>TX_FMT_16f_16f</doc></value> + <value value="26" name="TX_FMT_16F_16F_16F_16F"><doc>TX_FMT_16f_16f_16f_16f</doc></value> + <value value="27" name="TX_FMT_32F"><doc>TX_FMT_32f</doc></value> + <value value="28" name="TX_FMT_32F_32F"><doc>TX_FMT_32f_32f</doc></value> + <value value="29" name="TX_FMT_32F_32F_32F_32F"><doc>TX_FMT_32f_32f_32f_32f</doc></value> + <value value="30" name="TX_FMT_W24_FP"><doc>TX_FMT_W24_FP</doc></value> + </bitfield> + <bitfield name="SIGNED_COMP0" high="5" low="5"> + <doc>Component0 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component0 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component0 filter should interpret texel data as signed</doc></value> + </bitfield> + <bitfield name="SIGNED_COMP1" high="6" low="6"> + <doc>Component1 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component1 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component1 filter should interpret texel data as signed</doc></value> + </bitfield> + <bitfield name="SIGNED_COMP2" high="7" low="7"> + <doc>Component2 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component2 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component2 filter should interpret texel data as signed</doc></value> + </bitfield> + <bitfield name="SIGNED_COMP3" high="8" low="8"> + <doc>Component3 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component3 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component3 filter should interpret texel data as signed</doc></value> + </bitfield> + <bitfield name="SEL_ALPHA" high="11" low="9"> + <doc>Specifies swizzling for alpha channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component0 for the Alpha Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component1 for the Alpha Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component2 for the Alpha Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component3 for the Alpha Channel.</doc></value> + <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_ALPHA_CHANNEL"><doc>Select the value 0 for the Alpha Channel.</doc></value> + <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_ALPHA_CHANNEL"><doc>Select the value 1 for the Alpha Channel.</doc></value> + </bitfield> + <bitfield name="SEL_RED" high="14" low="12"> + <doc>Specifies swizzling for red channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_RED_CHANNEL"><doc>Select Texture Component0 for the Red Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_RED_CHANNEL"><doc>Select Texture Component1 for the Red Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_RED_CHANNEL"><doc>Select Texture Component2 for the Red Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_RED_CHANNEL"><doc>Select Texture Component3 for the Red Channel.</doc></value> + <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_RED_CHANNEL"><doc>Select the value 0 for the Red Channel.</doc></value> + <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_RED_CHANNEL"><doc>Select the value 1 for the Red Channel.</doc></value> + </bitfield> + <bitfield name="SEL_GREEN" high="17" low="15"> + <doc>Specifies swizzling for green channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component0 for the Green Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component1 for the Green Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component2 for the Green Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component3 for the Green Channel.</doc></value> + <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_GREEN_CHANNEL"><doc>Select the value 0 for the Green Channel.</doc></value> + <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_GREEN_CHANNEL"><doc>Select the value 1 for the Green Channel.</doc></value> + </bitfield> + <bitfield name="SEL_BLUE" high="20" low="18"> + <doc>Specifies swizzling for blue channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component0 for the Blue Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component1 for the Blue Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component2 for the Blue Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component3 for the Blue Channel.</doc></value> + <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_BLUE_CHANNEL"><doc>Select the value 0 for the Blue Channel.</doc></value> + <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_BLUE_CHANNEL"><doc>Select the value 1 for the Blue Channel.</doc></value> + </bitfield> + <bitfield name="GAMMA" high="21" low="21"> + <doc>Optionally remove gamma from texture before passing to shader. Only apply to 8bit or less components.</doc> + <use-enum ref="ENUM154" /> + </bitfield> + <bitfield name="YUV_TO_RGB" high="23" low="22"> + <doc>YUV to RGB conversion mode</doc> + <use-enum ref="ENUM155" /> + </bitfield> + <bitfield name="SWAP_YUV" high="24" low="24"> + <doc></doc> + <use-enum ref="ENUM156" /> + </bitfield> + <bitfield name="TEX_COORD_TYPE" high="26" low="25"> + <doc>Specifies coordinate type.</doc> + <use-enum ref="ENUM157" /> + </bitfield> + <bitfield name="CACHE" high="31" low="27"> + <doc>Multi-texture performance can be optimized and made deterministic by assigning textures to separate regions under sw control.</doc> + <use-enum ref="ENUM158" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4500" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT2" access="rw" offset="0x0000"> + <doc>Texture Format State for Map 0</doc> + <bitfield name="TXPITCH" high="13" low="0"> + <doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN is asserted. Pitch is given as number of texels minus one. Maximum pitch is 16K texels.</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4540" stride="0x0004" length="16"> + <reg32 name="TX_OFFSET" access="rw" offset="0x0000"> + <doc>Texture Offset State for Map 0</doc> + <bitfield name="ENDIAN_SWAP" high="1" low="0"> + <doc>Endian Control</doc> + <use-enum ref="ENUM159" /> + </bitfield> + <bitfield name="MACRO_TILE" high="2" low="2"> + <doc>Macro Tile Control</doc> + <use-enum ref="ENUM160" /> + </bitfield> + <bitfield name="MICRO_TILE" high="4" low="3"> + <doc>Micro Tile Control</doc> + <use-enum ref="ENUM161" /> + </bitfield> + <bitfield name="TXOFFSET" high="31" low="5"> + <doc>32-byte aligned pointer to base map</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x47C0" stride="0x0004" length="64"> + <reg32 name="US_ALU_ALPHA_ADDR" access="rw" offset="0x0000"> + <doc>This table specifies the Alpha source addresses for up to 64 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> + <bitfield name="ADDR0" high="5" low="0"> + <doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDR1" high="11" low="6"> + <doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDR2" high="17" low="12"> + <doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDRD" high="22" low="18"> + <doc>Specifies the address of the pixel stack frame register to which the Alpha result of this instruction is to be written.</doc> + </bitfield> + <bitfield name="WMASK" high="23" low="23"> + <doc>Specifies whether or not to write the Alpha component of the result for this instruction to the pixel stack frame.</doc> + <value value="0" name="NONE"><doc>NONE: No not write register.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only.</doc></value> + </bitfield> + <bitfield name="OMASK" high="24" low="24"> + <doc>Specifies whether or not to write the Alpha component of the result of this instruction to the output fifo.</doc> + <value value="0" name="NONE"><doc>NONE: No not write output.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only.</doc></value> + </bitfield> + <bitfield name="TARGET" high="26" low="25"> + <doc>Specifies which frame buffer target to write to.</doc> + <use-enum ref="ENUM164" /> + </bitfield> + <bitfield name="OMASK_W" high="27" low="27"> + <doc>Specifies whether or not to write the Alpha component of the result of this instuction to the depth output fifo.</doc> + <value value="0" name="NONE"><doc>NONE: No not write output to w.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only.</doc></value> + </bitfield> + <bitfield name="STAT_WE" high="31" low="28"> + <doc>Specifies which components (R,G,B,A) contribute to the stat count (see performance counter field in US_CONFIG).</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x49C0" stride="0x0004" length="64"> + <reg32 name="US_ALU_ALPHA_INST" access="rw" offset="0x0000"> + <doc>ALU Alpha Instruction</doc> + <bitfield name="SEL_A" high="4" low="0"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM166" /> + </bitfield> + <bitfield name="MOD_A" high="6" low="5"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SEL_B" high="11" low="7"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM166" /> + </bitfield> + <bitfield name="MOD_B" high="13" low="12"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SEL_C" high="18" low="14"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM166" /> + </bitfield> + <bitfield name="MOD_C" high="20" low="19"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SRCP_OP" high="22" low="21"> + <doc>Specifies how the pre-subtract value (SRCP) is computed</doc> + <use-enum ref="ENUM168" /> + </bitfield> + <bitfield name="OP" high="26" low="23"> + <doc>Specifies the operand for this instruction.</doc> + <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> + <value value="1" name="OP_DP"><doc>OP_DP: Result = dot product from RGB ALU</doc></value> + <value value="2" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> + <value value="3" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> + <value value="5" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> + <value value="6" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> + <value value="7" name="OP_FRC"><doc>OP_FRC: Result = fractional(A)</doc></value> + <value value="8" name="OP_EX"><doc>OP_EX</doc></value> + <value value="2" name="RESULT"><doc>Result = 2^^A</doc></value> + <value value="9" name="OP_LN"><doc>OP_LN</doc></value> + <value value="2" name="RESULT"><doc>Result = log2(A)</doc></value> + <value value="10" name="OP_RCP"><doc>OP_RCP: Result = 1/A</doc></value> + <value value="11" name="OP_RSQ"><doc>OP_RSQ: Result = 1/sqrt(A)</doc></value> + </bitfield> + <bitfield name="OMOD" high="29" low="27"> + <doc>Specifies the output modifier for this instruction.</doc> + <use-enum ref="ENUM170" /> + </bitfield> + <bitfield name="CLAMP" high="30" low="30"> + <doc>Specifies clamp mode for this instruction.</doc> + <use-enum ref="ENUM171" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x46C0" stride="0x0004" length="64"> + <reg32 name="US_ALU_RGB_ADDR" access="rw" offset="0x0000"> + <doc>This table specifies the RGB source and destination addresses for up to 64 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> + <bitfield name="ADDR0" high="5" low="0"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDR1" high="11" low="6"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDR2" high="17" low="12"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc> + </bitfield> + <bitfield name="ADDRD" high="22" low="18"> + <doc>Specifies the address of the pixel stack frame register to which the RGB result of this instruction is to be written.</doc> + </bitfield> + <bitfield name="WMASK" high="25" low="23"> + <doc>Specifies which of the R, G, and B components of the result of this instruction are written to the pixel stack frame.</doc> + <use-enum ref="ENUM172" /> + </bitfield> + <bitfield name="OMASK" high="28" low="26"> + <doc>Specifies which of the R, G, and B components of the result of this instruction are written to the output fifo.</doc> + <use-enum ref="ENUM172" /> + </bitfield> + <bitfield name="TARGET" high="30" low="29"> + <doc>Specifies which frame buffer target to write to.</doc> + <use-enum ref="ENUM164" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x48C0" stride="0x0004" length="64"> + <reg32 name="US_ALU_RGB_INST" access="rw" offset="0x0000"> + <doc>ALU RGB Instruction</doc> + <bitfield name="SEL_A" high="4" low="0"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM173" /> + </bitfield> + <bitfield name="MOD_A" high="6" low="5"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SEL_B" high="11" low="7"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM173" /> + </bitfield> + <bitfield name="MOD_B" high="13" low="12"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SEL_C" high="18" low="14"> + <doc>Specifies the operand and component select for inputs A, B, and C.</doc> + <use-enum ref="ENUM173" /> + </bitfield> + <bitfield name="MOD_C" high="20" low="19"> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="SRCP_OP" high="22" low="21"> + <doc>Specifies how the pre-subtract value (SRCP) is computed</doc> + <use-enum ref="ENUM174" /> + </bitfield> + <bitfield name="OP" high="26" low="23"> + <doc>Specifies the operand for this instruction.</doc> + <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> + <value value="1" name="OP_DP"><doc>OP_DP</doc></value> + <value value="3" name="RESULT"><doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> + <value value="2" name="OP_DP"><doc>OP_DP</doc></value> + <value value="4" name="RESULT"><doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc></value> + <value value="3" name="OP_D2A"><doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc></value> + <value value="4" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> + <value value="5" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> + <value value="7" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> + <value value="8" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> + <value value="9" name="OP_FRC"><doc>OP_FRC: Result = frac(A)</doc></value> + <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq from Alpha ALU</doc></value> + </bitfield> + <bitfield name="OMOD" high="29" low="27"> + <doc>Specifies the output modifier for this instruction.</doc> + <use-enum ref="ENUM170" /> + </bitfield> + <bitfield name="CLAMP" high="30" low="30"> + <doc>Specifies clamp mode for this instruction.</doc> + <use-enum ref="ENUM171" /> + </bitfield> + <bitfield name="NOP" high="31" low="31"> + <doc>Specifies whether to insert a NOP instruction after this. This would get specified in order to meet dependency requirements for the pre-subtract inputs.</doc> + <value value="0" name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE"><doc>Do not insert NOP instruction after this one</doc></value> + <value value="1" name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE"><doc>Insert a NOP instruction after this one</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4610" stride="0x0004" length="4"> + <reg32 name="US_CODE_ADDR" access="rw" offset="0x0000"> + <doc>Code Address for Indirection Levels 0 to 3</doc> + <bitfield name="ALU_START" high="5" low="0"> + <doc>Specifies the start address of the ALU microcode segment associated with the current indirection level (0:63)</doc> + </bitfield> + <bitfield name="ALU_SIZE" high="11" low="6"> + <doc>Specifies the size of the ALU microcode segment associated with the current indirection level (1:64)</doc> + </bitfield> + <bitfield name="TEX_START" high="16" low="12"> + <doc>Specifies the start address of the texture microcode segment associated with the current indirection level (0:31)</doc> + </bitfield> + <bitfield name="TEX_SIZE" high="21" low="17"> + <doc>Specifies the size of the texture microcode segment associated with the current indirection level (1:32)</doc> + </bitfield> + <bitfield name="RGBA_OUT" high="22" low="22"> + <doc>Indicates at least one RGBA output instruction at this level</doc> + </bitfield> + <bitfield name="W_OUT" high="23" low="23"> + <doc>Indicates at least one W output instruction at this level</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_CODE_OFFSET" access="rw" offset="0x4608"> + <doc>Specifies the offset and size for the ALU and Texture micrcode. These values are used to support relocatable code, and to support register writes to the code store without requiring a pipeline flush.</doc> + <bitfield name="ALU_OFFSET" high="5" low="0"> + <doc>Specifies the offset for the ALU code. This value is added to the ALU_START field in the US_CODE_ADDR registers (0:63)</doc> + </bitfield> + <bitfield name="ALU_SIZE" high="12" low="6"> + <doc>Specifies the total size for the ALU code for all levels (0:64)</doc> + </bitfield> + <bitfield name="TEX_OFFSET" high="17" low="13"> + <doc>Specifies the offset for the Texture code. This value is added to the TEX_START field in the US_CODE_ADDR registers (0:31)</doc> + </bitfield> + <bitfield name="TEX_SIZE" high="23" low="18"> + <doc>Specifies the total size for the Texture code for all levels (0:32)</doc> + </bitfield> + </reg32> + <reg32 name="US_CONFIG" access="rw" offset="0x4600"> + <doc>Shader Configuration</doc> + <bitfield name="NLEVEL" high="2" low="0"> + <doc>Specifies the valid indirection levels.</doc> + <value value="0" name="LEVEL_3_ONLY"><doc>Level 3 only (normal DX7-style texturing)</doc></value> + <value value="1" name="LEVELS_2_AND_3"><doc>Levels 2 and 3 (DX8-style bump mapping)</doc></value> + <value value="2" name="LEVELS_1"><doc>Levels 1, 2, and 3</doc></value> + <value value="3" name="LEVELS_0"><doc>Levels 0, 1, 2, and 3</doc></value> + </bitfield> + <bitfield name="FIRST_TEX" high="3" low="3"> + <doc>Specifies whether or not the texture code for the first valid level is enabled</doc> + <use-enum ref="ENUM178" /> + </bitfield> + </reg32> + <stripe offset="0x46A4" stride="0x0004" length="4"> + <reg32 name="US_OUT_FMT" access="rw" offset="0x0000"> + <doc>Specifies how the shader output is written to the fog unit for each of up to four render targets</doc> + <bitfield name="OUT_FMT" high="4" low="0"> + <doc>Specifies the number and size of components</doc> + <use-enum ref="ENUM179" /> + </bitfield> + <bitfield name="C0_SEL" high="9" low="8"> + <doc>Specifies the source for components C0, C1, C2, C3</doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C1_SEL" high="11" low="10"> + <doc>Specifies the source for components C0, C1, C2, C3</doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C2_SEL" high="13" low="12"> + <doc>Specifies the source for components C0, C1, C2, C3</doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C3_SEL" high="15" low="14"> + <doc>Specifies the source for components C0, C1, C2, C3</doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="OUT_SIGN" high="19" low="16"> + <doc>Mask specifying whether components C3, C2, C1 and C0 are signed (C4_8, C_16, C2_16 and C4_16 formats only)</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_PIXSIZE" access="rw" offset="0x4604"> + <doc>Shader pixel size. This register specifies the size and partitioning of the current pixel stack frame</doc> + <bitfield name="PIX_SIZE" high="4" low="0"> + <doc>Specifies the total size of the current pixel stack frame (1:32)</doc> + </bitfield> + </reg32> + <stripe offset="0x4620" stride="0x0004" length="32"> + <reg32 name="US_TEX_INST" access="rw" offset="0x0000"> + <doc>Texture Instruction</doc> + <bitfield name="SRC_ADDR" high="4" low="0"> + <doc>Specifies the location (within the shader pixel stack frame) of the texture address for this instruction</doc> + </bitfield> + <bitfield name="DST_ADDR" high="10" low="6"> + <doc>Specifies the location (within the shader pixel stack frame) of the returned texture data for this instruction</doc> + </bitfield> + <bitfield name="TEX_ID" high="14" low="11"> + <doc>Specifies the id of the texture map used for this instruction</doc> + </bitfield> + <bitfield name="INST" high="17" low="15"> + <doc>Specifies the operation taking place for this instruction</doc> + <value value="0" name="NOP"><doc>NOP: Do nothing</doc></value> + <value value="1" name="LD"><doc>LD: Do Texture Lookup (S,T,R)</doc></value> + <value value="2" name="TEXKILL"><doc>TEXKILL: Kill pixel if any component is < 0</doc></value> + <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc></value> + <value value="4" name="LODBIAS"><doc>LODBIAS: Do texture lookup with lod bias</doc></value> + </bitfield> + <bitfield name="OMOD" high="18" low="18"> + <doc>unused</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_W_FMT" access="rw" offset="0x46B4"> + <doc>Specifies the source and format for the Depth (W) value output by the shader</doc> + <bitfield name="W_FMT" high="1" low="0"> + <doc>Format for W</doc> + <value value="0" name="W"><doc>W</doc></value> + <value value="0" name="W_IS_ALWAYS_ZERO"><doc>W is always zero</doc></value> + <value value="1" name="W"><doc>W</doc></value> + <value value="24" name="24"><doc>24-bit fixed point</doc></value> + <value value="2" name="W24_FP"><doc>W24_FP - 24-bit floating point</doc></value> + </bitfield> + <bitfield name="W_SRC" high="2" low="2"> + <doc>Source for W</doc> + <use-enum ref="ENUM183" /> + </bitfield> + </reg32> + <stripe offset="0x4C0C" stride="0x0010" length="32"> + <reg32 name="US_ALU_CONST_A" access="rw" offset="0x0000"> + <doc>Shader Constant Color 0 Alpha Component</doc> + <bitfield name="KA" high="23" low="0"> + <doc>Specifies the alpha component; (S16E7) fixed format.</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4C08" stride="0x0010" length="32"> + <reg32 name="US_ALU_CONST_B" access="rw" offset="0x0000"> + <doc>Shader Constant Color 0 Blue Component</doc> + <bitfield name="KB" high="23" low="0"> + <doc>Specifies the blue component; (S16E7) fixed format.</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4C04" stride="0x0010" length="32"> + <reg32 name="US_ALU_CONST_G" access="rw" offset="0x0000"> + <doc>Shader Constant Color 0 Green Component</doc> + <bitfield name="KG" high="23" low="0"> + <doc>Specifies the green component; (S16E7) fixed format.</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4C00" stride="0x0010" length="32"> + <reg32 name="US_ALU_CONST_R" access="rw" offset="0x0000"> + <doc>Shader Constant Color 0 Red Component</doc> + <bitfield name="KR" high="23" low="0"> + <doc>Specifies the red component; (S16E7) fixed format.</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_CLIP_CNTL" access="rw" offset="0x221C"> + <doc>Control Bits for User Clip Planes and Clipping</doc> + <bitfield name="UCP_ENA_0" high="0" low="0"> + <doc>Enable User Clip Plane 0</doc> + </bitfield> + <bitfield name="UCP_ENA_1" high="1" low="1"> + <doc>Enable User Clip Plane 1</doc> + </bitfield> + <bitfield name="UCP_ENA_2" high="2" low="2"> + <doc>Enable User Clip Plane 2</doc> + </bitfield> + <bitfield name="UCP_ENA_3" high="3" low="3"> + <doc>Enable User Clip Plane 3</doc> + </bitfield> + <bitfield name="UCP_ENA_4" high="4" low="4"> + <doc>Enable User Clip Plane 4</doc> + </bitfield> + <bitfield name="UCP_ENA_5" high="5" low="5"> + <doc>Enable User Clip Plane 5</doc> + </bitfield> + <bitfield name="PS_UCP_MODE" high="15" low="14"> + <doc>0 = Cull using distance from center of point 1 = Cull using radius-based distance from center of point 2 = Cull using radius-based distance from center of point, Expand and Clip on intersection 3 = Always expand and clip as trifan</doc> + </bitfield> + <bitfield name="CLIP_DISABLE" high="16" low="16"> + <doc>Disables clip code generation and clipping process for TCL</doc> + </bitfield> + <bitfield name="UCP_CULL_ONLY_ENA" high="17" low="17"> + <doc>Cull Primitives against UCPS, but don`t clip</doc> + </bitfield> + <bitfield name="BOUNDARY_EDGE_FLAG_ENA" high="18" low="18"> + <doc>If set, boundary edges are highlighted, else they are not highlighted</doc> + </bitfield> + </reg32> + <reg32 name="VAP_CNTL" access="rw" offset="0x2080"> + <doc>Vertex Assembler/Processor Control Register</doc> + <bitfield name="PVS_NUM_SLOTS" high="3" low="0"> + <doc>Specifies the number of vertex slots to be used in the VAP PVS process. A slot represents a single vertex storage location1 across multiple engines (one vertex per engine). By decreasing the number of slots, there is more memory for each vertex, but less parallel processing. Similarly, by increasing the number of slots, thre is less memory per vertex but more vertices being processed in parallel.</doc> + </bitfield> + <bitfield name="PVS_NUM_CNTLRS" high="7" low="4"> + <doc>Specifies the maximum number of controllers to be processing in parallel. In general should be set to max value of TBD. Can be changed for performance analysis.</doc> + </bitfield> + <bitfield name="PVS_NUM_FPUS" high="11" low="8"> + <doc>Specifies the number of Floating Point Units (Vector/Math Engines) to use when processing vertices.</doc> + </bitfield> + <bitfield name="VF_MAX_VTX_NUM" high="21" low="18"> + <doc>This field controls the number of vertices that the vertex fetcher manages for the TCL and Setup Vertex Storage memories (and therefore the number of vertices that can be re-used). This value should be set to 12 for most operation, This number may be modified for performance evaluation. The value is the maximum vertex number used which is one less than the number of vertices (i.e. a 12 means 13 vertices will be used)</doc> + </bitfield> + <bitfield name="DX_CLIP_SPACE_DEF" high="22" low="22"> + <doc>Clip space is defined as:</doc> + <use-enum ref="ENUM184" /> + </bitfield> + </reg32> + <reg32 name="VAP_CNTL_STATUS" access="rw" offset="0x2140"> + <doc>Vertex Assemblen/Processor Control Status</doc> + <bitfield name="VC_SWAP" high="1" low="0"> + <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB Default = 0</doc> + </bitfield> + <bitfield name="PVS_BYPASS" high="8" low="8"> + <doc>The TCL engine is logically or physically removed from the circuit.</doc> + </bitfield> + <bitfield name="PVS_BUSY" high="11" low="11"> + <doc>Transform/Clip/Light (TCL) Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VS_BUSY" high="24" low="24"> + <doc>Vertex Store is Busy. Read-only.</doc> + </bitfield> + <bitfield name="RCP_BUSY" high="25" low="25"> + <doc>Reciprocal Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VTE_BUSY" high="26" low="26"> + <doc>ViewPort Transform Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="MIU_BUSY" high="27" low="27"> + <doc>Memory Interface Unit is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VC_BUSY" high="28" low="28"> + <doc>Vertex Cache is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VF_BUSY" high="29" low="29"> + <doc>Vertex Fetcher is Busy. Read-only.</doc> + </bitfield> + <bitfield name="REGPIPE_BUSY" high="30" low="30"> + <doc>Register Pipeline is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VAP_BUSY" high="31" low="31"> + <doc>VAP Engine is Busy. Read-only.</doc> + </bitfield> + </reg32> + <stripe offset="0x2150" stride="0x0004" length="8"> + <reg32 name="VAP_PROG_STREAM_CNTL" access="rw" offset="0x0000"> + <doc>Programmable Stream Control Word 0</doc> + <bitfield name="DATA_TYPE_0" high="3" low="0"> + <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) * These data types use the SIGNED and NORMALIZE flags described below.</doc> + </bitfield> + <bitfield name="SKIP_DWORDS_0" high="7" low="4"> + <doc>The number of DWORDS to skip (discard) after processing the current element.</doc> + </bitfield> + <bitfield name="DST_VEC_LOC_0" high="12" low="8"> + <doc>The vector address in the input memory to write this element</doc> + </bitfield> + <bitfield name="LAST_VEC_0" high="13" low="13"> + <doc>If set, indicates the last vector of the current vertex stream</doc> + </bitfield> + <bitfield name="SIGNED_0" high="14" low="14"> + <doc>Determines whether fixed point data types are unsigned (0) or 2`s complement signed (1) data types. See NORMALIZE for complete description of affect</doc> + </bitfield> + <bitfield name="NORMALIZE_0" high="15" low="15"> + <doc>Determines whether the fixed to floating point conversion will normalize the value (i.e. fixed point value is all fractional bits) or not (i.e. fixed point value is all integer bits). This table describes the fixed to float conversion results SIGNED NORMALIZE FLT RANGE 0 0 0.0 - (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 0.0 - 1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - 127.0) 1 1 -1.0 - 1.0 where n is the number of bits in the associated fixed point value For signed, normalize conversion, since the fixed point range is not evenly distributed around 0, there are 3 different methods supported by R300. See the VAP_PSC_SGN_NORM_CNTL description for details.</doc> + <use-enum ref="ENUM185" /> + </bitfield> + <bitfield name="SKIP_DWORDS_1" high="23" low="20"> + <doc>See SKIP_DWORDS_0</doc> + </bitfield> + <bitfield name="DST_VEC_LOC_1" high="28" low="24"> + <doc>See DST_VEC_LOC_0</doc> + </bitfield> + <bitfield name="LAST_VEC_1" high="29" low="29"> + <doc>See LAST_VEC_0</doc> + </bitfield> + <bitfield name="SIGNED_1" high="30" low="30"> + <doc>See SIGNED_0</doc> + </bitfield> + <bitfield name="NORMALIZE_1" high="31" low="31"> + <doc>See NORMALIZE_0</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x2290" stride="0x0004" length="16"> + <reg32 name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" access="rw" offset="0x0000"> + <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> + <bitfield name="PVS_FC_LOOP_INIT_VAL_0" high="7" low="0"> + <doc>This field stores the automatic loop index register init value. This is an 8-bit unsigned value 0-255. This field is only used if the corresponding control flow instruction is a loop.</doc> + </bitfield> + <bitfield name="PVS_FC_LOOP_STEP_VAL_0" high="15" low="8"> + <doc>This field stores the automatic loop index register step value. This is an 8-bit 2`s comp signed value -128-127. This field is only used if the corresponding control flow instruction is a loop.</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_VF_CNTL" access="rw" offset="0x2084"> + <doc>Vertex Fetcher Control</doc> + <bitfield name="PRIM_TYPE" high="3" low="0"> + <doc>Primitive Type 0 : None (will not trigger Setup Engine to run) 1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 : Triangle Fan 6 : Triangle Strip 7 : Triangle with wFlags (aka, Rage128 `Type-2` triangles) * 8-11 : Unused 12 : Line Loop 13 : Quad List 14 : Quad Strip 15 : Polygon *Encoding 7 indicates whether a 16-bit word of wFlags is present in the stream of indices arriving when the VTX_AMODE is programmed as a `0`. The Setup Engine just steps over the wFlags word; ignoring it. 0 = Stream contains just indices, as: [ Index1, Index0] [ Index3, Index2] [ Index5, Index4 ] etc... 1 = Stream contains indices and wFlags: [ Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ wFlags, Index5 ] etc...</doc> + </bitfield> + <bitfield name="PRIM_WALK" high="5" low="4"> + <doc>Method of Passing Vertex Data. 0 : State-Based Vertex Data. (Vertex data and tokens embedded in command stream.) 1 = Indexes (Indices embedded in command stream; vertex data to be fetched from memory.) 2 = Vertex List (Vertex data to be fetched from memory.) 3 = Vertex Data (Vertex data embedded in command stream.)</doc> + </bitfield> + <bitfield name="INDEX_SIZE" high="11" low="11"> + <doc>When set, vertex indices are 32-bits/indx, otherwise, 16- bits/indx.</doc> + </bitfield> + <bitfield name="VTX_REUSE_DIS" high="12" low="12"> + <doc>When set, vertex reuse is disabled. DO NOT SET unless PRIM_WALK is Indexes.</doc> + </bitfield> + <bitfield name="DUAL_INDEX_MODE" high="13" low="13"> + <doc>When set, the incoming index is treated as two separate indices. Bits 23-16 are used as the index for AOS 0 (These are 0 for 16-bit indices) Bits 15-0 are used as the index for AOS 1-15. This mode was added specifically for HOS usage</doc> + </bitfield> + <bitfield name="NUM_VERTICES" high="31" low="16"> + <doc>Number of vertices in the command packet.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VTX_NUM_ARRAYS" access="rw" offset="0x20C0"> + <doc>Vertex Array of Structures Control</doc> + <bitfield name="VTX_NUM_ARRAYS" high="4" low="0"> + <doc>The number of arrays required to represent the current vertex type. Each Array is described by the following three fields: VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> + </bitfield> + <bitfield name="VC_FORCE_PREFETCH" high="5" low="5"> + <doc>Force Vertex Data Pre-fetching. If this bit is set, then a 256-bit word will always be fetched, regardless of which dwords are needed. Typically useful when VAP_VF_CNTL.PRIM_WALK is set to Vertex List (Auto-incremented indices).</doc> + </bitfield> + <bitfield name="AOS_0_FETCH_SIZE" high="16" low="16"> + <doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule size 1 = 256-bit granule size This allows the driver to program the fetch size based on DWORDS/VTX/AOS combined with AGP vs. LOC Memory. The general belief is that the granule size should always be 256-bits for LOC memory and AGP8X data, but should be 128-bit for AGP2X/4X data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc> + </bitfield> + <bitfield name="AOS_1_FETCH_SIZE" high="17" low="17"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_2_FETCH_SIZE" high="18" low="18"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_3_FETCH_SIZE" high="19" low="19"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_4_FETCH_SIZE" high="20" low="20"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_5_FETCH_SIZE" high="21" low="21"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_6_FETCH_SIZE" high="22" low="22"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_7_FETCH_SIZE" high="23" low="23"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_8_FETCH_SIZE" high="24" low="24"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_9_FETCH_SIZE" high="25" low="25"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_10_FETCH_SIZE" high="26" low="26"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_11_FETCH_SIZE" high="27" low="27"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_12_FETCH_SIZE" high="28" low="28"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_13_FETCH_SIZE" high="29" low="29"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_14_FETCH_SIZE" high="30" low="30"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_15_FETCH_SIZE" high="31" low="31"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VTX_STATE_CNTL" access="rw" offset="0x2180"> + <doc>VAP Vertex State Control Register</doc> + <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"> + <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"> + <doc>0 : Select Color 1 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"> + <doc>0 : Select Color 2 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"> + <doc>0 : Select Color 3 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"> + <doc>0 : Select Color 4 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"> + <doc>0 : Select Color 5 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"> + <doc>0 : Select Color 6 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"> + <doc>0 : Select Color 7 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"> + <doc>0 : User Color 0 State is NOT updated when User Color 0 is written. 1 : User Color 1 State IS updated when User Color 0 is written.</doc> + </bitfield> + <bitfield name="USE_ADDR_IND_TBL" high="18" low="18"> + <doc>0 : Use vertex state addresses directly to write to vertex state memory. 1 : Use Address Indirection table to write to vertex state memory for lower 64 DWORD addresses.</doc> + </bitfield> + </reg32> + <stripe offset="0x2430" stride="0x0004" length="4"> + <reg32 name="VAP_VTX_ST_BLND_WT" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x232C" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_A" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x2328" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_B" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x2324" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_G" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x2470" stride="0x0004" length="8"> + <reg32 name="VAP_VTX_ST_CLR_PKD" access="w" offset="0x0000" /> + </stripe> + <stripe offset="0x2320" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_R" access="rw" offset="0x0000" /> + </stripe> + <reg32 name="VAP_VTX_ST_DISC_FOG" access="rw" offset="0x2424" /> + <reg32 name="VAP_VTX_ST_EDGE_FLAGS" access="rw" offset="0x245C" /> + <reg32 name="VAP_VTX_ST_END_OF_PKT" access="w" offset="0x24AC" /> + <reg32 name="VAP_VTX_ST_NORM_0_PKD" access="w" offset="0x2498" /> + <reg32 name="VAP_VTX_ST_NORM_0_X" access="rw" offset="0x2310" /> + <reg32 name="VAP_VTX_ST_NORM_0_Y" access="rw" offset="0x2314" /> + <reg32 name="VAP_VTX_ST_NORM_0_Z" access="rw" offset="0x2318" /> + <reg32 name="VAP_VTX_ST_NORM_1_X" access="rw" offset="0x2450" /> + <reg32 name="VAP_VTX_ST_NORM_1_Y" access="rw" offset="0x2454" /> + <reg32 name="VAP_VTX_ST_NORM_1_Z" access="rw" offset="0x2458" /> + <reg32 name="VAP_VTX_ST_PNT_SPRT_SZ" access="rw" offset="0x2420" /> + <reg32 name="VAP_VTX_ST_POS_0_W_4" access="rw" offset="0x230C" /> + <reg32 name="VAP_VTX_ST_POS_0_X_2" access="w" offset="0x2490" /> + <reg32 name="VAP_VTX_ST_POS_0_X_3" access="w" offset="0x24A0" /> + <reg32 name="VAP_VTX_ST_POS_0_X_4" access="rw" offset="0x2300" /> + <reg32 name="VAP_VTX_ST_POS_0_Y_2" access="w" offset="0x2494" /> + <reg32 name="VAP_VTX_ST_POS_0_Y_3" access="w" offset="0x24A4" /> + <reg32 name="VAP_VTX_ST_POS_0_Y_4" access="rw" offset="0x2304" /> + <reg32 name="VAP_VTX_ST_POS_0_Z_3" access="w" offset="0x24A8" /> + <reg32 name="VAP_VTX_ST_POS_0_Z_4" access="rw" offset="0x2308" /> + <reg32 name="VAP_VTX_ST_POS_1_W" access="rw" offset="0x244C" /> + <reg32 name="VAP_VTX_ST_POS_1_X" access="rw" offset="0x2440" /> + <reg32 name="VAP_VTX_ST_POS_1_Y" access="rw" offset="0x2444" /> + <reg32 name="VAP_VTX_ST_POS_1_Z" access="rw" offset="0x2448" /> + <reg32 name="VAP_VTX_ST_PVMS" access="rw" offset="0x231C" /> + <reg32 name="VAP_VTX_ST_SHININESS_0" access="rw" offset="0x2428" /> + <reg32 name="VAP_VTX_ST_SHININESS_1" access="rw" offset="0x242C" /> + <stripe offset="0x23AC" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_Q" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x23A8" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_R" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x23A0" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_S" access="rw" offset="0x0000" /> + </stripe> + <stripe offset="0x23A4" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_T" access="rw" offset="0x0000" /> + </stripe> + <reg32 name="VAP_VTX_ST_USR_CLR_A" access="rw" offset="0x246C" /> + <reg32 name="VAP_VTX_ST_USR_CLR_B" access="rw" offset="0x2468" /> + <reg32 name="VAP_VTX_ST_USR_CLR_G" access="rw" offset="0x2464" /> + <reg32 name="VAP_VTX_ST_USR_CLR_PKD" access="w" offset="0x249C" /> + <reg32 name="VAP_VTX_ST_USR_CLR_R" access="rw" offset="0x2460" /> + <reg32 name="ZB_BW_CNTL" access="rw" offset="0x4F1C"> + <doc>Z Buffer Band-Width Control Bit Defa</doc> + <bitfield name="HIZ_ENABLE" high="0" low="0"> + <doc>Enables hierarchical Z.</doc> + <use-enum ref="ENUM187" /> + </bitfield> + <bitfield name="HIZ_MIN" high="1" low="1"> + <doc></doc> + <use-enum ref="ENUM188" /> + </bitfield> + <bitfield name="FAST_FILL" high="2" low="2"> + <doc></doc> + <use-enum ref="ENUM189" /> + </bitfield> + <bitfield name="RD_COMP_ENABLE" high="3" low="3"> + <doc>Enables reading of compressed Z data from memory to the cache.</doc> + <use-enum ref="ENUM190" /> + </bitfield> + <bitfield name="WR_COMP_ENABLE" high="4" low="4"> + <doc>Enables writing of compressed Z data from cache to memory,</doc> + <use-enum ref="ENUM191" /> + </bitfield> + <bitfield name="ZB_CB_CLEAR" high="5" low="5"> + <doc>This bit is set when the Z buffer is used to help the CB in clearing a region. Part of the region is cleared by the color buffer and part will be cleared by the Z buffer. Since the Z buffer does not have any write masks in the cache, full micro-tiles need to be written. If a partial micro-tile is touched , then the un-touched part will be unknowns. The cache will operate in write-allocate mode and quads will be accumulated in the cache and then evicted to main memory. The color value is supplied through the ZB_DEPTHCLEARVALUE register.</doc> + <use-enum ref="ENUM192" /> + </bitfield> + <bitfield name="FORCE_COMPRESSED_STENCIL" high="6" low="6"> + <doc>Enabling this bit will force all the compressed stencil values to be</doc> + </bitfield> + </reg32> + <reg32 name="ZB_CNTL" access="rw" offset="0x4F00"> + <doc>Z Buffer Control</doc> + <bitfield name="STENCIL_ENABLE" high="0" low="0"> + <doc>Enables stenciling.</doc> + <use-enum ref="ENUM178" /> + </bitfield> + <bitfield name="Z_ENABLE" high="1" low="1"> + <doc>Enables Z functions.</doc> + <use-enum ref="ENUM178" /> + </bitfield> + <bitfield name="ZWRITEENABLE" high="2" low="2"> + <doc>Enables writing of the Z buffer.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="ZSIGNED_COMPARE" high="3" low="3"> + <doc>Enable signed Z buffer comparison , for W-buffering.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="STENCIL_FRONT_BACK" high="4" low="4"> + <doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK bit to one specifies that stencilfunc/stencilfail/stencilzpass/stencilzfail registers are used if the quad is generated from front faced primitive and stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf are used if the quad is generated from a back faced primitive. If the STENCIL_FRONT_BACK is not set, then stencilfunc/stencilfail/stencilzpass/stencilzfail registers determine the operation independent of the front/back face state of the quad.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + </reg32> + <reg32 name="ZB_FORMAT" access="rw" offset="0x4F10"> + <doc>Format of the Data in the Z buffer</doc> + <bitfield name="DEPTHFORMAT" high="3" low="0"> + <doc>Specifies the format of the Z buffer.</doc> + <use-enum ref="ENUM196" /> + </bitfield> + <bitfield name="INVERT" high="4" low="4"> + <doc></doc> + <value value="0" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 0`s</doc></value> + <value value="1" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 1`s.</doc></value> + </bitfield> + <bitfield name="PEQ8" high="5" low="5"> + <doc>This bit is unused</doc> + <value value="0" name="7_BYTES_PER_PLANE_EQUATION"><doc>7 bytes per plane equation, 1 byte for stencil</doc></value> + <value value="1" name="8_BYTES_PER_PLANE_EQUATION"><doc>8 bytes per plane equation, no bytes for stencil</doc></value> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_OFFSET" access="rw" offset="0x4F44"> + <doc>Hierarchical Z Memory Offset</doc> + <bitfield name="HIZ_OFFSET" high="16" low="2"> + <doc>DWORD offset into HiZ RAM. A DWORD can hold an 8-bit HiZ value for 4 blocks, so this offset is aligned on 4 4x4 blocks. In each pipe, the HIZ RAM DWORD address is generated from a pixel x[11:0] , y[11:0] as follows: HIZ_DWORD_ADDRESS[13:0] = HIZ_OFFSET[16:3] + Y[11:3] * HIZ_PITCH[13:5] + X[11:5].</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_RDINDEX" access="rw" offset="0x4F50"> + <doc>Hierarchical Z Read Index</doc> + <bitfield name="HIZ_RDINDEX" high="16" low="2"> + <doc>Read index into HiZ RAM. The index must start on a DWORD boundary. RDINDEX words much like WRINDEX. Every read from HIZ_DWORD will increment the register by 2.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_WRINDEX" access="rw" offset="0x4F48"> + <doc>Hierarchical Z Write Index</doc> + <bitfield name="HIZ_WRINDEX" high="16" low="2"> + <doc>Self-incrementing write index into the HiZ RAM. Starting write index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is written, this index will increment by two DWORD, this due to the fact that there are 2 pipes and the data is broadcasted to both pipes. HIZ_OFFSET and HIZ_PITCH are not used to compute read/write address to HIZ ram, when it is accessed through WRINDEX and DWORD</doc> + </bitfield> + </reg32> + <reg32 name="ZB_ZSTENCILCNTL" access="rw" offset="0x4F04"> + <doc>Z and Stencil Function Control</doc> + <bitfield name="ZFUNC" high="2" low="0"> + <doc>Specifies the Z function.</doc> + <use-enum ref="ENUM202" /> + </bitfield> + <bitfield name="STENCILFUNC" high="5" low="3"> + <doc>Specifies the stencil function.</doc> + <use-enum ref="ENUM203" /> + </bitfield> + <bitfield name="STENCILFAIL" high="8" low="6"> + <doc>Specifies the stencil value to be written if the stencil test fails.</doc> + <use-enum ref="ENUM204" /> + </bitfield> + <bitfield name="STENCILZPASS" high="11" low="9"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled).</doc> + </bitfield> + <bitfield name="STENCILZFAIL" high="14" low="12"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails.</doc> + </bitfield> + <bitfield name="STENCILFUNC_BF" high="17" low="15"> + <doc>Same encoding as STENCILFUNC. Specifies the stencil function for back faced quads , if STENCIL_FRONT_BACK = 1.</doc> + </bitfield> + <bitfield name="STENCILFAIL_BF" high="20" low="18"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test fails for back faced quads, if STENCIL_FRONT_BACK = 1</doc> + </bitfield> + <bitfield name="STENCILZPASS_BF" high="23" low="21"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled) for back faced quads, if STENCIL_FRONT_BACK = 1</doc> + </bitfield> + <bitfield name="STENCILZFAIL_BF" high="26" low="24"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails for back faced quads, if STENCIL_FRONT_BACK =1</doc> + </bitfield> + </reg32> +</group> + +<group name="r500_regs" prepend="R500_"> + <reg32 name="CP_CSQ2_STAT" access="r" offset="0x07FC"> + <doc>(RO) Command Stream Indirect Queue 2 Status</doc> + <bitfield name="CSQ_WPTR_INDIRECT" high="9" low="0"> + <doc>Current Write Pointer into the Indirect Queue. Default = 0.</doc> + </bitfield> + <bitfield name="CSQ_RPTR_INDIRECT2" high="19" low="10"> + <doc>Current Read Pointer into the Indirect Queue. Default = 0.</doc> + </bitfield> + <bitfield name="CSQ_WPTR_INDIRECT2" high="29" low="20"> + <doc>Current Write Pointer into the Indirect Queue. Default = 0.</doc> + </bitfield> + </reg32> + <reg32 name="CP_CSQ_ADDR" access="w" offset="0x07F0"> + <doc>(WO) Command Stream Queue Address</doc> + <bitfield name="CSQ_ADDR" high="11" low="2"> + <doc>Address into the Command Stream Queue which is to be read from. Used for debug, to read the contents of the Command Stream Queue.</doc> + </bitfield> + </reg32> + <reg32 name="CP_CSQ_APER_INDIRECT" access="rw" offset="0x1300"> + <doc>IB1 Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 name="CP_CSQ_APER_INDIRECT2" access="rw" offset="0x1200"> + <doc>IB2 Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 name="CP_CSQ_APER_PRIMARY" access="rw" offset="0x1000"> + <doc>Primary Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 name="CP_CSQ_AVAIL" access="rw" offset="0x07B8"> + <doc>Command Stream Queue Available Counts</doc> + <bitfield name="CSQ_CNT_PRIMARY" high="9" low="0"> + <doc>Count of available dwords in the queue for the Primary Stream. Read Only.</doc> + </bitfield> + <bitfield name="CSQ_CNT_INDIRECT" high="19" low="10"> + <doc>Count of available dwords in the queue for the Indirect Stream. Read Only.</doc> + </bitfield> + <bitfield name="CSQ_CNT_INDIRECT2" high="29" low="20"> + <doc>Count of available dwords in the queue for the Indirect Stream. Read Only.</doc> + </bitfield> + </reg32> + <reg32 name="CP_CSQ_CNTL" access="rw" offset="0x0740"> + <doc>Command Stream Queue Control</doc> + <bitfield name="CSQ_MODE" high="31" low="28"> + <doc>Command Stream Queue Mode. Controls whether each command stream is enabled, and whether it is in push mode (Programmed I/O), or pull mode (Bus-Master). Encodings are chosen to be compatible with Rage128. 0= Primary Disabled, Indirect Disabled. 1= Primary PIO, Indirect Disabled. 2= Primary BM, Indirect Disabled. 3,5,7= Primary PIO, Indirect BM. 4,6,8= Primary BM, Indirect BM. 9-14= Reserved. 15= Primary PIO, Indirect PIO Default = 0</doc> + <value value="0" name="PRIMARY_DISABLED"><doc>Primary Disabled, Indirect Disabled.</doc></value> + <value value="1" name="PRIMARY_PIO"><doc>Primary PIO, Indirect Disabled.</doc></value> + <value value="2" name="PRIMARY_BM"><doc>Primary BM, Indirect Disabled. 3,5,</doc></value> + <value value="7" name="PRIMARY_PIO"><doc>Primary PIO, Indirect BM. 4,6,</doc></value> + <value value="8" name="PRIMARY_BM"><doc>Primary BM, Indirect BM. 9-</doc></value> + <value value="15" name="PRIMARY_PIO"><doc>Primary PIO, Indirect PIO Default = 0</doc></value> + </bitfield> + </reg32> + <reg32 name="CP_CSQ_DATA" access="r" offset="0x07F4"> + <doc>(RO) Command Stream Queue Data</doc> + </reg32> + <reg32 name="CP_CSQ_MODE" access="rw" offset="0x0744"> + <doc>Alternate Command Stream Queue Control</doc> + <bitfield name="INDIRECT2_START" high="6" low="0"> + <doc>Start location of Indirect Queue #2 in the command cache. This value also sets the size in double octwords of the Indirect Queue #1 cache that will reside in locations INDIRECT1_START to (INDIRECT2_START - 1). The Indirect Queue #2 will reside in locations INDIRECT2_START to 0x5f. The minimum size of the Indirect Queues must be at least twice the MAX_FETCH size as programmed in the CP_RB_CNTL register.</doc> + </bitfield> + <bitfield name="INDIRECT1_START" high="14" low="8"> + <doc>Start location of Indirect Queue #1 in the command cache. This value is also the size in double octwords of the Primary Queue cache that will reside in locations 0 to (INDIRECT1_START - 1). The minimum size of the Primary Queue cache must be at least twice the MAX_FETCH size as programmed in the CP_RB_CNTL register.</doc> + </bitfield> + <bitfield name="CSQ_INDIRECT2_MODE" high="26" low="26"> + <doc></doc> + <use-enum ref="ENUM207" /> + </bitfield> + <bitfield name="CSQ_INDIRECT2_ENABLE" high="27" low="27"> + <doc>Enables Indirect Buffer #2. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc> + </bitfield> + <bitfield name="CSQ_INDIRECT1_MODE" high="28" low="28"> + <doc></doc> + <use-enum ref="ENUM207" /> + </bitfield> + <bitfield name="CSQ_INDIRECT1_ENABLE" high="29" low="29"> + <doc>Enables Indirect Buffer #1. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc> + </bitfield> + <bitfield name="CSQ_PRIMARY_MODE" high="30" low="30"> + <doc></doc> + <use-enum ref="ENUM207" /> + </bitfield> + <bitfield name="CSQ_PRIMARY_ENABLE" high="31" low="31"> + <doc>Enables Primary Buffer. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc> + </bitfield> + </reg32> + <reg32 name="CP_CSQ_STAT" access="r" offset="0x07F8"> + <doc>(RO) Command Stream Queue Status</doc> + <bitfield name="CSQ_RPTR_PRIMARY" high="9" low="0"> + <doc>Current Read Pointer into the Primary Queue. Default = 0.</doc> + </bitfield> + <bitfield name="CSQ_WPTR_PRIMARY" high="19" low="10"> + <doc>Current Write Pointer into the Primary Queue. Default = 0.</doc> + </bitfield> + <bitfield name="CSQ_RPTR_INDIRECT" high="29" low="20"> + <doc>Current Read Pointer into the Indirect Queue. Default = 0.</doc> + </bitfield> + </reg32> + <reg32 name="CP_GUI_COMMAND" access="rw" offset="0x0728"> + <doc>Command for PIO GUI DMAs</doc> + </reg32> + <reg32 name="CP_GUI_DST_ADDR" access="rw" offset="0x0724"> + <doc>Destination Address for PIO GUI DMAs</doc> + </reg32> + <reg32 name="CP_GUI_SRC_ADDR" access="rw" offset="0x0720"> + <doc>Source Address for PIO GUI DMAs</doc> + </reg32> + <reg32 name="CP_IB2_BASE" access="rw" offset="0x0730"> + <doc>Indirect Buffer 2 Base</doc> + <bitfield name="IB2_BASE" high="31" low="2"> + <doc>Indirect Buffer 2 Base. Address of the beginning of the indirect buffer. Only DWORD access is allowed to this register.</doc> + </bitfield> + </reg32> + <reg32 name="CP_IB2_BUFSZ" access="rw" offset="0x0734"> + <doc>Indirect Buffer 2 Size</doc> + <bitfield name="IB2_BUFSZ" high="22" low="0"> + <doc>Indirect Buffer 2 Size. This size is expressed in dwords. This field is an initiator to begin fetching commands from the Indirect Buffer. Only DWORD access is allowed to this register. Default = 0</doc> + </bitfield> + </reg32> + <reg32 name="CP_IB_BASE" access="rw" offset="0x0738"> + <doc>Indirect Buffer Base</doc> + <bitfield name="IB_BASE" high="31" low="2"> + <doc>Indirect Buffer Base. Address of the beginning of the indirect buffer. Only DWORD access is allowed to this register.</doc> + </bitfield> + </reg32> + <reg32 name="CP_IB_BUFSZ" access="rw" offset="0x073C"> + <doc>Indirect Buffer Size</doc> + <bitfield name="IB_BUFSZ" high="22" low="0"> + <doc>Indirect Buffer Size. This size is expressed in dwords. This field is an initiator to begin fetching commands from the Indirect Buffer. Only DWORD access is allowed to this register. Default = 0</doc> + </bitfield> + </reg32> + <reg32 name="CP_ME_CNTL" access="rw" offset="0x07D0"> + <doc>Micro Engine Control</doc> + <bitfield name="ME_STAT" high="15" low="0"> + <doc>Status of MicroEngine internal registers. This value depends on the current value of the ME_STATMUX field. Read Only.</doc> + </bitfield> + <bitfield name="ME_STATMUX" high="20" low="16"> + <doc>Selects which status is to be returned on the ME_STAT field.</doc> + </bitfield> + <bitfield name="ME_BUSY" high="29" low="29"> + <doc>Busy indicator for the MicroEngine. 0 = MicroEngine not busy. 1 = MicroEngine is active. Read Only.</doc> + </bitfield> + <bitfield name="ME_MODE" high="30" low="30"> + <doc>Run-Mode of MicroEngine. 0 = Single-Step Mode. 1 = Free-running Mode. Default = 1</doc> + </bitfield> + <bitfield name="ME_STEP" high="31" low="31"> + <doc>Step the MicroEngine by one instruction. Writing a `1` to this field causes the MicroEngine to step by one instruction, if and only if the ME_MODE bit is a `0`. Write Only.</doc> + </bitfield> + </reg32> + <reg32 name="CP_ME_RAM_ADDR" access="rw" offset="0x07D4"> + <doc>MicroEngine RAM Address</doc> + <bitfield name="ME_RAM_ADDR" high="7" low="0"> + <doc>MicroEngine RAM Address (Write Mode) Writing this</doc> + </bitfield> + </reg32> + <reg32 name="CP_ME_RAM_DATAH" access="rw" offset="0x07DC"> + <doc>MicroEngine RAM Data High</doc> + <bitfield name="ME_RAM_DATAH" high="7" low="0"> + <doc>MicroEngine RAM Data High Used to load the MicroEngine RAM.</doc> + </bitfield> + </reg32> + <reg32 name="CP_ME_RAM_DATAL" access="rw" offset="0x07E0"> + <doc>MicroEngine RAM Data Low</doc> + </reg32> + <reg32 name="CP_ME_RAM_RADDR" access="rw" offset="0x07D8"> + <doc>MicroEngine RAM Read Address</doc> + <bitfield name="ME_RAM_RADDR" high="7" low="0"> + <doc>MicroEngine RAM Address (Read Mode) Writing</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_BASE" access="rw" offset="0x0700"> + <doc>Ring Buffer Base</doc> + <bitfield name="RB_BASE" high="31" low="2"> + <doc>Ring Buffer Base. Address of the beginning of the ring buffer.</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_CNTL" access="rw" offset="0x0704"> + <doc>Ring Buffer Control</doc> + <bitfield name="RB_BUFSZ" high="5" low="0"> + <doc>Ring Buffer Size. This size is expressed in log2 of the actual size. Values 0 and 1 are clamped to an 8 DWORD ring buffer. A value of 2 to 22 will give a ring buffer: 2^(RB_BUFSZ+1). Values greater than 22 will clamp to 22. Default = 0</doc> + </bitfield> + <bitfield name="RB_BLKSZ" high="13" low="8"> + <doc>Ring Buffer Block Size. This defines the number of quadwords that the Command Processor will read between updates to the host`s copy of the Read Pointer. This size is expressed in log2 of the actual size (in 64-bit quadwords). For example, for a block of 1024 quadwords, you would program this field to 10(decimal). Default = 0</doc> + </bitfield> + <bitfield name="BUF_SWAP" high="17" low="16"> + <doc>Endian Swap Control for Ring Buffer and Indirect Buffer. Only affects the chip behavior if the buffer resides in system memory. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB Default = 0</doc> + </bitfield> + <bitfield name="MAX_FETCH" high="19" low="18"> + <doc>Maximum Fetch Size for any read request that the CP makes to memory. 0 = 1 double octword. (32 bytes) 1 = 2 double octwords. (64 bytes) 2 = 4 double octwords. (128 bytes) 3 = 8 double octwords. (256 bytes). Default =0</doc> + </bitfield> + <bitfield name="RB_NO_UPDATE" high="27" low="27"> + <doc>Ring Buffer No Write to Read Pointer 0= Write to Host`s copy of Read Pointer in system memory. 1= Do not write to Host`s copy of Read pointer. The purpose of this control bit is to have a fall-back position if the bus- mastered write to system memory doesn`t work, in which case the driver will have to read the Graphics Controller`s copy of the Read Pointer directly, with some performance penalty. Default = 0</doc> + <value value="0" name="WRITE_TO_HOST"><doc>Write to Host`s copy of Read Pointer in system memory.</doc></value> + <value value="1" name="DO_NOT_WRITE_TO_HOST"><doc>Do not write to Host`s copy of Read pointer. The purpose of this control bit is to have a fall-back position if the bus- mastered write to system memory doesn`t work, in which case the driver will have to read the Graphics Controller`s copy of the Read Pointer directly, with some performance penalty. Default = 0</doc></value> + </bitfield> + <bitfield name="RB_RPTR_WR_ENA" high="31" low="31"> + <doc>Ring Buffer Read Pointer Write Transfer Enable. When set the contents of the CP_RB_RPTR_WR register is transferred to the active read pointer (CP_RB_RPTR) whenever the CP_RB_WPTR register is written. Default =0</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_RPTR" access="rw" offset="0x0710"> + <doc>Ring Buffer Read Pointer Address (RO)</doc> + <bitfield name="RB_RPTR" high="22" low="0"> + <doc>Ring Buffer Read Pointer. This is an index (in dwords) of the current element being read from the ring buffer.</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_RPTR_ADDR" access="rw" offset="0x070C"> + <doc>Ring Buffer Read Pointer Address</doc> + <bitfield name="RB_RPTR_SWAP" high="1" low="0"> + <doc>Swap control of the reported read pointer address. See CP_RB_CNTL.BUF_SWAP for the encoding.</doc> + </bitfield> + <bitfield name="RB_RPTR_ADDR" high="31" low="2"> + <doc>Ring Buffer Read Pointer Address. Address of the Host`s copy of the Read Pointer. CP_RB_RPTR (RO) Ring Buffer Read Pointer</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_RPTR_WR" access="rw" offset="0x071C"> + <doc>Writable Ring Buffer Read Pointer Address</doc> + <bitfield name="RB_RPTR_WR" high="22" low="0"> + <doc>Writable Ring Buffer Read Pointer. Writable for updating the RB_RPTR after an ACPI.</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_WPTR" access="rw" offset="0x0714"> + <doc>(RO) Ring Buffer Write Pointer</doc> + <bitfield name="RB_WPTR" high="22" low="0"> + <doc>Ring Buffer Write Pointer. This is an index (in dwords) of the last known element to be written to the ring buffer (by the host).</doc> + </bitfield> + </reg32> + <reg32 name="CP_RB_WPTR_DELAY" access="rw" offset="0x0718"> + <doc>Ring Buffer Write Pointer Delay</doc> + <bitfield name="PRE_WRITE_TIMER" high="27" low="0"> + <doc>Pre-Write Timer. The number of clocks that a write to the CP_RB_WPTR register will be delayed until actually taking effect. Default = 0</doc> + </bitfield> + <bitfield name="PRE_WRITE_LIMIT" high="31" low="28"> + <doc>Pre-Write Limit. The number of times that the CP_RB_WPTR register can be written (while the PRE_WRITE_TIMER has not expired) before the CP_RB_WPTR register is forced to be updated with the most recently written value. Default = 0</doc> + </bitfield> + </reg32> + <reg32 name="CP_RESYNC_ADDR" access="rw" offset="0x0778"> + <doc>Raster Engine Sync Address (WO)</doc> + <bitfield name="RESYNC_ADDR" high="2" low="0"> + <doc>Scratch Register Offset Address.</doc> + </bitfield> + </reg32> + <reg32 name="CP_RESYNC_DATA" access="rw" offset="0x077C"> + <doc>Raster Engine Sync Data (WO)</doc> + </reg32> + <reg32 name="CP_STAT" access="r" offset="0x07C0"> + <doc>(RO) Busy Status Signals</doc> + <bitfield name="MRU_BUSY" high="0" low="0"> + <doc>Memory Read Unit Busy.</doc> + </bitfield> + <bitfield name="MWU_BUSY" high="1" low="1"> + <doc>Memory Write Unit Busy.</doc> + </bitfield> + <bitfield name="RSIU_BUSY" high="2" low="2"> + <doc>Register Backbone Input Interface Busy.</doc> + </bitfield> + <bitfield name="RCIU_BUSY" high="3" low="3"> + <doc>RBBM Output Interface Busy.</doc> + </bitfield> + <bitfield name="CSF_PRIMARY_BUSY" high="9" low="9"> + <doc>Primary Command Stream Fetcher Busy.</doc> + </bitfield> + <bitfield name="CSF_INDIRECT_BUSY" high="10" low="10"> + <doc>Indirect #1 Command Stream Fetcher Busy.</doc> + </bitfield> + <bitfield name="CSQ_PRIMARY_BUSY" high="11" low="11"> + <doc>Data in Command Queue for Primary Stream.</doc> + </bitfield> + <bitfield name="CSQ_INDIRECT_BUSY" high="12" low="12"> + <doc>Data in Command Queue for Indirect #1 Stream.</doc> + </bitfield> + <bitfield name="CSI_BUSY" high="13" low="13"> + <doc>Command Stream Interpreter Busy.</doc> + </bitfield> + <bitfield name="CSF_INDIRECT2_BUSY" high="14" low="14"> + <doc>Indirect #2 Command Stream Fetcher Busy.</doc> + </bitfield> + <bitfield name="CSQ_INDIRECT2_BUSY" high="15" low="15"> + <doc>Data in Command Queue for Indirect #2 Stream.</doc> + </bitfield> + <bitfield name="GUIDMA_BUSY" high="28" low="28"> + <doc>GUI DMA Engine Busy.</doc> + </bitfield> + <bitfield name="VIDDMA_BUSY" high="29" low="29"> + <doc>VID DMA Engine Busy.</doc> + </bitfield> + <bitfield name="CMDSTRM_BUSY" high="30" low="30"> + <doc>Command Stream Busy.</doc> + </bitfield> + <bitfield name="CP_BUSY" high="31" low="31"> + <doc>CP Busy.</doc> + </bitfield> + </reg32> + <reg32 name="CP_VID_COMMAND" access="rw" offset="0x07CC"> + <doc>Command for PIO VID DMAs</doc> + </reg32> + <reg32 name="CP_VID_DST_ADDR" access="rw" offset="0x07C8"> + <doc>Destination Address for PIO VID DMAs</doc> + </reg32> + <reg32 name="CP_VID_SRC_ADDR" access="rw" offset="0x07C4"> + <doc>Source Address for PIO VID DMAs</doc> + </reg32> + <reg32 name="CP_VP_ADDR_CNTL" access="rw" offset="0x07E8"> + <doc>Virtual vs Physical Address Control - Selects whether the address corresponds to a physical or virtual address in memory.</doc> + <bitfield name="SCRATCH_ALT_VP_WR" high="0" low="0"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="SCRATCH_VP_WR" high="1" low="1"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="RPTR_VP_UPDATE" high="2" low="2"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="VIDDMA_VP_WR" high="3" low="3"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="VIDDMA_VP_RD" high="4" low="4"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="GUIDMA_VP_WR" high="5" low="5"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="GUIDMA_VP_RD" high="6" low="6"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="INDR2_VP_FETCH" high="7" low="7"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="INDR1_VP_FETCH" high="8" low="8"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + <bitfield name="RING_VP_FETCH" high="9" low="9"> + <doc></doc> + <use-enum ref="ENUM209" /> + </bitfield> + </reg32> + <reg32 name="RB3D_AARESOLVE_CTL" access="rw" offset="0x4E88"> + <doc>Resolve Buffer Control. Unpipelined</doc> + <bitfield name="AARESOLVE_MODE" high="0" low="0"> + <doc>Specifies if the color buffer is in resolve mode. The cache must be empty before changing this register.</doc> + <use-enum ref="ENUM0" /> + </bitfield> + <bitfield name="AARESOLVE_GAMMA" high="1" low="1"> + <doc>Specifies the gamma and degamma to be applied to the samples before and after filtering, respectively.</doc> + <use-enum ref="ENUM1" /> + </bitfield> + <bitfield name="AARESOLVE_ALPHA" high="2" low="2"> + <doc>Controls whether alpha is averaged in the resolve. 0 => the resolved alpha value is selected from the sample 0 value. 1=> the resolved alpha value is a filtered (average) result of of the samples.</doc> + <value value="1" name=""><doc>> the resolved alpha value is a filtered (average) result of of the samples. POSSIBLE VALUES:</doc></value> + <value value="0" name="RESOLVED_ALPHA_VALUE_IS_TAKEN_FROM_SAMPLE_0"><doc>Resolved alpha value is taken from sample 0.</doc></value> + <value value="1" name="RESOLVED_ALPHA_VALUE_IS_THE_AVERAGE_OF_THE_SAMPLES"><doc>Resolved alpha value is the average of the samples. The average is not gamma corrected.</doc></value> + </bitfield> + </reg32> + <reg32 name="RB3D_BLENDCNTL" access="rw" offset="0x4E04"> + <doc>Alpha Blend Control for Color Channels. Pipelined through the blender.</doc> + <bitfield name="ALPHA_BLEND_ENABLE" high="0" low="0"> + <doc>Allow alpha blending with the destination.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="SEPARATE_ALPHA_ENABLE" high="1" low="1"> + <doc>Enables use of RB3D_ABLENDCNTL</doc> + <use-enum ref="ENUM6" /> + </bitfield> + <bitfield name="READ_ENABLE" high="2" low="2"> + <doc>When blending is enabled, this enables memory reads. Memory reads will still occur when this is disabled if they are for reasons not related to blending.</doc> + <use-enum ref="ENUM7" /> + </bitfield> + <bitfield name="DISCARD_SRC_PIXELS" high="5" low="3"> + <doc>Discard pixels when blending is enabled based on the src color.</doc> + <value value="0" name="DISABLE"><doc>Disable</doc></value> + <value value="1" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="2" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="3" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="4" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> + <value value="5" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> + <value value="6" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> + </bitfield> + <bitfield name="COMB_FCN" high="14" low="12"> + <doc>Combine Function , Allows modification of how the SRCBLEND and DESTBLEND are combined.</doc> + <use-enum ref="ENUM2" /> + </bitfield> + <bitfield name="SRCBLEND" high="21" low="16"> + <doc>Source Blend Function , Alpha blending function (SRC).</doc> + <use-enum ref="ENUM3" /> + </bitfield> + <bitfield name="DESTBLEND" high="29" low="24"> + <doc>Destination Blend Function , Alpha blending function (DST).</doc> + <use-enum ref="ENUM4" /> + </bitfield> + <bitfield name="SRC_ALPHA_0_NO_READ" high="30" low="30"> + <doc>Enables source alpha zero performance optimization to skip reads.</doc> + <value value="0" name="DISABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS"><doc>Disable source alpha zero performance optimization to skip reads</doc></value> + <value value="1" name="ENABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS"><doc>Enable source alpha zero performance optimization to skip reads</doc></value> + </bitfield> + <bitfield name="SRC_ALPHA_1_NO_READ" high="31" low="31"> + <doc>Enables source alpha one performance optimization to skip reads.</doc> + <value value="0" name="DISABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS"><doc>Disable source alpha one performance optimization to skip reads</doc></value> + <value value="1" name="ENABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS"><doc>Enable source alpha one performance optimization to skip reads</doc></value> + </bitfield> + </reg32> + <reg32 name="RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD" access="rw" offset="0x4EA4"> + <doc>Discard src pixels greater than or equal to threshold.</doc> + <bitfield name="BLUE" high="7" low="0"> + <doc>Blue</doc> + </bitfield> + <bitfield name="GREEN" high="15" low="8"> + <doc>Green</doc> + </bitfield> + <bitfield name="RED" high="23" low="16"> + <doc>Red</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="24"> + <doc>Alpha</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD" access="rw" offset="0x4EA0"> + <doc>Discard src pixels less than or equal to threshold.</doc> + <bitfield name="BLUE" high="7" low="0"> + <doc>Blue</doc> + </bitfield> + <bitfield name="GREEN" high="15" low="8"> + <doc>Green</doc> + </bitfield> + <bitfield name="RED" high="23" low="16"> + <doc>Red</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="24"> + <doc>Alpha</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_CCTL" access="rw" offset="0x4E00"> + <doc>Unpipelined.</doc> + <bitfield name="NUM_MULTIWRITES" high="6" low="5"> + <doc>A quad is replicated and written to this many buffers.</doc> + <use-enum ref="ENUM9" /> + </bitfield> + <bitfield name="CLRCMP_FLIPE_ENABLE" high="7" low="7"> + <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. This is used to ensure 3D data does not get chromakeyed away by logic in the backend.</doc> + <use-enum ref="ENUM10" /> + </bitfield> + <bitfield name="AA_COMPRESSION_ENABLE" high="9" low="9"> + <doc>Enables AA color compression. Cmask must also be enabled when aa compression is enabled. The cache must be empty before this is changed.</doc> + <use-enum ref="ENUM11" /> + </bitfield> + <bitfield name="CMASK_ENABLE" high="10" low="10"> + <doc>Enables use of the cmask ram. The cache must be empty before this is changed.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="Reserved" high="11" low="11"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE" high="12" low="12"> + <doc>Enables indepedent color channel masks for the MRTs. Disabling this feature will cause all the MRTs to use color channel mask 0.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="WRITE_COMPRESSION_DISABLE" high="13" low="13"> + <doc>Disables write compression.</doc> + <value value="0" name="ENABLE_WRITE_COMPRESSION"><doc>Enable write compression</doc></value> + <value value="1" name="DISABLE_WRITE_COMPRESSION"><doc>Disable write compression</doc></value> + </bitfield> + <bitfield name="INDEPENDENT_COLORFORMAT_ENABLE" high="14" low="14"> + <doc>Enables independent color format for the MRTs. Disabling this feature will cause all the MRTs to use color format 0.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + </reg32> + <stripe offset="0x4E38" stride="0x0004" length="4"> + <reg32 name="RB3D_COLORPITCH" access="rw" offset="0x0000"> + <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> + <bitfield name="COLORPITCH" high="13" low="1"> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + </bitfield> + <bitfield name="COLORTILE" high="16" low="16"> + <doc>Denotes whether the 3D destination is in macrotiled format.</doc> + <use-enum ref="ENUM12" /> + </bitfield> + <bitfield name="COLORMICROTILE" high="18" low="17"> + <doc>Denotes whether the 3D destination is in microtiled format.</doc> + <use-enum ref="ENUM13" /> + </bitfield> + <bitfield name="COLORENDIAN" high="20" low="19"> + <doc>Specifies endian control for the color buffer.</doc> + <use-enum ref="ENUM14" /> + </bitfield> + <bitfield name="COLORFORMAT" high="24" low="21"> + <doc>3D destination color format.</doc> + <value value="0" name="ARGB10101010"><doc>ARGB10101010</doc></value> + <value value="1" name="UV1010"><doc>UV1010</doc></value> + <value value="2" name="CI8"><doc>CI8 (2D ONLY)</doc></value> + <value value="3" name="ARGB1555"><doc>ARGB1555</doc></value> + <value value="4" name="RGB565"><doc>RGB565</doc></value> + <value value="5" name="ARGB2101010"><doc>ARGB2101010</doc></value> + <value value="6" name="ARGB8888"><doc>ARGB8888</doc></value> + <value value="7" name="ARGB32323232"><doc>ARGB32323232</doc></value> + <value value="9" name="I8"><doc>I8</doc></value> + <value value="10" name="ARGB16161616"><doc>ARGB16161616</doc></value> + <value value="11" name="YUV422_PACKED"><doc>YUV422 packed (VYUY)</doc></value> + <value value="12" name="YUV422_PACKED"><doc>YUV422 packed (YVYU)</doc></value> + <value value="13" name="UV88"><doc>UV88</doc></value> + <value value="14" name="I10"><doc>I10</doc></value> + <value value="15" name="ARGB4444"><doc>ARGB4444</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="RB3D_COLOR_CHANNEL_MASK" access="rw" offset="0x4E0C"> + <doc>3D Color Channel Mask. If all the channels used in the current color format are disabled, then the cb will discard all the incoming quads. Pipelined through the blender.</doc> + <bitfield name="BLUE_MASK" high="0" low="0"> + <doc>mask bit for the blue channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="GREEN_MASK" high="1" low="1"> + <doc>mask bit for the green channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="RED_MASK" high="2" low="2"> + <doc>mask bit for the red channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="ALPHA_MASK" high="3" low="3"> + <doc>mask bit for the alpha channel</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="BLUE_MASK1" high="4" low="4"> + <doc>mask bit for the blue channel of MRT 1</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="GREEN_MASK1" high="5" low="5"> + <doc>mask bit for the green channel of MRT 1</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="RED_MASK1" high="6" low="6"> + <doc>mask bit for the red channel of MRT 1</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="ALPHA_MASK1" high="7" low="7"> + <doc>mask bit for the alpha channel of MRT 1</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="BLUE_MASK2" high="8" low="8"> + <doc>mask bit for the blue channel of MRT 2</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="GREEN_MASK2" high="9" low="9"> + <doc>mask bit for the green channel of MRT 2</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="RED_MASK2" high="10" low="10"> + <doc>mask bit for the red channel of MRT 2</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="ALPHA_MASK2" high="11" low="11"> + <doc>mask bit for the alpha channel of MRT 2</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="BLUE_MASK3" high="12" low="12"> + <doc>mask bit for the blue channel of MRT 3</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="GREEN_MASK3" high="13" low="13"> + <doc>mask bit for the green channel of MRT 3</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="RED_MASK3" high="14" low="14"> + <doc>mask bit for the red channel of MRT 3</doc> + <use-enum ref="ENUM16" /> + </bitfield> + <bitfield name="ALPHA_MASK3" high="15" low="15"> + <doc>mask bit for the alpha channel of MRT 3</doc> + <use-enum ref="ENUM16" /> + </bitfield> + </reg32> + <reg32 name="RB3D_COLOR_CLEAR_VALUE" access="rw" offset="0x4E14"> + <doc>Clear color that is used when the color mask is set to 00. Unpipelined. Program this register with a 32-bit value in ARGB8888 or ARGB2101010 formats, ignoring the fields.</doc> + <bitfield name="BLUE" high="7" low="0"> + <doc>blue clear color</doc> + </bitfield> + <bitfield name="GREEN" high="15" low="8"> + <doc>green clear color</doc> + </bitfield> + <bitfield name="RED" high="23" low="16"> + <doc>red clear color</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="24"> + <doc>alpha clear color</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_COLOR_CLEAR_VALUE_AR" access="rw" offset="0x46C0"> + <doc>Alpha and red clear color values that are used when the color mask is set to 00 in FP16 per component mode. Unpipelined.</doc> + <bitfield name="RED" high="15" low="0"> + <doc>red clear color</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="16"> + <doc>alpha clear color</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_COLOR_CLEAR_VALUE_GB" access="rw" offset="0x46C4"> + <doc>Green and blue clear color values that are used when the color mask is set to 00 in FP16 per component mode. Unpipelined.</doc> + <bitfield name="BLUE" high="15" low="0"> + <doc>blue clear color</doc> + </bitfield> + <bitfield name="GREEN" high="31" low="16"> + <doc>green clear color</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_CONSTANT_COLOR" access="rw" offset="0x4E10"> + <doc>Constant color used by the blender. Pipelined through the blender.</doc> + <bitfield name="BLUE" high="7" low="0"> + <doc>blue constant color (For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE instead)</doc> + </bitfield> + <bitfield name="GREEN" high="15" low="8"> + <doc>green constant color (For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__GREEN instead)</doc> + </bitfield> + <bitfield name="RED" high="23" low="16"> + <doc>red constant color (For R520, this field is ignored, use RB3D_CONSTANT_COLOR_AR__RED instead)</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="24"> + <doc>alpha constant color (For R520, this field is ignored, use RB3D_CONSTANT_COLOR_AR__ALPHA instead)</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_CONSTANT_COLOR_AR" access="rw" offset="0x4EF8"> + <doc>Constant color used by the blender. Pipelined through the blender.</doc> + <bitfield name="RED" high="15" low="0"> + <doc>red constant color in 0.10 fixed or FP16 format</doc> + </bitfield> + <bitfield name="ALPHA" high="31" low="16"> + <doc>alpha constant color in 0.10 fixed or FP16 format</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_CONSTANT_COLOR_GB" access="rw" offset="0x4EFC"> + <doc>Constant color used by the blender. Pipelined through the blender.</doc> + <bitfield name="BLUE" high="15" low="0"> + <doc>blue constant color in 0.10 fixed or FP16 format</doc> + </bitfield> + <bitfield name="GREEN" high="31" low="16"> + <doc>green constant color in 0.10 fixed or FP16 format</doc> + </bitfield> + </reg32> + <reg32 name="RB3D_FIFO_SIZE" access="rw" offset="0x4EF4"> + <doc>Sets the fifo sizes</doc> + <bitfield name="OP_FIFO_SIZE" high="1" low="0"> + <doc>Determines the size of the op fifo</doc> + <use-enum ref="ENUM216" /> + </bitfield> + </reg32> + <reg32 name="FG_ALPHA_FUNC" access="rw" offset="0x4BD4"> + <doc>Alpha Function</doc> + <bitfield name="AF_VAL" high="7" low="0"> + <doc>Specifies the 8-bit alpha compare value when AF_EN_8BIT is enabled</doc> + </bitfield> + <bitfield name="AF_FUNC" high="10" low="8"> + <doc>Specifies the alpha compare function.</doc> + <use-enum ref="ENUM22" /> + </bitfield> + <bitfield name="AF_EN" high="11" low="11"> + <doc>Enables/Disables alpha compare function.</doc> + <use-enum ref="ENUM23" /> + </bitfield> + <bitfield name="AF_EN_8BIT" high="12" low="12"> + <doc>Enable 8-bit alpha compare function.</doc> + <value value="0" name="DEFAULT_10"><doc>Default 10-bit alpha compare.</doc></value> + <value value="1" name="ENABLE_8"><doc>Enable 8-bit alpha compare.</doc></value> + </bitfield> + <bitfield name="AM_EN" high="16" low="16"> + <doc>Enables/Disables alpha-to-mask function.</doc> + <use-enum ref="ENUM24" /> + </bitfield> + <bitfield name="AM_CFG" high="17" low="17"> + <doc>Specfies number of sub-pixel samples for alpha-to-mask function.</doc> + <use-enum ref="ENUM25" /> + </bitfield> + <bitfield name="DITH_EN" high="20" low="20"> + <doc>Enables/Disables RGB Dithering (Not supported in R520)</doc> + <use-enum ref="ENUM26" /> + </bitfield> + <bitfield name="ALP_OFF_EN" high="24" low="24"> + <doc>Alpha offset enable/disable (Not supported in R520)</doc> + <value value="0" name="DISABLES_ALPHA_OFFSET_OF_2"><doc>Disables alpha offset of 2 (default r300 & rv350 behavior)</doc></value> + <value value="1" name="ENABLES_OFFSET_OF_2_ON_ALPHA_COMING_IN_FROM_THE_US"><doc>Enables offset of 2 on alpha coming in from the US</doc></value> + </bitfield> + <bitfield name="DISCARD_ZERO_MASK_QUAD" high="25" low="25"> + <doc>Enable/Disable discard zero mask coverage quad to ZB</doc> + <value value="0" name="NO_DISCARD_OF_ZERO_COVERAGE_MASK_QUADS"><doc>No discard of zero coverage mask quads</doc></value> + <value value="1" name="DISCARD_ZERO_COVERAGE_MASK_QUADS"><doc>Discard zero coverage mask quads</doc></value> + </bitfield> + <bitfield name="FP16_ENABLE" high="28" low="28"> + <doc>Enables/Disables FP16 alpha function</doc> + <value value="0" name="DEFAULT_10"><doc>Default 10-bit alpha compare and alpha-to-mask function</doc></value> + <value value="1" name="ENABLE_FP16_ALPHA_COMPARE_AND_ALPHA"><doc>Enable FP16 alpha compare and alpha-to-mask function</doc></value> + </bitfield> + </reg32> + <reg32 name="FG_ALPHA_VALUE" access="rw" offset="0x4BE0"> + <doc>Alpha Compare Value</doc> + <bitfield name="AF_VAL" high="15" low="0"> + <doc>Specifies the alpha compare value, 0.10 fixed or FP16 format</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_B" access="rw" offset="0x4BD0"> + <doc>Blue Component of Fog Color</doc> + <bitfield name="BLUE" high="9" low="0"> + <doc>Blue component of fog color; (0.10) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_G" access="rw" offset="0x4BCC"> + <doc>Green Component of Fog Color</doc> + <bitfield name="GREEN" high="9" low="0"> + <doc>Green component of fog color; (0.10) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_COLOR_R" access="rw" offset="0x4BC8"> + <doc>Red Component of Fog Color</doc> + <bitfield name="RED" high="9" low="0"> + <doc>Red component of fog color; (0.10) fixed format.</doc> + </bitfield> + </reg32> + <reg32 name="FG_FOG_FACTOR" access="rw" offset="0x4BC4"> + <doc>Constant Factor for Fog Blending</doc> + <bitfield name="FACTOR" high="9" low="0"> + <doc>Constant fog factor; fixed (0.10) format.</doc> + </bitfield> + </reg32> + <reg32 name="GA_COLOR_CONTROL_PS3" access="rw" offset="0x4258"> + <doc>Specifies color properties and mappings of textures.</doc> + <bitfield name="TEX0_SHADING_PS3" high="1" low="0"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX1_SHADING_PS3" high="3" low="2"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX2_SHADING_PS3" high="5" low="4"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX3_SHADING_PS3" high="7" low="6"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX4_SHADING_PS3" high="9" low="8"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX5_SHADING_PS3" high="11" low="10"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX6_SHADING_PS3" high="13" low="12"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX7_SHADING_PS3" high="15" low="14"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX8_SHADING_PS3" high="17" low="16"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX9_SHADING_PS3" high="19" low="18"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for each texture.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="TEX10_SHADING_PS3" high="21" low="20"> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for tex10 components.</doc> + <use-enum ref="ENUM30" /> + </bitfield> + <bitfield name="COLOR0_TEX_OVERRIDE" high="25" low="22"> + <doc>Specifies if each color should come from a texture and which one.</doc> + <use-enum ref="ENUM221" /> + </bitfield> + <bitfield name="COLOR1_TEX_OVERRIDE" high="29" low="26"> + <doc>Specifies if each color should come from a texture and which one.</doc> + <use-enum ref="ENUM221" /> + </bitfield> + </reg32> + <reg32 name="GA_ENHANCE" access="rw" offset="0x4274"> + <doc>GA Enhancement Register</doc> + <bitfield name="DEADLOCK_CNTL" high="0" low="0"> + <doc>TCL/GA Deadlock control.</doc> + <use-enum ref="ENUM32" /> + </bitfield> + <bitfield name="FASTSYNC_CNTL" high="1" low="1"> + <doc>Enables Fast register/primitive switching</doc> + <use-enum ref="ENUM33" /> + </bitfield> + <bitfield name="REG_READWRITE" high="2" low="2"> + <doc>R520+: When set, GA supports simultaneous register reads & writes</doc> + <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> + <value value="1" name="ENABLES_GA_SUPPORT_OF_SIMULTANEOUS_REGISTER_READS_AND_WRITES"><doc>Enables GA support of simultaneous register reads and writes.</doc></value> + </bitfield> + <bitfield name="REG_NOSTALL" high="3" low="3"> + <doc></doc> + <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> + <value value="1" name="ENABLES_GA_SUPPORT_OF_NO"><doc>Enables GA support of no-stall reads for register read back.</doc></value> + </bitfield> + </reg32> + <reg32 name="GA_FIFO_CNTL" access="rw" offset="0x4270"> + <doc>GA Input fifo high water marks</doc> + <bitfield name="VERTEX_FIFO" high="2" low="0"> + <doc>Number of words remaining in input vertex fifo before asserting nearly full</doc> + </bitfield> + <bitfield name="INDEX_FIFO" high="5" low="3"> + <doc>Number of words remaining in input primitive fifo before asserting nearly full</doc> + </bitfield> + <bitfield name="REG_FIFO" high="13" low="6"> + <doc>Number of words remaining in input register fifo before asserting nearly full</doc> + </bitfield> + </reg32> + <reg32 name="GA_FILL_A" access="rw" offset="0x422C"> + <doc>Alpha fill color</doc> + </reg32> + <reg32 name="GA_FILL_B" access="rw" offset="0x4228"> + <doc>Blue fill color</doc> + </reg32> + <reg32 name="GA_FILL_G" access="rw" offset="0x4224"> + <doc>Green fill color</doc> + </reg32> + <reg32 name="GA_FILL_R" access="rw" offset="0x4220"> + <doc>Red fill color</doc> + </reg32> + <reg32 name="GA_IDLE" access="rw" offset="0x425C"> + <doc>Returns idle status of various G3D block, captured when GA_IDLE written or when hard or soft reset asserted.</doc> + <bitfield name="PIPE3_Z_IDLE" high="0" low="0"> + <doc>Idle status of physical pipe 3 Z unit</doc> + </bitfield> + <bitfield name="PIPE2_Z_IDLE" high="1" low="1"> + <doc>Idle status of physical pipe 2 Z unit</doc> + </bitfield> + <bitfield name="PIPE3_CB_IDLE" high="2" low="2"> + <doc>Idle status of physical pipe 3 CB unit</doc> + </bitfield> + <bitfield name="PIPE2_CB_IDLE" high="3" low="3"> + <doc>Idle status of physical pipe 2 CB unit</doc> + </bitfield> + <bitfield name="PIPE3_FG_IDLE" high="4" low="4"> + <doc>Idle status of physical pipe 3 FG unit</doc> + </bitfield> + <bitfield name="PIPE2_FG_IDLE" high="5" low="5"> + <doc>Idle status of physical pipe 2 FG unit</doc> + </bitfield> + <bitfield name="PIPE3_US_IDLE" high="6" low="6"> + <doc>Idle status of physical pipe 3 US unit</doc> + </bitfield> + <bitfield name="PIPE2_US_IDLE" high="7" low="7"> + <doc>Idle status of physical pipe 2 US unit</doc> + </bitfield> + <bitfield name="PIPE3_SC_IDLE" high="8" low="8"> + <doc>Idle status of physical pipe 3 SC unit</doc> + </bitfield> + <bitfield name="PIPE2_SC_IDLE" high="9" low="9"> + <doc>Idle status of physical pipe 2 SC unit</doc> + </bitfield> + <bitfield name="PIPE3_RS_IDLE" high="10" low="10"> + <doc>Idle status of physical pipe 3 RS unit</doc> + </bitfield> + <bitfield name="PIPE2_RS_IDLE" high="11" low="11"> + <doc>Idle status of physical pipe 2 RS unit</doc> + </bitfield> + <bitfield name="PIPE1_Z_IDLE" high="12" low="12"> + <doc>Idle status of physical pipe 1 Z unit</doc> + </bitfield> + <bitfield name="PIPE0_Z_IDLE" high="13" low="13"> + <doc>Idle status of physical pipe 0 Z unit</doc> + </bitfield> + <bitfield name="PIPE1_CB_IDLE" high="14" low="14"> + <doc>Idle status of physical pipe 1 CB unit</doc> + </bitfield> + <bitfield name="PIPE0_CB_IDLE" high="15" low="15"> + <doc>Idle status of physical pipe 0 CB unit</doc> + </bitfield> + <bitfield name="PIPE1_FG_IDLE" high="16" low="16"> + <doc>Idle status of physical pipe 1 FG unit</doc> + </bitfield> + <bitfield name="PIPE0_FG_IDLE" high="17" low="17"> + <doc>Idle status of physical pipe 0 FG unit</doc> + </bitfield> + <bitfield name="PIPE1_US_IDLE" high="18" low="18"> + <doc>Idle status of physical pipe 1 US unit</doc> + </bitfield> + <bitfield name="PIPE0_US_IDLE" high="19" low="19"> + <doc>Idle status of physical pipe 0 US unit</doc> + </bitfield> + <bitfield name="PIPE1_SC_IDLE" high="20" low="20"> + <doc>Idle status of physical pipe 1 SC unit</doc> + </bitfield> + <bitfield name="PIPE0_SC_IDLE" high="21" low="21"> + <doc>Idle status of physical pipe 0 SC unit</doc> + </bitfield> + <bitfield name="PIPE1_RS_IDLE" high="22" low="22"> + <doc>Idle status of physical pipe 1 RS unit</doc> + </bitfield> + <bitfield name="PIPE0_RS_IDLE" high="23" low="23"> + <doc>Idle status of physical pipe 0 RS unit</doc> + </bitfield> + <bitfield name="SU_IDLE" high="24" low="24"> + <doc>Idle status of SU unit</doc> + </bitfield> + <bitfield name="GA_IDLE" high="25" low="25"> + <doc>Idle status of GA unit</doc> + </bitfield> + <bitfield name="GA_UNIT2_IDLE" high="26" low="26"> + <doc>Idle status of GA unit2</doc> + </bitfield> + </reg32> + <reg32 name="GA_LINE_CNTL" access="rw" offset="0x4234"> + <doc>Line control</doc> + <bitfield name="WIDTH" high="15" low="0"> + <doc>1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b subprecision); (16.0) fixed format.</doc> + </bitfield> + <bitfield name="END_TYPE" high="17" low="16"> + <doc>Specifies how ends of lines should be drawn.</doc> + <use-enum ref="ENUM34" /> + </bitfield> + <bitfield name="SORT" high="18" low="18"> + <doc>R520+: When enabled, all lines are sorted so that V0 is vertex with smallest X, or if X equal, smallest Y.</doc> + <value value="0" name="NO_SORTING"><doc>No sorting (default)</doc></value> + <value value="1" name="SORT_ON_MINX_THAN_MINY"><doc>Sort on minX than MinY</doc></value> + </bitfield> + </reg32> + <reg32 name="GA_OFFSET" access="rw" offset="0x4290"> + <doc>Specifies x & y offsets for vertex data after conversion to FP.</doc> + <bitfield name="X_OFFSET" high="15" low="0"> + <doc>Specifies X offset in S15 format (subpixels -- 1/12 or 1/16, even in 8b subprecision).</doc> + </bitfield> + <bitfield name="Y_OFFSET" high="31" low="16"> + <doc>Specifies Y offset in S15 format (subpixels -- 1/12 or 1/16, even in 8b subprecision).</doc> + </bitfield> + </reg32> + <reg32 name="GA_POINT_SIZE" access="rw" offset="0x421C"> + <doc>Dimensions for Points</doc> + <bitfield name="HEIGHT" high="15" low="0"> + <doc>1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in 8b precision).</doc> + </bitfield> + <bitfield name="WIDTH" high="31" low="16"> + <doc>1/2 Width of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in 8b precision)</doc> + </bitfield> + </reg32> + <reg32 name="GA_ROUND_MODE" access="rw" offset="0x428C"> + <doc>Specifies the rouding mode for geometry & color SPFP to FP conversions.</doc> + <bitfield name="GEOMETRY_ROUND" high="1" low="0"> + <doc>Trunc (0) or round to nearest (1) for geometry (XY).</doc> + <use-enum ref="ENUM38" /> + </bitfield> + <bitfield name="COLOR_ROUND" high="3" low="2"> + <doc>When set, FP32 to FP20 using round to nearest; otherwise trunc</doc> + <use-enum ref="ENUM38" /> + </bitfield> + <bitfield name="RGB_CLAMP" high="4" low="4"> + <doc>Specifies SPFP color clamp range of [0,1] or FP20 for RGB.</doc> + <value value="0" name="CLAMP_TO"><doc>Clamp to [0,1.0] for RGB</doc></value> + <value value="1" name="RGB_IS_FP20"><doc>RGB is FP20</doc></value> + </bitfield> + <bitfield name="ALPHA_CLAMP" high="5" low="5"> + <doc>Specifies SPFP alpha clamp range of [0,1] or FP20.</doc> + <value value="0" name="CLAMP_TO"><doc>Clamp to [0,1.0] for Alpha</doc></value> + <value value="1" name="ALPHA_IS_FP20"><doc>Alpha is FP20</doc></value> + </bitfield> + <bitfield name="GEOMETRY_MASK" high="9" low="6"> + <doc>4b negative polarity mask for subpixel precision. Inverted version gets ANDed with subpixel X, Y masks.</doc> + </bitfield> + </reg32> + <reg32 name="GA_SOLID_BA" access="rw" offset="0x4280"> + <doc>Specifies blue & alpha components of fill color -- S312 format -- Backwards comp.</doc> + <bitfield name="COLOR_ALPHA" high="15" low="0"> + <doc>Component alpha value. (S3.12)</doc> + </bitfield> + <bitfield name="COLOR_BLUE" high="31" low="16"> + <doc>Component blue value. (S3.12)</doc> + </bitfield> + </reg32> + <reg32 name="GA_SOLID_RG" access="rw" offset="0x427C"> + <doc>Specifies red & green components of fill color -- S312 format -- Backwards comp.</doc> + <bitfield name="COLOR_GREEN" high="15" low="0"> + <doc>Component green value (S3.12).</doc> + </bitfield> + <bitfield name="COLOR_RED" high="31" low="16"> + <doc>Component red value (S3.12).</doc> + </bitfield> + </reg32> + <reg32 name="GA_US_VECTOR_DATA" access="rw" offset="0x4254"> + <doc>Data register for loading US instructions and constants</doc> + </reg32> + <reg32 name="GA_US_VECTOR_INDEX" access="rw" offset="0x4250"> + <doc>Used to load US instructions and constants</doc> + <bitfield name="INDEX" high="8" low="0"> + <doc>Instruction (TYPE == GA_US_VECTOR_INST) or constant (TYPE == GA_US_VECTOR_CONST) number at which to start loading. The GA will then expect n*6 (instructions) or n*4 (constants) writes to GA_US_VECTOR_DATA. The GA will self-increment until this register is written again. For instructions, the GA expects the dwords in the following order: US_CMN_INST, US_ALU_RGB_ADDR, US_ALU_ALPHA_ADDR, US_ALU_ALPHA, US_RGB_INST, US_ALPHA_INST, US_RGBA_INST. For constants, the GA expects the dwords in RGBA order.</doc> + </bitfield> + <bitfield name="TYPE" high="16" low="16"> + <doc>Specifies if the GA should load instructions or constants.</doc> + <value value="0" name="LOAD_INSTRUCTIONS"><doc>Load instructions - INDEX is an instruction index</doc></value> + <value value="1" name="LOAD_CONSTANTS"><doc>Load constants - INDEX is a constant index</doc></value> + </bitfield> + <bitfield name="CLAMP" high="17" low="17"> + <doc></doc> + <value value="0" name="NO_CLAMPING_OF_DATA"><doc>No clamping of data - Default</doc></value> + <value value="1" name="CLAMP_TO"><doc>Clamp to [-1.0,1.0] constant data</doc></value> + </bitfield> + </reg32> + <reg32 name="GB_ENABLE" access="rw" offset="0x4008"> + <doc>Specifies top of Raster pipe specific enable controls.</doc> + <bitfield name="POINT_STUFF_ENABLE" high="0" low="0"> + <doc>Specifies if points will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM43" /> + </bitfield> + <bitfield name="LINE_STUFF_ENABLE" high="1" low="1"> + <doc>Specifies if lines will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM44" /> + </bitfield> + <bitfield name="TRIANGLE_STUFF_ENABLE" high="2" low="2"> + <doc>Specifies if triangles will have stuffed texture coordinates.</doc> + <use-enum ref="ENUM45" /> + </bitfield> + <bitfield name="STENCIL_AUTO" high="5" low="4"> + <doc>Specifies if the auto dec/inc stencil mode should be enabled, and how.</doc> + <use-enum ref="ENUM46" /> + </bitfield> + <bitfield name="TEX0_SOURCE" high="17" low="16"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX1_SOURCE" high="19" low="18"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX2_SOURCE" high="21" low="20"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX3_SOURCE" high="23" low="22"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX4_SOURCE" high="25" low="24"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX5_SOURCE" high="27" low="26"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX6_SOURCE" high="29" low="28"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + <bitfield name="TEX7_SOURCE" high="31" low="30"> + <doc>Specifies the sources of the texture coordinates for each texture.</doc> + <use-enum ref="ENUM229" /> + </bitfield> + </reg32> + <reg32 name="GB_FIFO_SIZE" access="rw" offset="0x4024"> + <doc>Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written</doc> + <bitfield name="SC_IFIFO_SIZE" high="1" low="0"> + <doc>Size of scan converter input FIFO (XYZ)</doc> + <use-enum ref="ENUM55" /> + </bitfield> + <bitfield name="SC_TZFIFO_SIZE" high="3" low="2"> + <doc>Size of scan converter top-of-pipe Z FIFO</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="SC_BFIFO_SIZE" high="5" low="4"> + <doc>Size of scan converter input FIFO (B)</doc> + <use-enum ref="ENUM55" /> + </bitfield> + <bitfield name="RS_TFIFO_SIZE" high="7" low="6"> + <doc>Size of ras input FIFO (Texture)</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="RS_CFIFO_SIZE" high="9" low="8"> + <doc>Size of ras input FIFO (Color)</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="US_RAM_SIZE" high="11" low="10"> + <doc>Size of us RAM</doc> + <use-enum ref="ENUM57" /> + </bitfield> + <bitfield name="US_OFIFO_SIZE" high="13" low="12"> + <doc>Size of us output FIFO (RGBA)</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="US_WFIFO_SIZE" high="15" low="14"> + <doc>Size of us output FIFO (W)</doc> + <use-enum ref="ENUM56" /> + </bitfield> + <bitfield name="RS_HIGHWATER_COL" high="18" low="16"> + <doc>High water mark for RS colors` fifo -- NOT USED</doc> + </bitfield> + <bitfield name="RS_HIGHWATER_TEX" high="21" low="19"> + <doc>High water mark for RS textures` fifo -- NOT USED</doc> + </bitfield> + <bitfield name="US_OFIFO_HIGHWATER" high="23" low="22"> + <doc>High water mark for US output fifo</doc> + <use-enum ref="ENUM58" /> + </bitfield> + <bitfield name="US_CUBE_FIFO_HIGHWATER" high="28" low="24"> + <doc>High water mark for US cube map fifo</doc> + </bitfield> + </reg32> + <reg32 name="GB_FIFO_SIZE1" access="rw" offset="0x4070"> + <doc>Specifies the sizes of the various FIFO`s in the sc/rs.</doc> + <bitfield name="SC_HIGHWATER_IFIFO" high="5" low="0"> + <doc>High water mark for SC input fifo</doc> + </bitfield> + <bitfield name="SC_HIGHWATER_BFIFO" high="11" low="6"> + <doc>High water mark for SC input fifo (B)</doc> + </bitfield> + <bitfield name="RS_HIGHWATER_COL" high="17" low="12"> + <doc>High water mark for RS colors` fifo</doc> + </bitfield> + <bitfield name="RS_HIGHWATER_TEX" high="23" low="18"> + <doc>High water mark for RS textures` fifo</doc> + </bitfield> + </reg32> + <reg32 name="GB_MSPOS0" access="rw" offset="0x4010"> + <doc>Specifies the position of multisamples 0 through 2</doc> + <bitfield name="MS_X0" high="3" low="0"> + <doc>Specifies the x and y position (in subpixels) of multisample 0</doc> + </bitfield> + <bitfield name="MS_Y0" high="7" low="4"> + <doc>Specifies the x and y position (in subpixels) of multisample 0</doc> + </bitfield> + <bitfield name="MS_X1" high="11" low="8"> + <doc>Specifies the x and y position (in subpixels) of multisample 1</doc> + </bitfield> + <bitfield name="MS_Y1" high="15" low="12"> + <doc>Specifies the x and y position (in subpixels) of multisample 1</doc> + </bitfield> + <bitfield name="MS_X2" high="19" low="16"> + <doc>Specifies the x and y position (in subpixels) of multisample 2</doc> + </bitfield> + <bitfield name="MS_Y2" high="23" low="20"> + <doc>Specifies the x and y position (in subpixels) of multisample 2</doc> + </bitfield> + <bitfield name="MSBD0_Y" high="27" low="24"> + <doc>Specifies the minimum x and y distance (in subpixels) between the pixel edge and the multisamples. These values are used in the first (coarse) scan converter</doc> + </bitfield> + <bitfield name="MSBD0_X" high="31" low="28"> + <doc>Specifies the minimum x and y distance (in subpixels) between the pixel edge and the multisamples. These values are used in the first (coarse) scan converter</doc> + </bitfield> + </reg32> + <reg32 name="GB_MSPOS1" access="rw" offset="0x4014"> + <doc>Specifies the position of multisamples 3 through 5</doc> + <bitfield name="MS_X3" high="3" low="0"> + <doc>Specifies the x and y position (in subpixels) of multisample 3</doc> + </bitfield> + <bitfield name="MS_Y3" high="7" low="4"> + <doc>Specifies the x and y position (in subpixels) of multisample 3</doc> + </bitfield> + <bitfield name="MS_X4" high="11" low="8"> + <doc>Specifies the x and y position (in subpixels) of multisample 4</doc> + </bitfield> + <bitfield name="MS_Y4" high="15" low="12"> + <doc>Specifies the x and y position (in subpixels) of multisample 4</doc> + </bitfield> + <bitfield name="MS_X5" high="19" low="16"> + <doc>Specifies the x and y position (in subpixels) of multisample 5</doc> + </bitfield> + <bitfield name="MS_Y5" high="23" low="20"> + <doc>Specifies the x and y position (in subpixels) of multisample 5</doc> + </bitfield> + <bitfield name="MSBD1" high="27" low="24"> + <doc>Specifies the minimum distance (in subpixels) between the pixel edge and the multisamples. This value is used in the second (quad) scan converter</doc> + </bitfield> + </reg32> + <reg32 name="GB_PIPE_SELECT" access="rw" offset="0x402C"> + <doc>Selects which of 4 pipes are active.</doc> + <bitfield name="PIPE0_ID" high="1" low="0"> + <doc>Maps physical pipe 0 to logical pipe ID (def 0).</doc> + </bitfield> + <bitfield name="PIPE1_ID" high="3" low="2"> + <doc>Maps physical pipe 1 to logical pipe ID (def 1).</doc> + </bitfield> + <bitfield name="PIPE2_ID" high="5" low="4"> + <doc>Maps physical pipe 2 to logical pipe ID (def 2).</doc> + </bitfield> + <bitfield name="PIPE3_ID" high="7" low="6"> + <doc>Maps physical pipe 3 to logical pipe ID (def 3).</doc> + </bitfield> + <bitfield name="PIPE_MASK" high="11" low="8"> + <doc>4b mask, indicates which physical pipes are enabled (def none=0x0) -- B3=P3, B2=P2, B1=P1, B0=P0. -- 1: enabled, 0: disabled</doc> + <value value="3" name="P3"><doc>P3, B</doc></value> + <value value="2" name="P2"><doc>P2, B</doc></value> + <value value="1" name="P1"><doc>P1, B</doc></value> + <value value="0" name="P0"><doc>P0. -- 1: enabled,</doc></value> + <value value="0" name="DISABLED"><doc>disabled</doc></value> + </bitfield> + <bitfield name="MAX_PIPE" high="13" low="12"> + <doc>2b, indicates, by the fuses, the max number of allowed pipes. 0 = 1 pipe ... 3 = 4 pipes -- Read Only</doc> + </bitfield> + <bitfield name="BAD_PIPES" high="17" low="14"> + <doc>4b, indicates, by the fuses, the bad pipes: B3=P3, B2=P2, B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only</doc> + <value value="3" name="P3"><doc>P3, B</doc></value> + <value value="2" name="P2"><doc>P2, B</doc></value> + <value value="1" name="P1"><doc>P1, B</doc></value> + <value value="0" name="P0"><doc>P0 --</doc></value> + <value value="1" name="BAD"><doc>bad,</doc></value> + <value value="0" name="GOOD"><doc>good -- Read Only</doc></value> + </bitfield> + <bitfield name="CONFIG_PIPES" high="18" low="18"> + <doc>If this bit is set when writing this register, the logical pipe ID values are assigned automatically based on the values that are read back in the MAX_PIPE and BAD_PIPES fields. This field is always read back as 0.</doc> + <value value="0" name="DO_NOTHING"><doc>Do nothing</doc></value> + <value value="1" name="FORCE_SELF"><doc>Force self-configuration</doc></value> + </bitfield> + </reg32> + <reg32 name="GB_SELECT" access="rw" offset="0x401C"> + <doc>Specifies various polygon specific selects (fog, depth, perspective).</doc> + <bitfield name="FOG_SELECT" high="2" low="0"> + <doc>Specifies source for outgoing (GA to SU) fog value.</doc> + <use-enum ref="ENUM59" /> + </bitfield> + <bitfield name="DEPTH_SELECT" high="3" low="3"> + <doc>Specifies source for outgoing (GA/SU & SU/RAS) depth value.</doc> + <use-enum ref="ENUM60" /> + </bitfield> + <bitfield name="W_SELECT" high="4" low="4"> + <doc>Specifies source for outgoing (1/W) value, used to disable perspective correct colors/textures.</doc> + <use-enum ref="ENUM61" /> + </bitfield> + <bitfield name="FOG_STUFF_ENABLE" high="5" low="5"> + <doc>Controls enabling of fog stuffing into texture coordinate.</doc> + <value value="0" name="DISABLE_FOG_TEXTURE_STUFFING"><doc>Disable fog texture stuffing</doc></value> + <value value="1" name="ENABLE_FOG_TEXTURE_STUFFING"><doc>Enable fog texture stuffing</doc></value> + </bitfield> + <bitfield name="FOG_STUFF_TEX" high="9" low="6"> + <doc>Controls which texture gets fog value</doc> + </bitfield> + <bitfield name="FOG_STUFF_COMP" high="11" low="10"> + <doc>Controls which component of texture gets fog value</doc> + </bitfield> + </reg32> + <reg32 name="GB_TILE_CONFIG" access="rw" offset="0x4018"> + <doc>Specifies the graphics pipeline configuration for rasterization</doc> + <bitfield name="ENABLE" high="0" low="0"> + <doc>Enables tiling, otherwise all tiles receive all polygons.</doc> + <use-enum ref="ENUM62" /> + </bitfield> + <bitfield name="PIPE_COUNT" high="3" low="1"> + <doc>Specifies the number of active pipes and contexts (up to 4 pipes, 1 ctx). When this field is written, it is automatically reduced by hardware so as not to use more pipes than the number indicated in GB_PIPE_SELECT.MAX_PIPES or the number of pipes left unmasked GB_PIPE_SELECT.BAD_PIPES. The potentially altered value is read back, rather than the original value written by software.</doc> + <value value="0" name="RV350"><doc>RV350 (1 pipe, 1 ctx)</doc></value> + <value value="3" name="R300"><doc>R300 (2 pipes, 1 ctx) 06 – R420-3P (3 pipes, 1 ctx) 07 – R420 (4 pipes, 1 ctx)</doc></value> + </bitfield> + <bitfield name="TILE_SIZE" high="5" low="4"> + <doc>Specifies width & height (square), in pixels (only 16, 32 available).</doc> + <value value="0" name="8_PIXELS"><doc>8 pixels.</doc></value> + <value value="1" name="16_PIXELS"><doc>16 pixels.</doc></value> + <value value="2" name="32_PIXELS"><doc>32 pixels.</doc></value> + </bitfield> + <bitfield name="SUPER_SIZE" high="8" low="6"> + <doc>Specifies number of tiles and config in super chip configuration.</doc> + <use-enum ref="ENUM65" /> + </bitfield> + <bitfield name="SUPER_X" high="11" low="9"> + <doc>X Location of chip within super tile.</doc> + </bitfield> + <bitfield name="SUPER_Y" high="14" low="12"> + <doc>Y Location of chip within super tile.</doc> + </bitfield> + <bitfield name="SUPER_TILE" high="15" low="15"> + <doc>Tile location of chip in a multi super tile config (Super size of 2,8,32 or 128).</doc> + <use-enum ref="ENUM66" /> + </bitfield> + <bitfield name="SUBPIXEL" high="16" low="16"> + <doc>Specifies the precision of subpixels wrt pixels (12 or 16).</doc> + <use-enum ref="ENUM67" /> + </bitfield> + <bitfield name="QUADS_PER_RAS" high="18" low="17"> + <doc>Specifies the number of quads to be sent to each rasterizer in turn when in RV300B or R300B mode</doc> + <value value="0" name="4_QUADS"><doc>4 Quads</doc></value> + <value value="1" name="8_QUADS"><doc>8 Quads</doc></value> + <value value="2" name="16_QUADS"><doc>16 Quads</doc></value> + <value value="3" name="32_QUADS"><doc>32 Quads</doc></value> + </bitfield> + <bitfield name="BB_SCAN" high="19" low="19"> + <doc>Specifies whether to use an intercept or bounding box based calculation for the first (coarse) scan converter</doc> + <value value="0" name="USE_INTERCEPT_BASED_SCAN_CONVERTER"><doc>Use intercept based scan converter</doc></value> + <value value="1" name="USE_BOUNDING_BOX_BASED_SCAN_CONVERTER"><doc>Use bounding box based scan converter</doc></value> + </bitfield> + <bitfield name="ALT_SCAN_EN" high="20" low="20"> + <doc>Specifies whether to use an altenate scan pattern for the coarse scan converter</doc> + <value value="0" name="USE_NORMAL_LEFT"><doc>Use normal left-right scan</doc></value> + <value value="1" name="USE_ALTERNATE_LEFT"><doc>Use alternate left-right-left scan</doc></value> + </bitfield> + <bitfield name="ALT_OFFSET" high="21" low="21"> + <doc>Not used -- should be 0</doc> + <value value="0" name="NOT_USED"><doc>Not used</doc></value> + <value value="1" name="NOT_USED"><doc>Not used</doc></value> + </bitfield> + <bitfield name="SUBPRECISION" high="22" low="22"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="ALT_TILING" high="23" low="23"> + <doc>Support for 3x2 tiling in 3P mode</doc> + <value value="0" name="USE_DEFAULT_TILING_IN_ALL_TILING_MODES"><doc>Use default tiling in all tiling modes</doc></value> + <value value="1" name="USE_ALTERNATIVE_3X2_TILING_IN_3P_MODE"><doc>Use alternative 3x2 tiling in 3P mode</doc></value> + </bitfield> + <bitfield name="Z_EXTENDED" high="24" low="24"> + <doc>Support for extended setup Z range from [0,1] to [-2,2] with per pixel clamping</doc> + <value value="0" name="USE"><doc>Use (24.1) Z format, with vertex clamp to [1.0,0.0]</doc></value> + <value value="1" name="USE"><doc>Use (S25.1) format, with vertex clamp to [2.0,- 2.0] and per pixel [1.0,0.0]</doc></value> + </bitfield> + </reg32> + <reg32 name="GB_Z_PEQ_CONFIG" access="rw" offset="0x4028"> + <doc>Specifies the z plane equation configuration.</doc> + <bitfield name="Z_PEQ_SIZE" high="0" low="0"> + <doc>Specifies the z plane equation size.</doc> + <value value="0" name="4X4_Z_PLANE_EQUATIONS"><doc>4x4 z plane equations (point-sampled or aa)</doc></value> + <value value="1" name="8X8_Z_PLANE_EQUATIONS"><doc>8x8 z plane equations (point-sampled only)</doc></value> + </bitfield> + </reg32> + <reg32 name="RS_COUNT" access="rw" offset="0x4300"> + <doc>This register specifies the rasterizer input packet configuration</doc> + <bitfield name="IT_COUNT" high="6" low="0"> + <doc>Specifies the total number of texture address components contained in the rasterizer input packet (0:32).</doc> + </bitfield> + <bitfield name="IC_COUNT" high="10" low="7"> + <doc>Specifies the total number of colors contained in the rasterizer input packet (0:4).</doc> + </bitfield> + <bitfield name="W_ADDR" high="17" low="12"> + <doc>Specifies the relative rasterizer input packet location of w (if w_count==1)</doc> + </bitfield> + <bitfield name="HIRES_EN" high="18" low="18"> + <doc>Enable high resolution texture coordinate output when q is equal to 1</doc> + </bitfield> + </reg32> + <stripe offset="0x4320" stride="0x0004" length="16"> + <reg32 name="RS_INST" access="rw" offset="0x0000"> + <doc>This table specifies what happens during each rasterizer instruction</doc> + <bitfield name="TEX_ID" high="3" low="0"> + <doc>Specifies the index (into the RS_IP table) of the texture address output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="TEX_CN" high="4" low="4"> + <doc>Write enable for texture address</doc> + <use-enum ref="ENUM68" /> + </bitfield> + <bitfield name="TEX_ADDR" high="11" low="5"> + <doc>Specifies the destination address (within the current pixel stack frame) of the texture address output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="COL_ID" high="15" low="12"> + <doc>Specifies the index (into the RS_IP table) of the color output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="COL_CN" high="17" low="16"> + <doc>Write enable for color</doc> + <value value="0" name="NO_WRITE"><doc>No write - color not valid</doc></value> + <value value="1" name="WRITE"><doc>write - color valid</doc></value> + <value value="2" name="WRITE_FBUFFER"><doc>write fbuffer - XY00->RGBA</doc></value> + <value value="3" name="WRITE_BACKFACE"><doc>write backface - B000->RGBA</doc></value> + </bitfield> + <bitfield name="COL_ADDR" high="24" low="18"> + <doc>Specifies the destination address (within the current pixel stack frame) of the color output during this rasterizer instruction</doc> + </bitfield> + <bitfield name="TEX_ADJ" high="25" low="25"> + <doc>Specifies whether to sample texture coordinates at the real or adjusted pixel centers</doc> + <use-enum ref="ENUM70" /> + </bitfield> + <bitfield name="W_CN" high="26" low="26"> + <doc>Specifies that the rasterizer should output w</doc> + <value value="0" name="NO_WRITE"><doc>No write - w not valid</doc></value> + <value value="1" name="WRITE"><doc>write - w valid</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="RS_INST_COUNT" access="rw" offset="0x4304"> + <doc>This register specifies the number of rasterizer instructions</doc> + <bitfield name="INST_COUNT" high="3" low="0"> + <doc>Number of rasterizer instructions (1:16)</doc> + </bitfield> + <bitfield name="TX_OFFSET" high="7" low="5"> + <doc>Indicates range of texture offset to minimize peroidic errors on texels sampled right on their edges</doc> + </bitfield> + </reg32> + <stripe offset="0x4074" stride="0x0004" length="16"> + <reg32 name="RS_IP" access="rw" offset="0x0000"> + <doc>This table specifies the source location and format for up to 16 texture addresses (i[0]:i[15]) and four colors (c[0]:c[3])</doc> + <bitfield name="TEX_PTR_S" high="5" low="0"> + <doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc> + </bitfield> + <bitfield name="TEX_PTR_T" high="11" low="6"> + <doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc> + </bitfield> + <bitfield name="TEX_PTR_R" high="17" low="12"> + <doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc> + </bitfield> + <bitfield name="TEX_PTR_Q" high="23" low="18"> + <doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc> + </bitfield> + <bitfield name="COL_PTR" high="26" low="24"> + <doc>Specifies the relative rasterizer input packet location of the color (c[i]).</doc> + </bitfield> + <bitfield name="COL_FMT" high="30" low="27"> + <doc>Specifies the format of the color (c[i]).</doc> + <use-enum ref="ENUM72" /> + </bitfield> + <bitfield name="OFFSET_EN" high="31" low="31"> + <doc>Enable application of the TX_OFFSET in RS_INST_COUNT</doc> + <value value="0" name="DO_NOT_APPLY_THE_TX_OFFSET_IN_RS_INST_COUNT"><doc>Do not apply the TX_OFFSET in RS_INST_COUNT</doc></value> + <value value="1" name="APPLY_THE_TX_OFFSET_SPECIFIED_BY_RS_INST_COUNT"><doc>Apply the TX_OFFSET specified by RS_INST_COUNT</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="SC_EDGERULE" access="rw" offset="0x43A8"> + <doc>Edge rules - what happens when an edge falls exactly on a sample point</doc> + <bitfield name="ER_TRI" high="4" low="0"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_POINT" high="9" low="5"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_LINE_LR" high="14" low="10"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_LINE_RL" high="19" low="15"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_LINE_TB" high="24" low="20"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + <bitfield name="ER_LINE_BT" high="29" low="25"> + <doc>Edge rules for triangles, points, left-right lines, right-left lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, bit 0 specifies whether a sample on a horizontal- bottom edge is in, bit 1 specifies whether a sample on a horizontal-top edge is in, bit 2 species whether a sample on a right edge is in, bit 3 specifies whether a sample on a left edge is in. For values 16 to 31, bit 0 specifies whether a sample on a vertical-right edge is in, bit 1 specifies whether a sample on a vertical-left edge is in, bit 2 species whether a sample on a bottom edge is in, bit 3 specifies whether a sample on a top edge is in</doc> + <use-enum ref="ENUM74" /> + </bitfield> + </reg32> + <reg32 name="SU_REG_DEST" access="rw" offset="0x42C8"> + <doc>SU Raster pipe destination select for registers</doc> + <bitfield name="SELECT" high="3" low="0"> + <doc>Register read/write destination select: b0: logical pipe0, b1: logical pipe1, b2: logical pipe2 and b3: logical pipe3</doc> + <value value="0" name="LOGICAL_PIPE0"><doc>logical pipe0, b</doc></value> + <value value="1" name="LOGICAL_PIPE1"><doc>logical pipe1, b</doc></value> + <value value="2" name="LOGICAL_PIPE2_AND_B"><doc>logical pipe2 and b</doc></value> + <value value="3" name="LOGICAL_PIPE3"><doc>logical pipe3</doc></value> + </bitfield> + </reg32> + <reg32 name="SU_TEX_WRAP" access="rw" offset="0x42A0"> + <doc>Enables for Cylindrical Wrapping</doc> + <bitfield name="T0C0" high="0" low="0"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T0C1" high="1" low="1"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T0C2" high="2" low="2"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T0C3" high="3" low="3"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T1C0" high="4" low="4"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T1C1" high="5" low="5"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T1C2" high="6" low="6"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T1C3" high="7" low="7"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T2C0" high="8" low="8"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T2C1" high="9" low="9"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T2C2" high="10" low="10"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T2C3" high="11" low="11"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T3C0" high="12" low="12"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T3C1" high="13" low="13"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T3C2" high="14" low="14"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T3C3" high="15" low="15"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T4C0" high="16" low="16"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T4C1" high="17" low="17"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T4C2" high="18" low="18"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T4C3" high="19" low="19"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T5C0" high="20" low="20"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T5C1" high="21" low="21"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T5C2" high="22" low="22"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T5C3" high="23" low="23"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T6C0" high="24" low="24"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T6C1" high="25" low="25"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T6C2" high="26" low="26"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T6C3" high="27" low="27"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T7C0" high="28" low="28"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T7C1" high="29" low="29"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T7C2" high="30" low="30"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T7C3" high="31" low="31"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + </reg32> + <reg32 name="SU_TEX_WRAP_PS3" access="rw" offset="0x4114"> + <doc>Specifies texture wrapping for new PS3 textures.</doc> + <bitfield name="T9C0" high="0" low="0"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T9C1" high="1" low="1"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T9C2" high="2" low="2"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T9C3" high="3" low="3"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T8C0" high="4" low="4"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T8C1" high="5" low="5"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T8C2" high="6" low="6"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + <bitfield name="T8C3" high="7" low="7"> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of texture N.</doc> + <use-enum ref="ENUM247" /> + </bitfield> + </reg32> + <stripe offset="0x45C0" stride="0x0004" length="16"> + <reg32 name="TX_BORDER_COLOR" access="rw" offset="0x0000"> + <doc>Border Color</doc> + </reg32> + </stripe> + <stripe offset="0x4580" stride="0x0004" length="16"> + <reg32 name="TX_CHROMA_KEY" access="rw" offset="0x0000"> + <doc>Texture Chroma Key</doc> + </reg32> + </stripe> + <reg32 name="TX_ENABLE" access="rw" offset="0x4104"> + <doc>Texture Enables for Maps 0 to 15</doc> + <bitfield name="TEX_0_ENABLE" high="0" low="0"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_1_ENABLE" high="1" low="1"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_2_ENABLE" high="2" low="2"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_3_ENABLE" high="3" low="3"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_4_ENABLE" high="4" low="4"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_5_ENABLE" high="5" low="5"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_6_ENABLE" high="6" low="6"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_7_ENABLE" high="7" low="7"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_8_ENABLE" high="8" low="8"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_9_ENABLE" high="9" low="9"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_10_ENABLE" high="10" low="10"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_11_ENABLE" high="11" low="11"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_12_ENABLE" high="12" low="12"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_13_ENABLE" high="13" low="13"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_14_ENABLE" high="14" low="14"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + <bitfield name="TEX_15_ENABLE" high="15" low="15"> + <doc>Texture Map Enables.</doc> + <use-enum ref="ENUM248" /> + </bitfield> + </reg32> + <stripe offset="0x4400" stride="0x0004" length="16"> + <reg32 name="TX_FILTER0" access="rw" offset="0x0000"> + <doc>Texture Filter State</doc> + <bitfield name="CLAMP_S" high="2" low="0"> + <doc>Clamp mode for texture coordinates</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="CLAMP_T" high="5" low="3"> + <doc>Clamp mode for texture coordinates</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="CLAMP_R" high="8" low="6"> + <doc>Clamp mode for texture coordinates</doc> + <use-enum ref="ENUM136" /> + </bitfield> + <bitfield name="MAG_FILTER" high="10" low="9"> + <doc>Filter used when texture is magnified</doc> + <use-enum ref="ENUM249" /> + </bitfield> + <bitfield name="MIN_FILTER" high="12" low="11"> + <doc>Filter used when texture is minified</doc> + <use-enum ref="ENUM249" /> + </bitfield> + <bitfield name="MIP_FILTER" high="14" low="13"> + <doc>Filter used between mipmap levels</doc> + <use-enum ref="ENUM138" /> + </bitfield> + <bitfield name="VOL_FILTER" high="16" low="15"> + <doc>Filter used between layers of a volume</doc> + <use-enum ref="ENUM139" /> + </bitfield> + <bitfield name="MAX_MIP_LEVEL" high="20" low="17"> + <doc>LOD index of largest (finest) mipmap to use (0 is largest). Ranges from 0 to NUM_LEVELS.</doc> + </bitfield> + <bitfield name="ID" high="31" low="28"> + <doc>Logical id for this physical texture</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4440" stride="0x0004" length="16"> + <reg32 name="TX_FILTER1" access="rw" offset="0x0000"> + <doc>Texture Filter State</doc> + <bitfield name="CHROMA_KEY_MODE" high="1" low="0"> + <doc>Chroma Key Mode</doc> + <use-enum ref="ENUM140" /> + </bitfield> + <bitfield name="MC_ROUND" high="2" low="2"> + <doc>Bilinear rounding mode</doc> + <use-enum ref="ENUM141" /> + </bitfield> + <bitfield name="LOD_BIAS" high="12" low="3"> + <doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias measured in mipmap levels. Added to the signed, computed LOD before the LOD is clamped.</doc> + </bitfield> + <bitfield name="MC_COORD_TRUNCATE" high="14" low="14"> + <doc>MPEG coordinate truncation mode</doc> + <use-enum ref="ENUM142" /> + </bitfield> + <bitfield name="TRI_PERF" high="16" low="15"> + <doc>Apply slope and bias to trilerp fraction to reduce the number of 2-level fetches for trilinear. Should only be used if MIP_FILTER is LINEAR.</doc> + <value value="0" name="BREAKPOINT"><doc>Breakpoint=0/8. lfrac_out = lfrac_in</doc></value> + <value value="1" name="BREAKPOINT"><doc>Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in - 1/6)</doc></value> + <value value="2" name="BREAKPOINT"><doc>Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in - 1/2)</doc></value> + <value value="3" name="BREAKPOINT"><doc>Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in - 3/2)</doc></value> + </bitfield> + <bitfield name="Reserved" high="19" low="17"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="Reserved" high="20" low="20"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="Reserved" high="21" low="21"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="MACRO_SWITCH" high="22" low="22"> + <doc>If enabled, addressing switches to macro-linear when image width is <= 8 micro-tiles. If disabled, functionality is same as RV350, switch to macro-linear when image width is < 8 micro-tiles.</doc> + <value value="0" name="RV350_MODE"><doc>RV350 mode</doc></value> + <value value="1" name="SWITCH_FROM_MACRO"><doc>Switch from macro-tiled to macro-linear when (width <= 8 micro-tiles)</doc></value> + </bitfield> + <bitfield name="BORDER_FIX" high="31" low="31"> + <doc>To fix issues when using non-square mipmaps, with border_color, and extreme minification.</doc> + <value value="0" name="R3XX_R4XX_MODE"><doc>R3xx R4xx mode</doc></value> + <value value="1" name="STOP_RIGHT_SHIFTING_COORD_ONCE_MIP_SIZE_IS_PINNED_TO_ONE"><doc>Stop right shifting coord once mip size is pinned to one</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="TX_FILTER4" access="rw" offset="0x4110"> + <doc>Filter4 Kernel</doc> + <bitfield name="WEIGHT_1" high="10" low="0"> + <doc>(s1.9). Bottom or Right weight of pair.</doc> + </bitfield> + <bitfield name="WEIGHT_0" high="21" low="11"> + <doc>(s1.9). Top or Left weight of pair.</doc> + </bitfield> + <bitfield name="WEIGHT_PAIR" high="22" low="22"> + <doc>Indicates which pair of weights within phase to load.</doc> + <value value="0" name="TOP_OR_LEFT"><doc>Top or Left</doc></value> + <value value="1" name="BOTTOM_OR_RIGHT"><doc>Bottom or Right</doc></value> + </bitfield> + <bitfield name="PHASE" high="26" low="23"> + <doc>Indicates which of 9 phases to load</doc> + </bitfield> + <bitfield name="DIRECTION" high="27" low="27"> + <doc>Indicates whether to load the horizontal or vertical weights</doc> + <value value="0" name="HORIZONTAL"><doc>Horizontal</doc></value> + <value value="1" name="VERTICAL"><doc>Vertical</doc></value> + </bitfield> + </reg32> + <stripe offset="0x4480" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT0" access="rw" offset="0x0000"> + <doc>Texture Format State</doc> + <bitfield name="TXWIDTH" high="10" low="0"> + <doc>Image width - 1. The largest image is 4096 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc> + </bitfield> + <bitfield name="TXHEIGHT" high="21" low="11"> + <doc>Image height - 1. The largest image is 4096 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc> + </bitfield> + <bitfield name="TXDEPTH" high="25" low="22"> + <doc>LOG2(depth) of volume texture</doc> + </bitfield> + <bitfield name="NUM_LEVELS" high="29" low="26"> + <doc>Number of mipmap levels minus 1. Ranges from 0 to 12. Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc> + </bitfield> + <bitfield name="PROJECTED" high="30" low="30"> + <doc>Specifies whether texture coords are projected.</doc> + <use-enum ref="ENUM143" /> + </bitfield> + <bitfield name="TXPITCH_EN" high="31" low="31"> + <doc>Indicates when TXPITCH should be used instead of TXWIDTH for image addressing</doc> + <use-enum ref="ENUM144" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x44C0" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT1" access="rw" offset="0x0000"> + <doc>Texture Format State</doc> + <bitfield name="TXFORMAT" high="4" low="0"> + <doc>Texture Format. Components are numbered right to left. Parenthesis indicate typical uses of each format.</doc> + <value value="0" name="TX_FMT_8_OR_TX_FMT_1"><doc>TX_FMT_8 or TX_FMT_1 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="1" name="TX_FMT_16_OR_TX_FMT_1_REVERSE"><doc>TX_FMT_16 or TX_FMT_1_REVERSE (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="2" name="TX_FMT_4_4_OR_TX_FMT_10"><doc>TX_FMT_4_4 or TX_FMT_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="3" name="TX_FMT_8_8_OR_TX_FMT_10_10"><doc>TX_FMT_8_8 or TX_FMT_10_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="4" name="TX_FMT_16_16_OR_TX_FMT_10_10_10_10"><doc>TX_FMT_16_16 or TX_FMT_10_10_10_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="5" name="TX_FMT_3_3_2_OR_TX_FMT_ATI1N"><doc>TX_FMT_3_3_2 or TX_FMT_ATI1N (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="6" name="TX_FMT_5_6_5"><doc>TX_FMT_5_6_5</doc></value> + <value value="7" name="TX_FMT_6_5_5"><doc>TX_FMT_6_5_5</doc></value> + <value value="8" name="TX_FMT_11_11_10"><doc>TX_FMT_11_11_10</doc></value> + <value value="9" name="TX_FMT_10_11_11"><doc>TX_FMT_10_11_11</doc></value> + <value value="10" name="TX_FMT_4_4_4_4"><doc>TX_FMT_4_4_4_4</doc></value> + <value value="11" name="TX_FMT_1_5_5_5"><doc>TX_FMT_1_5_5_5</doc></value> + <value value="12" name="TX_FMT_8_8_8_8"><doc>TX_FMT_8_8_8_8</doc></value> + <value value="13" name="TX_FMT_2_10_10_10"><doc>TX_FMT_2_10_10_10</doc></value> + <value value="14" name="TX_FMT_16_16_16_16"><doc>TX_FMT_16_16_16_16</doc></value> + <value value="18" name="TX_FMT_Y8"><doc>TX_FMT_Y8</doc></value> + <value value="19" name="TX_FMT_AVYU444"><doc>TX_FMT_AVYU444</doc></value> + <value value="20" name="TX_FMT_VYUY422"><doc>TX_FMT_VYUY422</doc></value> + <value value="21" name="TX_FMT_YVYU422"><doc>TX_FMT_YVYU422</doc></value> + <value value="22" name="TX_FMT_16_MPEG"><doc>TX_FMT_16_MPEG</doc></value> + <value value="23" name="TX_FMT_16_16_MPEG"><doc>TX_FMT_16_16_MPEG</doc></value> + <value value="24" name="TX_FMT_16F"><doc>TX_FMT_16f</doc></value> + <value value="25" name="TX_FMT_16F_16F"><doc>TX_FMT_16f_16f</doc></value> + <value value="26" name="TX_FMT_16F_16F_16F_16F"><doc>TX_FMT_16f_16f_16f_16f</doc></value> + <value value="27" name="TX_FMT_32F"><doc>TX_FMT_32f</doc></value> + <value value="28" name="TX_FMT_32F_32F"><doc>TX_FMT_32f_32f</doc></value> + <value value="29" name="TX_FMT_32F_32F_32F_32F"><doc>TX_FMT_32f_32f_32f_32f</doc></value> + <value value="30" name="TX_FMT_W24_FP"><doc>TX_FMT_W24_FP</doc></value> + <value value="31" name="TX_FMT_ATI2N"><doc>TX_FMT_ATI2N</doc></value> + </bitfield> + <bitfield name="SIGNED_COMP0" high="5" low="5"> + <doc>Component filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM256" /> + </bitfield> + <bitfield name="SIGNED_COMP1" high="6" low="6"> + <doc>Component filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM256" /> + </bitfield> + <bitfield name="SIGNED_COMP2" high="7" low="7"> + <doc>Component filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM256" /> + </bitfield> + <bitfield name="SIGNED_COMP3" high="8" low="8"> + <doc>Component filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM256" /> + </bitfield> + <bitfield name="SEL_ALPHA" high="11" low="9"> + <doc>Specifies swizzling for each channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM257" /> + </bitfield> + <bitfield name="SEL_RED" high="14" low="12"> + <doc>Specifies swizzling for each channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM257" /> + </bitfield> + <bitfield name="SEL_GREEN" high="17" low="15"> + <doc>Specifies swizzling for each channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM257" /> + </bitfield> + <bitfield name="SEL_BLUE" high="20" low="18"> + <doc>Specifies swizzling for each channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> + <use-enum ref="ENUM257" /> + </bitfield> + <bitfield name="GAMMA" high="21" low="21"> + <doc>Optionally remove gamma from texture before passing to shader. Only apply to 8bit or less components.</doc> + <use-enum ref="ENUM154" /> + </bitfield> + <bitfield name="YUV_TO_RGB" high="23" low="22"> + <doc>YUV to RGB conversion mode</doc> + <use-enum ref="ENUM155" /> + </bitfield> + <bitfield name="SWAP_YUV" high="24" low="24"> + <doc></doc> + <use-enum ref="ENUM156" /> + </bitfield> + <bitfield name="TEX_COORD_TYPE" high="26" low="25"> + <doc>Specifies coordinate type.</doc> + <use-enum ref="ENUM157" /> + </bitfield> + <bitfield name="CACHE" high="31" low="27"> + <doc>This field is ignored on R520 and RV510.</doc> + <use-enum ref="ENUM158" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4500" stride="0x0004" length="16"> + <reg32 name="TX_FORMAT2" access="rw" offset="0x0000"> + <doc>Texture Format State</doc> + <bitfield name="TXPITCH" high="13" low="0"> + <doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN is asserted. Pitch is given as number of texels minus one. Maximum pitch is 16K texels.</doc> + </bitfield> + <bitfield name="TXFORMAT_MSB" high="14" low="14"> + <doc>Specifies the MSB of the texture format to extend the number of formats to 64.</doc> + </bitfield> + <bitfield name="TXWIDTH_11" high="15" low="15"> + <doc>Specifies bit 11 of TXWIDTH to extend the largest image to 4096 texels.</doc> + </bitfield> + <bitfield name="TXHEIGHT_11" high="16" low="16"> + <doc>Specifies bit 11 of TXHEIGHT to extend the largest image to 4096 texels.</doc> + </bitfield> + <bitfield name="POW2FIX2FLT" high="17" low="17"> + <doc>Optionally divide by 256 instead of 255 during fix2float. Can only be asserted for 8-bit components.</doc> + <value value="0" name="DIVIDE_BY_POW2"><doc>Divide by pow2-1 for fix2float (default)</doc></value> + <value value="1" name="DIVIDE_BY_POW2_FOR_FIX2FLOAT"><doc>Divide by pow2 for fix2float</doc></value> + </bitfield> + <bitfield name="SEL_FILTER4" high="19" low="18"> + <doc>If filter4 is enabled, specifies which texture component to apply filter4 to.</doc> + <value value="0" name="SELECT_TEXTURE_COMPONENT0"><doc>Select Texture Component0.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1"><doc>Select Texture Component1.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2"><doc>Select Texture Component2.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3"><doc>Select Texture Component3.</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4540" stride="0x0004" length="16"> + <reg32 name="TX_OFFSET" access="rw" offset="0x0000"> + <doc>Texture Offset State</doc> + <bitfield name="ENDIAN_SWAP" high="1" low="0"> + <doc>Endian Control</doc> + <use-enum ref="ENUM159" /> + </bitfield> + <bitfield name="MACRO_TILE" high="2" low="2"> + <doc>Macro Tile Control</doc> + <use-enum ref="ENUM160" /> + </bitfield> + <bitfield name="MICRO_TILE" high="4" low="3"> + <doc>Micro Tile Control</doc> + <use-enum ref="ENUM161" /> + </bitfield> + <bitfield name="TXOFFSET" high="31" low="5"> + <doc>32-byte aligned pointer to base map</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0xA800" stride="0x0004" length="512"> + <reg32 name="US_ALU_ALPHA_INST" access="rw" offset="0x0000"> + <doc>ALU Alpha Instruction</doc> + <bitfield name="ALPHA_OP" high="3" low="0"> + <doc>Specifies the opcode for this instruction.</doc> + <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> + <value value="1" name="OP_DP"><doc>OP_DP: Result = dot product from RGB ALU</doc></value> + <value value="2" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> + <value value="3" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> + <value value="5" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> + <value value="6" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> + <value value="7" name="OP_FRC"><doc>OP_FRC: Result = A-floor(A)</doc></value> + <value value="8" name="OP_EX"><doc>OP_EX</doc></value> + <value value="2" name="RESULT"><doc>Result = 2^^A</doc></value> + <value value="9" name="OP_LN"><doc>OP_LN</doc></value> + <value value="2" name="RESULT"><doc>Result = log2(A)</doc></value> + <value value="10" name="OP_RCP"><doc>OP_RCP: Result = 1/A</doc></value> + <value value="11" name="OP_RSQ"><doc>OP_RSQ: Result = 1/sqrt(A)</doc></value> + <value value="12" name="OP_SIN"><doc>OP_SIN: Result = sin(A*2pi)</doc></value> + <value value="13" name="OP_COS"><doc>OP_COS: Result = cos(A*2pi)</doc></value> + <value value="14" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + <value value="15" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + </bitfield> + <bitfield name="ALPHA_ADDRD" high="10" low="4"> + <doc>Specifies the address of the pixel stack frame register to which the Alpha result of this instruction is to be written.</doc> + </bitfield> + <bitfield name="ALPHA_ADDRD_REL" high="11" low="11"> + <doc>Specifies whether the loop register is added to the value of ALPHA_ADDRD before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM261" /> + </bitfield> + <bitfield name="ALPHA_SEL_A" high="13" low="12"> + <doc>Specifies the operands for Alpha inputs A and B.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="ALPHA_SWIZ_A" high="16" low="14"> + <doc>Specifies the channel sources for Alpha inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="ALPHA_MOD_A" high="18" low="17"> + <doc>Specifies the input modifiers for Alpha inputs A and B.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="ALPHA_SEL_B" high="20" low="19"> + <doc>Specifies the operands for Alpha inputs A and B.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="ALPHA_SWIZ_B" high="23" low="21"> + <doc>Specifies the channel sources for Alpha inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="ALPHA_MOD_B" high="25" low="24"> + <doc>Specifies the input modifiers for Alpha inputs A and B.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="OMOD" high="28" low="26"> + <doc>Specifies the output modifier for this instruction.</doc> + <use-enum ref="ENUM264" /> + </bitfield> + <bitfield name="TARGET" high="30" low="29"> + <doc>This specifies which (cached) frame buffer target to write to. For non-output ALU instructions, this specifies how to compare the results against zero when setting the predicate bits.</doc> + <use-enum ref="ENUM265" /> + </bitfield> + <bitfield name="W_OMASK" high="31" low="31"> + <doc>Specifies whether or not to write the Alpha component of the result of this instuction to the depth output fifo.</doc> + <value value="0" name="NONE"><doc>NONE: Do not write output to w.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only to w.</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x9800" stride="0x0004" length="512"> + <reg32 name="US_ALU_ALPHA_ADDR" access="rw" offset="0x0000"> + <doc>This table specifies the Alpha source addresses and pre-subtract operation for up to 512 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> + <bitfield name="ADDR0" high="7" low="0"> + <doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR0_CONST" high="8" low="8"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR0_REL" high="9" low="9"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="ADDR1" high="17" low="10"> + <doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR1_CONST" high="18" low="18"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR1_REL" high="19" low="19"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="ADDR2" high="27" low="20"> + <doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR2_CONST" high="28" low="28"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR2_REL" high="29" low="29"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="SRCP_OP" high="31" low="30"> + <doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> + <use-enum ref="ENUM168" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0xB000" stride="0x0004" length="512"> + <reg32 name="US_ALU_RGBA_INST" access="rw" offset="0x0000"> + <doc>ALU Shared RGBA Instruction</doc> + <bitfield name="RGB_OP" high="3" low="0"> + <doc>Specifies the opcode for this instruction.</doc> + <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> + <value value="1" name="OP_DP"><doc>OP_DP</doc></value> + <value value="3" name="RESULT"><doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> + <value value="2" name="OP_DP"><doc>OP_DP</doc></value> + <value value="4" name="RESULT"><doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc></value> + <value value="3" name="OP_D2A"><doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc></value> + <value value="4" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> + <value value="5" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> + <value value="7" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> + <value value="8" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> + <value value="9" name="OP_FRC"><doc>OP_FRC: Result = A-floor(A)</doc></value> + <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from Alpha ALU</doc></value> + <value value="11" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + <value value="12" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + </bitfield> + <bitfield name="RGB_ADDRD" high="10" low="4"> + <doc>Specifies the address of the pixel stack frame register to which the RGB result of this instruction is to be written.</doc> + </bitfield> + <bitfield name="RGB_ADDRD_REL" high="11" low="11"> + <doc>Specifies whether the loop register is added to the value of RGB_ADDRD before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM261" /> + </bitfield> + <bitfield name="RGB_SEL_C" high="13" low="12"> + <doc>Specifies the operands for RGB and Alpha input C.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="RED_SWIZ_C" high="16" low="14"> + <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="GREEN_SWIZ_C" high="19" low="17"> + <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="BLUE_SWIZ_C" high="22" low="20"> + <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="RGB_MOD_C" high="24" low="23"> + <doc>Specifies the input modifiers for RGB and Alpha input C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="ALPHA_SEL_C" high="26" low="25"> + <doc>Specifies the operands for RGB and Alpha input C.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="ALPHA_SWIZ_C" high="29" low="27"> + <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="ALPHA_MOD_C" high="31" low="30"> + <doc>Specifies the input modifiers for RGB and Alpha input C.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0xA000" stride="0x0004" length="512"> + <reg32 name="US_ALU_RGB_INST" access="rw" offset="0x0000"> + <doc>ALU RGB Instruction</doc> + <bitfield name="RGB_SEL_A" high="1" low="0"> + <doc>Specifies the operands for RGB inputs A and B.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="RED_SWIZ_A" high="4" low="2"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="GREEN_SWIZ_A" high="7" low="5"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="BLUE_SWIZ_A" high="10" low="8"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="RGB_MOD_A" high="12" low="11"> + <doc>Specifies the input modifiers for RGB inputs A and B.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="RGB_SEL_B" high="14" low="13"> + <doc>Specifies the operands for RGB inputs A and B.</doc> + <use-enum ref="ENUM262" /> + </bitfield> + <bitfield name="RED_SWIZ_B" high="17" low="15"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="GREEN_SWIZ_B" high="20" low="18"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="BLUE_SWIZ_B" high="23" low="21"> + <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> + <use-enum ref="ENUM263" /> + </bitfield> + <bitfield name="RGB_MOD_B" high="25" low="24"> + <doc>Specifies the input modifiers for RGB inputs A and B.</doc> + <use-enum ref="ENUM167" /> + </bitfield> + <bitfield name="OMOD" high="28" low="26"> + <doc>Specifies the output modifier for this instruction.</doc> + <use-enum ref="ENUM264" /> + </bitfield> + <bitfield name="TARGET" high="30" low="29"> + <doc>This specifies which (cached) frame buffer target to write to. For non-output ALU instructions, this specifies how to compare the results against zero when setting the predicate bits.</doc> + <use-enum ref="ENUM265" /> + </bitfield> + <bitfield name="ALU_WMASK" high="31" low="31"> + <doc>Specifies whether to update the current ALU result.</doc> + <value value="0" name="DO_NOT_MODIFY_THE_CURRENT_ALU_RESULT"><doc>Do not modify the current ALU result.</doc></value> + <value value="1" name="MODIFY_THE_CURRENT_ALU_RESULT_BASED_ON_THE_SETTINGS_OF_ALU_RESULT_SEL_AND_ALU_RESULT_OP"><doc>Modify the current ALU result based on the settings of ALU_RESULT_SEL and ALU_RESULT_OP.</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x9000" stride="0x0004" length="512"> + <reg32 name="US_ALU_RGB_ADDR" access="rw" offset="0x0000"> + <doc>This table specifies the RGB source addresses and pre-subtract operation for up to 512 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> + <bitfield name="ADDR0" high="7" low="0"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR0_CONST" high="8" low="8"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR0_REL" high="9" low="9"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="ADDR1" high="17" low="10"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR1_CONST" high="18" low="18"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR1_REL" high="19" low="19"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="ADDR2" high="27" low="20"> + <doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc> + </bitfield> + <bitfield name="ADDR2_CONST" high="28" low="28"> + <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> + <use-enum ref="ENUM267" /> + </bitfield> + <bitfield name="ADDR2_REL" high="29" low="29"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM268" /> + </bitfield> + <bitfield name="SRCP_OP" high="31" low="30"> + <doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> + <use-enum ref="ENUM174" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0xB800" stride="0x0004" length="512"> + <reg32 name="US_CMN_INST" access="rw" offset="0x0000"> + <doc>Shared instruction fields for all instruction types</doc> + <bitfield name="TYPE" high="1" low="0"> + <doc>Specifies the type of instruction. Note that output instructions write to render targets.</doc> + <value value="0" name="US_INST_TYPE_ALU"><doc>US_INST_TYPE_ALU: This instruction is an ALU instruction.</doc></value> + <value value="1" name="US_INST_TYPE_OUT"><doc>US_INST_TYPE_OUT: This instruction is an output instruction.</doc></value> + <value value="2" name="US_INST_TYPE_FC"><doc>US_INST_TYPE_FC: This instruction is a flow control instruction.</doc></value> + <value value="3" name="US_INST_TYPE_TEX"><doc>US_INST_TYPE_TEX: This instruction is a texture instruction.</doc></value> + </bitfield> + <bitfield name="TEX_SEM_WAIT" high="2" low="2"> + <doc>Specifies whether to wait for the texture semaphore.</doc> + <value value="0" name="THIS_INSTRUCTION_MAY_ISSUE_IMMEDIATELY"><doc>This instruction may issue immediately.</doc></value> + <value value="1" name="THIS_INSTRUCTION_WILL_NOT_ISSUE_UNTIL_THE_TEXTURE_SEMAPHORE_IS_AVAILABLE"><doc>This instruction will not issue until the texture semaphore is available.</doc></value> + </bitfield> + <bitfield name="RGB_PRED_SEL" high="5" low="3"> + <doc>Specifies whether the instruction uses predication. For ALU/TEX/Output this specifies predication for the RGB channels only. For FC this specifies the predicate for the entire instruction.</doc> + <value value="0" name="US_PRED_SEL_NONE"><doc>US_PRED_SEL_NONE: No predication</doc></value> + <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: Independent Channel Predication</doc></value> + <value value="2" name="US_PRED_SEL_RRRR"><doc>US_PRED_SEL_RRRR: R-Replicate Predication</doc></value> + <value value="3" name="US_PRED_SEL_GGGG"><doc>US_PRED_SEL_GGGG: G-Replicate Predication</doc></value> + <value value="4" name="US_PRED_SEL_BBBB"><doc>US_PRED_SEL_BBBB: B-Replicate Predication</doc></value> + <value value="5" name="US_PRED_SEL_AAAA"><doc>US_PRED_SEL_AAAA: A-Replicate Predication</doc></value> + </bitfield> + <bitfield name="RGB_PRED_INV" high="6" low="6"> + <doc>Specifies whether the predicate should be inverted. For ALU/TEX/Output this specifies predication for the RGB channels only. For FC this specifies the predicate for the entire instruction.</doc> + <use-enum ref="ENUM274" /> + </bitfield> + <bitfield name="WRITE_INACTIVE" high="7" low="7"> + <doc>Specifies which pixels to write to.</doc> + <value value="0" name="ONLY_WRITE_TO_CHANNELS_OF_ACTIVE_PIXELS"><doc>Only write to channels of active pixels</doc></value> + <value value="1" name="WRITE_TO_CHANNELS_OF_ALL_PIXELS"><doc>Write to channels of all pixels, including inactive pixels</doc></value> + </bitfield> + <bitfield name="LAST" high="8" low="8"> + <doc>Specifies whether this is the last instruction.</doc> + <value value="0" name="DO_NOT_TERMINATE_THE_SHADER_AFTER_EXECUTING_THIS_INSTRUCTION"><doc>Do not terminate the shader after executing this instruction (unless this instruction is at END_ADDR).</doc></value> + <value value="1" name="ALL_ACTIVE_PIXELS_ARE_WILLING_TO_TERMINATE_AFTER_EXECUTING_THIS_INSTRUCTION"><doc>All active pixels are willing to terminate after executing this instruction. There is no guarantee that the shader will actually terminate here. This feature is provided as a performance optimization for tests where pixels can conditionally terminate early.</doc></value> + </bitfield> + <bitfield name="NOP" high="9" low="9"> + <doc>Specifies whether to insert a NOP instruction after this. This would get specified in order to meet dependency requirements for the pre-subtract inputs, and dependency requirements for src0 of an MDH/MDV instruction.</doc> + <value value="0" name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE"><doc>Do not insert NOP instruction after this one.</doc></value> + <value value="1" name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE"><doc>Insert a NOP instruction after this one.</doc></value> + </bitfield> + <bitfield name="ALU_WAIT" high="10" low="10"> + <doc>Specifies whether to wait for pending ALU instructions to complete before issuing this instruction.</doc> + <value value="0" name="DO_NOT_WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION"><doc>Do not wait for pending ALU instructions to complete before issuing the current instruction.</doc></value> + <value value="1" name="WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION"><doc>Wait for pending ALU instructions to complete before issuing the current instruction.</doc></value> + </bitfield> + <bitfield name="RGB_WMASK" high="13" low="11"> + <doc>Specifies which components of the result of the RGB instruction are written to the pixel stack frame.</doc> + <use-enum ref="ENUM279" /> + </bitfield> + <bitfield name="ALPHA_WMASK" high="14" low="14"> + <doc>Specifies whether the result of the Alpha instruction is written to the pixel stack frame.</doc> + <value value="0" name="NONE"><doc>NONE: Do not write register.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only.</doc></value> + </bitfield> + <bitfield name="RGB_OMASK" high="17" low="15"> + <doc>Specifies which components of the result of the RGB instruction are written to the output fifo if this is an output instruction, and which predicate bits should be modified if this is an ALU instruction.</doc> + <use-enum ref="ENUM279" /> + </bitfield> + <bitfield name="ALPHA_OMASK" high="18" low="18"> + <doc>Specifies whether the result of the Alpha instruction is written to the output fifo if this is an output instruction, and whether the Alpha predicate bit should be modified if this is an ALU instruction.</doc> + <value value="0" name="NONE"><doc>NONE: Do not write output.</doc></value> + <value value="1" name="A"><doc>A: Write the alpha channel only.</doc></value> + </bitfield> + <bitfield name="RGB_CLAMP" high="19" low="19"> + <doc>Specifies RGB and Alpha clamp mode for this instruction.</doc> + <use-enum ref="ENUM171" /> + </bitfield> + <bitfield name="ALPHA_CLAMP" high="20" low="20"> + <doc>Specifies RGB and Alpha clamp mode for this instruction.</doc> + <use-enum ref="ENUM171" /> + </bitfield> + <bitfield name="ALU_RESULT_SEL" high="21" low="21"> + <doc>Specifies which component of the result of this instruction should be used as the `ALU result` by a subsequent flow control instruction.</doc> + <value value="0" name="RED"><doc>RED: Use red as ALU result for FC.</doc></value> + <value value="1" name="ALPHA"><doc>ALPHA: Use alpha as ALU result for FC.</doc></value> + </bitfield> + <bitfield name="ALPHA_PRED_INV" high="22" low="22"> + <doc>Specifies whether the predicate should be inverted. For ALU/TEX/Output this specifies predication for the alpha channel only. This field has no effect on FC instructions.</doc> + <use-enum ref="ENUM274" /> + </bitfield> + <bitfield name="ALU_RESULT_OP" high="24" low="23"> + <doc>Specifies how to compare the ALU result against zero for the `alu_result` bit in a subsequent flow control instruction.</doc> + <value value="0" name="EQUAL_TO"><doc>Equal to</doc></value> + <value value="1" name="LESS_THAN"><doc>Less than</doc></value> + <value value="2" name="GREATER_THAN_OR_EQUAL_TO"><doc>Greater than or equal to</doc></value> + <value value="3" name="NOT_EQUAL"><doc>Not equal</doc></value> + </bitfield> + <bitfield name="ALPHA_PRED_SEL" high="27" low="25"> + <doc>Specifies whether the instruction uses predication. For ALU/TEX/Output this specifies predication for the alpha channel only. This field has no effect on FC instructions.</doc> + <value value="0" name="US_PRED_SEL_NONE"><doc>US_PRED_SEL_NONE: No predication</doc></value> + <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: A predication (identical to US_PRED_SEL_AAAA)</doc></value> + <value value="2" name="US_PRED_SEL_RRRR"><doc>US_PRED_SEL_RRRR: R Predication</doc></value> + <value value="3" name="US_PRED_SEL_GGGG"><doc>US_PRED_SEL_GGGG: G Predication</doc></value> + <value value="4" name="US_PRED_SEL_BBBB"><doc>US_PRED_SEL_BBBB: B Predication</doc></value> + <value value="5" name="US_PRED_SEL_AAAA"><doc>US_PRED_SEL_AAAA: A Predication</doc></value> + </bitfield> + <bitfield name="STAT_WE" high="31" low="28"> + <doc>Specifies which components (R,G,B,A) contribute to the stat count</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_CODE_ADDR" access="rw" offset="0x4630"> + <doc>Code start and end instruction addresses.</doc> + <bitfield name="START_ADDR" high="8" low="0"> + <doc>Specifies the address of the first instruction to execute in the shader program. This address is relative to the shader program offset given in US_CODE_OFFSET.OFFSET_ADDR.</doc> + </bitfield> + <bitfield name="END_ADDR" high="24" low="16"> + <doc>Specifies the address of the last instruction to execute in the shader program. This address is relative to the shader program offset given in US_CODE_OFFSET.OFFSET_ADDR. Shader program execution will always terminate after the instruction at this address is executed.</doc> + </bitfield> + </reg32> + <reg32 name="US_CODE_OFFSET" access="rw" offset="0x4638"> + <doc>Offsets used for relative instruction addresses in the shader program, including START_ADDR, END_ADDR, and any non-global flow control jump addresses.</doc> + <bitfield name="OFFSET_ADDR" high="8" low="0"> + <doc>Specifies the offset to add to relative instruction addresses, including START_ADDR, END_ADDR, and some flow control jump addresses.</doc> + </bitfield> + </reg32> + <reg32 name="US_CODE_RANGE" access="rw" offset="0x4634"> + <doc>Range of instructions that contains the current shader program.</doc> + <bitfield name="CODE_ADDR" high="8" low="0"> + <doc>Specifies the start address of the current code window. This address is an absolute address.</doc> + </bitfield> + <bitfield name="CODE_SIZE" high="24" low="16"> + <doc>Specifies the size of the current code window, minus one. The last instruction in the code window is given by CODE_ADDR + CODE_SIZE.</doc> + </bitfield> + </reg32> + <reg32 name="US_CONFIG" access="rw" offset="0x4600"> + <doc>Shader Configuration</doc> + <bitfield name="Reserved" high="0" low="0"> + <doc>Set to 0</doc> + </bitfield> + <bitfield name="ZERO_TIMES_ANYTHING_EQUALS_ZERO" high="1" low="1"> + <doc>Control how ALU multiplier behaves when one argument is zero. This affects the multiplier used in MAD and dot product calculations.</doc> + <value value="0" name="DEFAULT_BEHAVIOUR"><doc>Default behaviour (0*inf=nan,0*nan=nan)</doc></value> + <value value="1" name="LEGACY_BEHAVIOUR_FOR_SHADER_MODEL_1"><doc>Legacy behaviour for shader model 1 (0*anything=0)</doc></value> + </bitfield> + </reg32> + <stripe offset="0xA000" stride="0x0004" length="512"> + <reg32 name="US_FC_ADDR" access="rw" offset="0x0000"> + <doc>Flow Control Instruction Address Fields</doc> + <bitfield name="BOOL_ADDR" high="4" low="0"> + <doc>The address of the static boolean register to use in the jump function.</doc> + </bitfield> + <bitfield name="INT_ADDR" high="12" low="8"> + <doc>The address of the static integer register to use for loop/rep and endloop/endrep.</doc> + </bitfield> + <bitfield name="JUMP_ADDR" high="24" low="16"> + <doc>The address to jump to if the jump function evaluates to true.</doc> + </bitfield> + <bitfield name="JUMP_GLOBAL" high="31" low="31"> + <doc>Specifies whether to interpret JUMP_ADDR as a global address.</doc> + <value value="0" name="ADD_THE_SHADER_PROGRAM_OFFSET_IN_US_CODE_OFFSET"><doc>Add the shader program offset in US_CODE_OFFSET.OFFSET_ADDR when calculating the destination address of a jump</doc></value> + <value value="1" name="DON"><doc>Don`t use the shader program offset when calculating the destination address jump</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_FC_BOOL_CONST" access="rw" offset="0x4620"> + <doc>Static Boolean Constants for Flow Control Branching Instructions. Quad-buffered.</doc> + </reg32> + <reg32 name="US_FC_CTRL" access="rw" offset="0x4624"> + <doc>Flow Control Options. Quad-buffered.</doc> + <bitfield name="TEST_EN" high="30" low="30"> + <doc>Specifies whether test mode is enabled. This flag currently has no effect in hardware.</doc> + <value value="0" name="NORMAL_MODE"><doc>Normal mode</doc></value> + <value value="1" name="TEST_MODE"><doc>Test mode (currently unused)</doc></value> + </bitfield> + <bitfield name="FULL_FC_EN" high="31" low="31"> + <doc>Specifies whether full flow control functionality is enabled.</doc> + <value value="0" name="USE_PARTIAL_FLOW"><doc>Use partial flow-control (enables twice the contexts). Loops and subroutines are not available in partial flow-control mode, and the nesting depth of branch statements is limited.</doc></value> + <value value="1" name="USE_FULL_PIXEL_SHADER_3"><doc>Use full pixel shader 3.0 flow control, including loops and subroutines.</doc></value> + </bitfield> + </reg32> + <stripe offset="0x9800" stride="0x0004" length="512"> + <reg32 name="US_FC_INST" access="rw" offset="0x0000"> + <doc>Flow Control Instruction</doc> + <bitfield name="OP" high="2" low="0"> + <doc>Specifies the type of flow control instruction.</doc> + <value value="0" name="US_FC_OP_JUMP"><doc>US_FC_OP_JUMP: (if, endif, call, etc)</doc></value> + <value value="1" name="US_FC_OP_LOOP"><doc>US_FC_OP_LOOP: same as jump except always take the jump if the static counter is 0. If we don`t take the jump, push initial loop counter and loop register (aL) values onto the loop stack.</doc></value> + <value value="2" name="US_FC_OP_ENDLOOP"><doc>US_FC_OP_ENDLOOP: same as jump but decrement the loop counter and increment the loop register (aL), and don`t take the jump if the loop counter becomes zero.</doc></value> + <value value="3" name="US_FC_OP_REP"><doc>US_FC_OP_REP: same as loop but don`t push the loop register aL.</doc></value> + <value value="4" name="US_FC_OP_ENDREP"><doc>US_FC_OP_ENDREP: same as endloop but don`t update/pop the loop register aL.</doc></value> + <value value="5" name="US_FC_OP_BREAKLOOP"><doc>US_FC_OP_BREAKLOOP: same as jump but pops the loop stacks if a pixel stops being active.</doc></value> + <value value="6" name="US_FC_OP_BREAKREP"><doc>US_FC_OP_BREAKREP: same as breakloop but don`t pop the loop register if it jumps.</doc></value> + <value value="7" name="US_FC_OP_CONTINUE"><doc>US_FC_OP_CONTINUE: used to disable pixels that are ready to jump to the ENDLOOP/ENDREP instruction.</doc></value> + </bitfield> + <bitfield name="B_ELSE" high="4" low="4"> + <doc>Specifies whether to perform an else operation on the active and branch-inactive pixels before executing the instruction.</doc> + <value value="0" name="DON"><doc>Don`t alter the branch state before executing the instruction.</doc></value> + <value value="1" name="PERFORM_AN_ELSE_OPERATION_ON_THE_BRANCH_STATE_BEFORE_EXECUTING_THE_INSTRUCTION"><doc>Perform an else operation on the branch state before executing the instruction; pixels in the active state are moved to the branch inactive state with zero counter, and vice versa.</doc></value> + </bitfield> + <bitfield name="JUMP_ANY" high="5" low="5"> + <doc>If set, jump if any active pixels want to take the jump (otherwise the instruction jumps only if all active pixels want to).</doc> + <value value="0" name="JUMP_IF_ALL_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ALL active pixels want to take the jump (for if and else). If no pixels are active, jump.</doc></value> + <value value="1" name="JUMP_IF_ANY_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ANY active pixels want to take the jump (for call, loop/rep and endrep/endloop). If no pixels are active, do not jump.</doc></value> + </bitfield> + <bitfield name="A_OP" high="7" low="6"> + <doc>The address stack operation to perform if we take the jump.</doc> + <value value="0" name="US_FC_A_OP_NONE"><doc>US_FC_A_OP_NONE: Don`t change the address stack</doc></value> + <value value="1" name="US_FC_A_OP_POP"><doc>US_FC_A_OP_POP: If we jump, pop the address stack and use that value for the jump target</doc></value> + <value value="2" name="US_FC_A_OP_PUSH"><doc>US_FC_A_OP_PUSH: If we jump, push the current address onto the address stack</doc></value> + </bitfield> + <bitfield name="JUMP_FUNC" high="15" low="8"> + <doc>A 2x2x2 table of boolean values indicating whether to take the jump. The table index is indexed by {ALU Compare Result, Predication Result, Boolean Value (from the static boolean address in US_FC_ADDR.BOOL)}. To determine whether to jump, look at bit ((alu_result<<2) | (predicate<<1) | bool).</doc> + </bitfield> + <bitfield name="B_POP_CNT" high="20" low="16"> + <doc>The amount to decrement the branch counter by if US_FC_B_OP_DECR operation is performed.</doc> + </bitfield> + <bitfield name="B_OP0" high="25" low="24"> + <doc>The branch state operation to perform if we don`t take the jump.</doc> + <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we don`t jump, don`t alter the branch counter for any pixel.</doc></value> + <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we don`t jump, decrement branch counter by B_POP_CNT for inactive pixels. Activate pixels with negative counters.</doc></value> + <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we don`t jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided to jump and set their counter to zero.</doc></value> + </bitfield> + <bitfield name="B_OP1" high="27" low="26"> + <doc>The branch state operation to perform if we do take the jump.</doc> + <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we do jump, don`t alter the branch counter for any pixel.</doc></value> + <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we do jump, decrement branch counter by B_POP_CNT for inactive pixels. Activate pixels with negative counters.</doc></value> + <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we do jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided not to jump and set their counter to zero.</doc></value> + </bitfield> + <bitfield name="IGNORE_UNCOVERED" high="28" low="28"> + <doc>If set, uncovered pixels will not participate in flow control decisions.</doc> + <value value="0" name="INCLUDE_UNCOVERED_PIXELS_IN_JUMP_DECISIONS"><doc>Include uncovered pixels in jump decisions</doc></value> + <value value="1" name="IGNORE_UNCOVERED_PIXELS_IN_MAKING_JUMP_DECISIONS"><doc>Ignore uncovered pixels in making jump decisions</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4C00" stride="0x0004" length="32"> + <reg32 name="US_FC_INT_CONST" access="rw" offset="0x0000"> + <doc>Integer Constants used by Flow Control Loop Instructions. Single buffered.</doc> + <bitfield name="KR" high="7" low="0"> + <doc>Specifies the number of iterations. Unsigned 8-bit integer in [0, 255].</doc> + </bitfield> + <bitfield name="KG" high="15" low="8"> + <doc>Specifies the initial value of the loop register (aL). Unsigned 8-bit integer in [0, 255].</doc> + </bitfield> + <bitfield name="KB" high="23" low="16"> + <doc>Specifies the increment used to change the loop register (aL) on each iteration. Signed 7-bit integer in [-128, 127].</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x4640" stride="0x0004" length="16"> + <reg32 name="US_FORMAT0" access="rw" offset="0x0000"> + <doc></doc> + <bitfield name="TXDEPTH" high="25" low="22"> + <doc></doc> + <value value="13" name="WIDTH"><doc>width > 2048, height <= 2048</doc></value> + <value value="14" name="WIDTH"><doc>width <= 2048, height > 2048</doc></value> + <value value="15" name="WIDTH"><doc>width > 2048, height > 2048</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x46A4" stride="0x0004" length="4"> + <reg32 name="US_OUT_FMT" access="rw" offset="0x0000"> + <doc></doc> + <bitfield name="OUT_FMT" high="4" low="0"> + <doc></doc> + <use-enum ref="ENUM179" /> + </bitfield> + <bitfield name="C0_SEL" high="9" low="8"> + <doc></doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C1_SEL" high="11" low="10"> + <doc></doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C2_SEL" high="13" low="12"> + <doc></doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="C3_SEL" high="15" low="14"> + <doc></doc> + <use-enum ref="ENUM180" /> + </bitfield> + <bitfield name="ROUND_ADJ" high="20" low="20"> + <doc></doc> + <value value="0" name="NORMAL_ROUNDING"><doc>Normal rounding</doc></value> + <value value="1" name="MODIFIED_ROUNDING_OF_FIXED"><doc>Modified rounding of fixed-point data</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_PIXSIZE" access="rw" offset="0x4604"> + <doc>Shader pixel size. This register specifies the size and partitioning of the current pixel stack frame</doc> + <bitfield name="PIX_SIZE" high="6" low="0"> + <doc>Specifies the total size of the current pixel stack frame (1:128)</doc> + </bitfield> + </reg32> + <stripe offset="0x9800" stride="0x0004" length="512"> + <reg32 name="US_TEX_ADDR" access="rw" offset="0x0000"> + <doc>Texture addresses and swizzles</doc> + <bitfield name="SRC_ADDR" high="6" low="0"> + <doc>Specifies the location (within the shader pixel stack frame) of the texture address for this instruction</doc> + </bitfield> + <bitfield name="SRC_ADDR_REL" high="7" low="7"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM298" /> + </bitfield> + <bitfield name="SRC_S_SWIZ" high="9" low="8"> + <doc>Specify which colour channel of src_addr to use for S coordinate</doc> + <use-enum ref="ENUM299" /> + </bitfield> + <bitfield name="SRC_T_SWIZ" high="11" low="10"> + <doc>Specify which colour channel of src_addr to use for T coordinate</doc> + <use-enum ref="ENUM300" /> + </bitfield> + <bitfield name="SRC_R_SWIZ" high="13" low="12"> + <doc>Specify which colour channel of src_addr to use for R coordinate</doc> + <use-enum ref="ENUM301" /> + </bitfield> + <bitfield name="SRC_Q_SWIZ" high="15" low="14"> + <doc>Specify which colour channel of src_addr to use for Q coordinate</doc> + <use-enum ref="ENUM302" /> + </bitfield> + <bitfield name="DST_ADDR" high="22" low="16"> + <doc>Specifies the location (within the shader pixel stack frame) of the returned texture data for this instruction</doc> + </bitfield> + <bitfield name="DST_ADDR_REL" high="23" low="23"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <value value="0" name="NONE"><doc>NONE: Do not modify destination address</doc></value> + <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL before lookup.</doc></value> + </bitfield> + <bitfield name="DST_R_SWIZ" high="25" low="24"> + <doc>Specify which colour channel of the returned texture data to write to the red channel of dst_addr</doc> + <value value="0" name="WRITE_R_CHANNEL_TO_R_CHANNEL"><doc>Write R channel to R channel</doc></value> + <value value="1" name="WRITE_G_CHANNEL_TO_R_CHANNEL"><doc>Write G channel to R channel</doc></value> + <value value="2" name="WRITE_B_CHANNEL_TO_R_CHANNEL"><doc>Write B channel to R channel</doc></value> + <value value="3" name="WRITE_A_CHANNEL_TO_R_CHANNEL"><doc>Write A channel to R channel</doc></value> + </bitfield> + <bitfield name="DST_G_SWIZ" high="27" low="26"> + <doc>Specify which colour channel of the returned texture data to write to the green channel of dst_addr</doc> + <value value="0" name="WRITE_R_CHANNEL_TO_G_CHANNEL"><doc>Write R channel to G channel</doc></value> + <value value="1" name="WRITE_G_CHANNEL_TO_G_CHANNEL"><doc>Write G channel to G channel</doc></value> + <value value="2" name="WRITE_B_CHANNEL_TO_G_CHANNEL"><doc>Write B channel to G channel</doc></value> + <value value="3" name="WRITE_A_CHANNEL_TO_G_CHANNEL"><doc>Write A channel to G channel</doc></value> + </bitfield> + <bitfield name="DST_B_SWIZ" high="29" low="28"> + <doc>Specify which colour channel of the returned texture data to write to the blue channel of dst_addr</doc> + <value value="0" name="WRITE_R_CHANNEL_TO_B_CHANNEL"><doc>Write R channel to B channel</doc></value> + <value value="1" name="WRITE_G_CHANNEL_TO_B_CHANNEL"><doc>Write G channel to B channel</doc></value> + <value value="2" name="WRITE_B_CHANNEL_TO_B_CHANNEL"><doc>Write B channel to B channel</doc></value> + <value value="3" name="WRITE_A_CHANNEL_TO_B_CHANNEL"><doc>Write A channel to B channel</doc></value> + </bitfield> + <bitfield name="DST_A_SWIZ" high="31" low="30"> + <doc>Specify which colour channel of the returned texture data to write to the alpha channel of dst_addr</doc> + <value value="0" name="WRITE_R_CHANNEL_TO_A_CHANNEL"><doc>Write R channel to A channel</doc></value> + <value value="1" name="WRITE_G_CHANNEL_TO_A_CHANNEL"><doc>Write G channel to A channel</doc></value> + <value value="2" name="WRITE_B_CHANNEL_TO_A_CHANNEL"><doc>Write B channel to A channel</doc></value> + <value value="3" name="WRITE_A_CHANNEL_TO_A_CHANNEL"><doc>Write A channel to A channel</doc></value> + </bitfield> + </reg32> + </stripe> + <stripe offset="0xA000" stride="0x0004" length="512"> + <reg32 name="US_TEX_ADDR_DXDY" access="rw" offset="0x0000"> + <doc>Additional texture addresses and swizzles for DX/DY inputs</doc> + <bitfield name="DX_ADDR" high="6" low="0"> + <doc>Specifies the location (within the shader pixel stack frame) of the DX value for this instruction</doc> + </bitfield> + <bitfield name="DX_ADDR_REL" high="7" low="7"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM298" /> + </bitfield> + <bitfield name="DX_S_SWIZ" high="9" low="8"> + <doc>Specify which colour channel of dx_addr to use for S coordinate</doc> + <use-enum ref="ENUM299" /> + </bitfield> + <bitfield name="DX_T_SWIZ" high="11" low="10"> + <doc>Specify which colour channel of dx_addr to use for T coordinate</doc> + <use-enum ref="ENUM300" /> + </bitfield> + <bitfield name="DX_R_SWIZ" high="13" low="12"> + <doc>Specify which colour channel of dx_addr to use for R coordinate</doc> + <use-enum ref="ENUM301" /> + </bitfield> + <bitfield name="DX_Q_SWIZ" high="15" low="14"> + <doc>Specify which colour channel of dx_addr to use for Q coordinate</doc> + <use-enum ref="ENUM302" /> + </bitfield> + <bitfield name="DY_ADDR" high="22" low="16"> + <doc>Specifies the location (within the shader pixel stack frame) of the DY value for this instruction</doc> + </bitfield> + <bitfield name="DY_ADDR_REL" high="23" low="23"> + <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> + <use-enum ref="ENUM298" /> + </bitfield> + <bitfield name="DY_S_SWIZ" high="25" low="24"> + <doc>Specify which colour channel of dy_addr to use for S coordinate</doc> + <use-enum ref="ENUM299" /> + </bitfield> + <bitfield name="DY_T_SWIZ" high="27" low="26"> + <doc>Specify which colour channel of dy_addr to use for T coordinate</doc> + <use-enum ref="ENUM300" /> + </bitfield> + <bitfield name="DY_R_SWIZ" high="29" low="28"> + <doc>Specify which colour channel of dy_addr to use for R coordinate</doc> + <use-enum ref="ENUM301" /> + </bitfield> + <bitfield name="DY_Q_SWIZ" high="31" low="30"> + <doc>Specify which colour channel of dy_addr to use for Q coordinate</doc> + <use-enum ref="ENUM302" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x9000" stride="0x0004" length="512"> + <reg32 name="US_TEX_INST" access="rw" offset="0x0000"> + <doc>Texture Instruction</doc> + <bitfield name="TEX_ID" high="19" low="16"> + <doc>Specifies the id of the texture map used for this instruction</doc> + </bitfield> + <bitfield name="INST" high="24" low="22"> + <doc>Specifies the operation taking place for this instruction</doc> + <value value="0" name="NOP"><doc>NOP: Do nothing</doc></value> + <value value="1" name="LD"><doc>LD: Do Texture Lookup (S,T,R)</doc></value> + <value value="2" name="TEXKILL"><doc>TEXKILL: Kill pixel if any component is < 0</doc></value> + <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc></value> + <value value="4" name="LODBIAS"><doc>LODBIAS: Do texture lookup with lod bias</doc></value> + <value value="5" name="LOD"><doc>LOD: Do texture lookup with explicit lod</doc></value> + <value value="6" name="DXDY"><doc>DXDY: Do texture lookup with lod calculated from DX and DY</doc></value> + </bitfield> + <bitfield name="TEX_SEM_ACQUIRE" high="25" low="25"> + <doc>Whether to hold the texture semaphore until the data is written to the temporary register.</doc> + <value value="0" name="DON"><doc>Don`t hold the texture semaphore</doc></value> + <value value="1" name="HOLD_THE_TEXTURE_SEMAPHORE_UNTIL_THE_DATA_IS_WRITTEN_TO_THE_TEMPORARY_REGISTER"><doc>Hold the texture semaphore until the data is written to the temporary register.</doc></value> + </bitfield> + <bitfield name="IGNORE_UNCOVERED" high="26" low="26"> + <doc>If set, US will not request data for pixels which are uncovered. Clear this bit for indirect texture lookups.</doc> + <value value="0" name="FETCH_TEXELS_FOR_UNCOVERED_PIXELS"><doc>Fetch texels for uncovered pixels</doc></value> + <value value="1" name="DON"><doc>Don`t fetch texels for uncovered pixels</doc></value> + </bitfield> + <bitfield name="UNSCALED" high="27" low="27"> + <doc>Whether to scale texture coordinates when sending them to the texture unit.</doc> + <value value="0" name="SCALE_THE_S"><doc>Scale the S, T, R texture coordinates from [0.0,1.0] to the dimensions of the target texture</doc></value> + <value value="1" name="USE_THE_UNSCALED_S"><doc>Use the unscaled S, T, R texture coordates.</doc></value> + </bitfield> + </reg32> + </stripe> + <reg32 name="US_W_FMT" access="rw" offset="0x46B4"> + <doc>Specifies the source and format for the Depth (W) value output by the shader</doc> + <bitfield name="W_FMT" high="1" low="0"> + <doc>Format for W</doc> + <value value="0" name="W"><doc>W</doc></value> + <value value="0" name="W_IS_ALWAYS_ZERO"><doc>W is always zero</doc></value> + <value value="1" name="W"><doc>W</doc></value> + <value value="24" name="24"><doc>24-bit fixed point</doc></value> + <value value="2" name="W24_FP"><doc>W24_FP - 24-bit floating point. The floating point values are a special format that preserve sorting order when values are compared as integers, allowing higher precision in W without additional logic in other blocks.</doc></value> + </bitfield> + <bitfield name="W_SRC" high="2" low="2"> + <doc>Source for W</doc> + <use-enum ref="ENUM183" /> + </bitfield> + </reg32> + <reg32 name="VAP_ALT_NUM_VERTICES" access="rw" offset="0x2088"> + <doc>Alternate Number of Vertices to allow > 16-bits of Vertex count</doc> + <bitfield name="NUM_VERTICES" high="23" low="0"> + <doc>24-bit vertex count for command packet. Used instead of bits 31:16 of VAP_VF_CNTL if VAP_VF_CNTL.USE_ALT_NUM_VERTS is set.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_CLIP_CNTL" access="rw" offset="0x221C"> + <doc>Control Bits for User Clip Planes and Clipping</doc> + <bitfield name="UCP_ENA_0" high="0" low="0"> + <doc>Enable User Clip Plane 0</doc> + </bitfield> + <bitfield name="UCP_ENA_1" high="1" low="1"> + <doc>Enable User Clip Plane 1</doc> + </bitfield> + <bitfield name="UCP_ENA_2" high="2" low="2"> + <doc>Enable User Clip Plane 2</doc> + </bitfield> + <bitfield name="UCP_ENA_3" high="3" low="3"> + <doc>Enable User Clip Plane 3</doc> + </bitfield> + <bitfield name="UCP_ENA_4" high="4" low="4"> + <doc>Enable User Clip Plane 4</doc> + </bitfield> + <bitfield name="UCP_ENA_5" high="5" low="5"> + <doc>Enable User Clip Plane 5</doc> + </bitfield> + <bitfield name="PS_UCP_MODE" high="15" low="14"> + <doc>0 = Cull using distance from center of point 1 = Cull using radius-based distance from center of point 2 = Cull using radius-based distance from center of point, Expand and Clip on intersection 3 = Always expand and clip as trifan</doc> + </bitfield> + <bitfield name="CLIP_DISABLE" high="16" low="16"> + <doc>Disables clip code generation and clipping process for TCL</doc> + </bitfield> + <bitfield name="UCP_CULL_ONLY_ENA" high="17" low="17"> + <doc>Cull Primitives against UCPS, but don`t clip</doc> + </bitfield> + <bitfield name="BOUNDARY_EDGE_FLAG_ENA" high="18" low="18"> + <doc>If set, boundary edges are highlighted, else they are not highlighted</doc> + </bitfield> + <bitfield name="COLOR2_IS_TEXTURE" high="20" low="20"> + <doc>If set, color2 is used as texture8 by GA (PS3.0 requirement)</doc> + </bitfield> + <bitfield name="COLOR3_IS_TEXTURE" high="21" low="21"> + <doc>If set, color3 is used as texture9 by GA (PS3.0 requirement)</doc> + </bitfield> + </reg32> + <reg32 name="VAP_CNTL" access="rw" offset="0x2080"> + <doc>Vertex Assembler/Processor Control Register</doc> + <bitfield name="PVS_NUM_SLOTS" high="3" low="0"> + <doc>Specifies the number of vertex slots to be used in the VAP PVS process. A slot represents a single vertex storage location1 across multiple engines (one vertex per engine). By decreasing the number of slots, there is more memory for each vertex, but less parallel processing. Similarly, by increasing the number of slots, there is less memory per vertex but more vertices being processed in parallel.</doc> + </bitfield> + <bitfield name="PVS_NUM_CNTLRS" high="7" low="4"> + <doc>Specifies the maximum number of controllers to be processing in parallel. In general should be set to max value of TBD. Can be changed for performance analysis.</doc> + </bitfield> + <bitfield name="PVS_NUM_FPUS" high="11" low="8"> + <doc>Specifies the number of Floating Point Units (Vector/Math Engines) to use when processing vertices.</doc> + </bitfield> + <bitfield name="VAP_NO_RENDER" high="17" low="17"> + <doc>If set, VAP will not process any draw commands (i.e. writes to VAP_VF_CNTL, the INDX and DATAPORT and Immediate mode writes are ignored.</doc> + </bitfield> + <bitfield name="VF_MAX_VTX_NUM" high="21" low="18"> + <doc>This field controls the number of vertices that the vertex fetcher manages for the TCL and Setup Vertex Storage memories (and therefore the number of vertices that can be re-used). This value should be set to 12 for most operation, This number may be modified for performance evaluation. The value is the maximum vertex number used which is one less than the number of vertices (i.e. a 12 means 13 vertices will be used)</doc> + </bitfield> + <bitfield name="DX_CLIP_SPACE_DEF" high="22" low="22"> + <doc>Clip space is defined as:</doc> + <use-enum ref="ENUM184" /> + </bitfield> + <bitfield name="TCL_STATE_OPTIMIZATION" high="23" low="23"> + <doc>If set, enables the TCL state optimization, and the new state is used only if there is a change in TCL state, between VF_CNTL (triggers)</doc> + </bitfield> + </reg32> + <reg32 name="VAP_CNTL_STATUS" access="rw" offset="0x2140"> + <doc>Vertex Assemblen/Processor Control Status</doc> + <bitfield name="VC_SWAP" high="1" low="0"> + <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB Default = 0</doc> + </bitfield> + <bitfield name="PVS_BYPASS" high="8" low="8"> + <doc>The TCL engine is logically or physically removed from the circuit.</doc> + </bitfield> + <bitfield name="PVS_BUSY" high="11" low="11"> + <doc>Transform/Clip/Light (TCL) Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="MAX_MPS" high="19" low="16"> + <doc>Maximum number of MPs fused for this chip. Read- only. For A11, fusemask is fixed to 1XXX. For A12, CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 000 => max_mps[3:0] = 1XXX => 8 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 001 => max_mps[3:0] = 0110 => 6 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 010 => max_mps[3:0] = 0101 => 5 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 011 => max_mps[3:0] = 0100 => 4 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 100 => max_mps[3:0] = 0011 => 3 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 101 => max_mps[3:0] = 0010 => 2 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 110 => max_mps[3:0] = 0001 => 1 MP CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 111 => max_mps[3:0] = 0000 => 0 MP Note that max_mps[3:0] = 0111 = 7 MPs is not available</doc> + </bitfield> + <bitfield name="VS_BUSY" high="24" low="24"> + <doc>Vertex Store is Busy. Read-only.</doc> + </bitfield> + <bitfield name="RCP_BUSY" high="25" low="25"> + <doc>Reciprocal Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VTE_BUSY" high="26" low="26"> + <doc>ViewPort Transform Engine is Busy. Read-only.</doc> + </bitfield> + <bitfield name="MIU_BUSY" high="27" low="27"> + <doc>Memory Interface Unit is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VC_BUSY" high="28" low="28"> + <doc>Vertex Cache is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VF_BUSY" high="29" low="29"> + <doc>Vertex Fetcher is Busy. Read-only.</doc> + </bitfield> + <bitfield name="REGPIPE_BUSY" high="30" low="30"> + <doc>Register Pipeline is Busy. Read-only.</doc> + </bitfield> + <bitfield name="VAP_BUSY" high="31" low="31"> + <doc>VAP Engine is Busy. Read-only.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_INDEX_OFFSET" access="rw" offset="0x208C"> + <doc>Offset Value added to index value in both Indexed and Auto-indexed modes. Disabled by setting to 0</doc> + <bitfield name="INDEX_OFFSET" high="24" low="0"> + <doc>25-bit signed 2`s comp offset value</doc> + </bitfield> + </reg32> + <stripe offset="0x2150" stride="0x0004" length="8"> + <reg32 name="VAP_PROG_STREAM_CNTL" access="rw" offset="0x0000"> + <doc>Programmable Stream Control Word 0</doc> + <bitfield name="DATA_TYPE_0" high="3" low="0"> + <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) 10 = FLOAT_8 (8 IEEE Floats) Sames as 2 FLOAT_4 but must use consecutive DST_VEC_LOC. Used to allow > 16 PSC for OGL path. 11 = FLT16_2 (1 DWORD with 2 16-bit floating point values (SE5M10 exp bias of 15, supports denormalized numbers)) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 12 = FLT16_4 (2 DWORDS with 4(2 per dword) 16-bit floating point values (SE5M10 exp bias of 15, supports denormalized numbers))) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) * These data types use the SIGNED and NORMALIZE flags described below.</doc> + </bitfield> + <bitfield name="SKIP_DWORDS_0" high="7" low="4"> + <doc>The number of DWORDS to skip (discard) after processing the current element.</doc> + </bitfield> + <bitfield name="DST_VEC_LOC_0" high="12" low="8"> + <doc>The vector address in the input memory to write this element</doc> + </bitfield> + <bitfield name="LAST_VEC_0" high="13" low="13"> + <doc>If set, indicates the last vector of the current vertex stream</doc> + </bitfield> + <bitfield name="SIGNED_0" high="14" low="14"> + <doc>Determines whether fixed point data types are unsigned (0) or 2`s complement signed (1) data types. See NORMALIZE for complete description of affect</doc> + </bitfield> + <bitfield name="NORMALIZE_0" high="15" low="15"> + <doc>Determines whether the fixed to floating point conversion will normalize the value (i.e. fixed point value is all fractional bits) or not (i.e. fixed point value is all integer bits). This table describes the fixed to float conversion results SIGNED NORMALIZE FLT RANGE 0 0 0.0 - (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 0.0 - 1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - 127.0) 1 1 -1.0 - 1.0 where n is the number of bits in the associated fixed point value For signed, normalize conversion, since the fixed point range is not evenly distributed around 0, there are 3 different methods supported by R300. See the VAP_PSC_SGN_NORM_CNTL description for details.</doc> + <use-enum ref="ENUM185" /> + </bitfield> + <bitfield name="DATA_TYPE_1" high="19" low="16"> + <doc>Similar to DATA_TYPE_0</doc> + </bitfield> + <bitfield name="SKIP_DWORDS_1" high="23" low="20"> + <doc>See SKIP_DWORDS_0</doc> + </bitfield> + <bitfield name="DST_VEC_LOC_1" high="28" low="24"> + <doc>See DST_VEC_LOC_0</doc> + </bitfield> + <bitfield name="LAST_VEC_1" high="29" low="29"> + <doc>See LAST_VEC_0</doc> + </bitfield> + <bitfield name="SIGNED_1" high="30" low="30"> + <doc>See SIGNED_0</doc> + </bitfield> + <bitfield name="NORMALIZE_1" high="31" low="31"> + <doc>See NORMALIZE_0</doc> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x2500" stride="0x0008" length="16"> + <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS_LW" access="rw" offset="0x0000"> + <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Lower Word Addresses Register 0</doc> + <bitfield name="PVS_FC_ACT_ADRS_0" high="15" low="0"> + <doc>This field defines the last PVS instruction to execute prior to the control flow redirection. JUMP - The last instruction executed prior to the jump LOOP - The last instruction executed prior to the loop (init loop counter/inc) JSR - The last instruction executed prior to the jump to the subroutine. (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> + <use-enum ref="ENUM313" /> + </bitfield> + <bitfield name="PVS_FC_LOOP_CNT_JMP_INST_0" high="31" low="16"> + <doc>This field has multiple definitions as follows: JUMP - The instruction address to jump to. LOOP - The loop count. *Note loop count of 0 must be replaced by a jump. JSR - The instruction address to jump to (first inst of subroutine). (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> + <use-enum ref="ENUM314" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x2504" stride="0x0008" length="16"> + <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS_UW" access="rw" offset="0x0000"> + <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Upper Word Addresses Register 0</doc> + <bitfield name="PVS_FC_LAST_INST_0" high="15" low="0"> + <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - The last instruction of the loop. JSR - The last instruction of the subroutine. (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> + <use-enum ref="ENUM313" /> + </bitfield> + <bitfield name="PVS_FC_RTN_INST_0" high="31" low="16"> + <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS + 1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1). (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> + <use-enum ref="ENUM314" /> + </bitfield> + </reg32> + </stripe> + <stripe offset="0x2290" stride="0x0004" length="16"> + <reg32 name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" access="rw" offset="0x0000"> + <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> + <bitfield name="PVS_FC_LOOP_INIT_VAL_0" high="7" low="0"> + <doc>This field stores the automatic loop index register init value. This is an 8-bit unsigned value 0-255. This field is only used if the corresponding control flow instruction is a loop.</doc> + </bitfield> + <bitfield name="PVS_FC_LOOP_STEP_VAL_0" high="15" low="8"> + <doc>This field stores the automatic loop index register step value. This is an 8-bit 2`s comp signed value -128-127. This field is only used if the corresponding control flow instruction is a loop.</doc> + </bitfield> + <bitfield name="PVS_FC_LOOP_REPEAT_NO_FLI_0" high="31" low="31"> + <doc>When this field is set, the automatic loop index register init value is not used at loop activation. The intial loop index is inherited from outer loop. The loop index register step value is used at the end of each loop iteration ; after loop completion, the outer loop index register is restored</doc> + </bitfield> + </reg32> + </stripe> + <reg32 name="VAP_TEX_TO_COLOR_CNTL" access="rw" offset="0x2218"> + <doc>For VS3.0 color2texture - flat shading on textures - limitation: only first 8 vectors can have clipping with wrap shortest or point sprite generated textures</doc> + </reg32> + <reg32 name="VAP_VF_CNTL" access="rw" offset="0x2084"> + <doc>Vertex Fetcher Control</doc> + <bitfield name="PRIM_TYPE" high="3" low="0"> + <doc>Primitive Type 0 : None (will not trigger Setup Engine to run) 1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 : Triangle Fan 6 : Triangle Strip 7 : Triangle with wFlags (aka, Rage128 `Type-2` triangles) * 8-11 : Unused 12 : Line Loop 13 : Quad List 14 : Quad Strip 15 : Polygon *Encoding 7 indicates whether a 16-bit word of wFlags is present in the stream of indices arriving when the VTX_AMODE is programmed as a `0`. The Setup Engine just steps over the wFlags word; ignoring it. 0 = Stream contains just indices, as: [ Index1, Index0] [ Index3, Index2] [ Index5, Index4 ] etc... 1 = Stream contains indices and wFlags: [ Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ wFlags, Index5 ] etc...</doc> + </bitfield> + <bitfield name="PRIM_WALK" high="5" low="4"> + <doc>Method of Passing Vertex Data. 0 : State-Based Vertex Data. (Vertex data and tokens embedded in command stream.) 1 = Indexes (Indices embedded in command stream; vertex data to be fetched from memory.) 2 = Vertex List (Vertex data to be fetched from memory.) 3 = Vertex Data (Vertex data embedded in command stream.)</doc> + </bitfield> + <bitfield name="RSVD_PREV_USED" high="10" low="6"> + <doc>Reserved bits</doc> + </bitfield> + <bitfield name="INDEX_SIZE" high="11" low="11"> + <doc>When set, vertex indices are 32-bits/indx, otherwise, 16- bits/indx.</doc> + </bitfield> + <bitfield name="VTX_REUSE_DIS" high="12" low="12"> + <doc>When set, vertex reuse is disabled. DO NOT SET unless PRIM_WALK is Indexes.</doc> + </bitfield> + <bitfield name="DUAL_INDEX_MODE" high="13" low="13"> + <doc>When set, the incoming index is treated as two separate indices. Bits 23-16 are used as the index for AOS 0 (These are 0 for 16-bit indices) Bits 15-0 are used as the index for AOS 1-15. This mode was added specifically for HOS usage</doc> + </bitfield> + <bitfield name="USE_ALT_NUM_VERTS" high="14" low="14"> + <doc>When set, the number of vertices in the command packet is taken from VAP_ALT_NUM_VERTICES register instead of bits 31:16 of VAP_VF_CNTL</doc> + </bitfield> + <bitfield name="NUM_VERTICES" high="31" low="16"> + <doc>Number of vertices in the command packet.</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VTX_NUM_ARRAYS" access="rw" offset="0x20C0"> + <doc>Vertex Array of Structures Control</doc> + <bitfield name="VTX_NUM_ARRAYS" high="4" low="0"> + <doc>The number of arrays required to represent the current vertex type. Each Array is described by the following three fields: VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> + </bitfield> + <bitfield name="VC_FORCE_PREFETCH" high="5" low="5"> + <doc>Force Vertex Data Pre-fetching. If this bit is set, then a 256-bit word will always be fetched, regardless of which dwords are needed. Typically useful when VAP_VF_CNTL.PRIM_WALK is set to Vertex List (Auto-incremented indices).</doc> + </bitfield> + <bitfield name="VC_DIS_CACHE_INVLD" high="6" low="6"> + <doc>If set, the vertex cache is not invalidated between draw packets. This allows vertex cache hits to occur from packet to packet. This must be set with caution with respect to multiple contexts in the driver.</doc> + </bitfield> + <bitfield name="AOS_0_FETCH_SIZE" high="16" low="16"> + <doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule size 1 = 256-bit granule size This allows the driver to program the fetch size based on DWORDS/VTX/AOS combined with AGP vs. LOC Memory. The general belief is that the granule size should always be 256-bits for LOC memory and AGP8X data, but should be 128-bit for AGP2X/4X data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc> + </bitfield> + <bitfield name="AOS_1_FETCH_SIZE" high="17" low="17"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_2_FETCH_SIZE" high="18" low="18"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_3_FETCH_SIZE" high="19" low="19"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_4_FETCH_SIZE" high="20" low="20"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_5_FETCH_SIZE" high="21" low="21"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_6_FETCH_SIZE" high="22" low="22"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_7_FETCH_SIZE" high="23" low="23"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_8_FETCH_SIZE" high="24" low="24"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_9_FETCH_SIZE" high="25" low="25"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_10_FETCH_SIZE" high="26" low="26"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_11_FETCH_SIZE" high="27" low="27"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_12_FETCH_SIZE" high="28" low="28"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_13_FETCH_SIZE" high="29" low="29"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_14_FETCH_SIZE" high="30" low="30"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + <bitfield name="AOS_15_FETCH_SIZE" high="31" low="31"> + <doc>See AOS_0_FETCH_SIZE</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VTX_STATE_CNTL" access="rw" offset="0x2180"> + <doc>VAP Vertex State Control Register</doc> + <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"> + <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"> + <doc>0 : Select Color 1 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"> + <doc>0 : Select Color 2 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"> + <doc>0 : Select Color 3 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"> + <doc>0 : Select Color 4 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"> + <doc>0 : Select Color 5 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"> + <doc>0 : Select Color 6 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"> + <doc>0 : Select Color 7 1 : Select User Color 0 2 : Select User Color 1 3 : Reserved</doc> + </bitfield> + <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"> + <doc>0 : User Color 0 State is NOT updated when User Color 0 is written. 1 : User Color 1 State IS updated when User Color 0 is written.</doc> + </bitfield> + <bitfield name="Reserved" high="18" low="18"> + <doc>Set to 0</doc> + </bitfield> + </reg32> + <stripe offset="0x2430" stride="0x0004" length="4"> + <reg32 name="VAP_VTX_ST_BLND_WT" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x232C" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_A" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x2328" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_B" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x2324" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_G" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x2470" stride="0x0004" length="8"> + <reg32 name="VAP_VTX_ST_CLR_PKD" access="w" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x2320" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_CLR_R" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <reg32 name="VAP_VTX_ST_DISC_FOG" access="rw" offset="0x2424"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_EDGE_FLAGS" access="rw" offset="0x245C"> + <doc>Data register</doc> + <bitfield name="DATA_REGISTER" high="0" low="0"> + <doc>EDGE_FLAGS</doc> + </bitfield> + </reg32> + <reg32 name="VAP_VTX_ST_END_OF_PKT" access="w" offset="0x24AC"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_0_PKD" access="w" offset="0x2498"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_0_X" access="rw" offset="0x2310"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_0_Y" access="rw" offset="0x2314"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_0_Z" access="rw" offset="0x2318"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_1_X" access="rw" offset="0x2450"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_1_Y" access="rw" offset="0x2454"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_NORM_1_Z" access="rw" offset="0x2458"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_PNT_SPRT_SZ" access="rw" offset="0x2420"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_W_4" access="rw" offset="0x230C"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_X_2" access="w" offset="0x2490"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_X_3" access="w" offset="0x24A0"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_X_4" access="rw" offset="0x2300"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_Y_2" access="w" offset="0x2494"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_Y_3" access="w" offset="0x24A4"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_Y_4" access="rw" offset="0x2304"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_Z_3" access="w" offset="0x24A8"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_0_Z_4" access="rw" offset="0x2308"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_1_W" access="rw" offset="0x244C"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_1_X" access="rw" offset="0x2440"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_1_Y" access="rw" offset="0x2444"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_POS_1_Z" access="rw" offset="0x2448"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_PVMS" access="rw" offset="0x231C"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_SHININESS_0" access="rw" offset="0x2428"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_SHININESS_1" access="rw" offset="0x242C"> + <doc>Data register</doc> + </reg32> + <stripe offset="0x23AC" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_Q" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x23A8" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_R" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x23A0" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_S" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe offset="0x23A4" stride="0x0010" length="8"> + <reg32 name="VAP_VTX_ST_TEX_T" access="rw" offset="0x0000"> + <doc>Data register</doc> + </reg32> + </stripe> + <reg32 name="VAP_VTX_ST_USR_CLR_A" access="rw" offset="0x246C"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_USR_CLR_B" access="rw" offset="0x2468"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_USR_CLR_G" access="rw" offset="0x2464"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_USR_CLR_PKD" access="w" offset="0x249C"> + <doc>Data register</doc> + </reg32> + <reg32 name="VAP_VTX_ST_USR_CLR_R" access="rw" offset="0x2460"> + <doc>Data register</doc> + </reg32> + <reg32 name="ZB_BW_CNTL" access="rw" offset="0x4F1C"> + <doc>Z Buffer Band-Width Control Defa</doc> + <bitfield name="HIZ_ENABLE" high="0" low="0"> + <doc>Enables hierarchical Z.</doc> + <use-enum ref="ENUM187" /> + </bitfield> + <bitfield name="HIZ_MIN" high="1" low="1"> + <doc></doc> + <use-enum ref="ENUM188" /> + </bitfield> + <bitfield name="FAST_FILL" high="2" low="2"> + <doc></doc> + <use-enum ref="ENUM189" /> + </bitfield> + <bitfield name="RD_COMP_ENABLE" high="3" low="3"> + <doc>Enables reading of compressed Z data from memory to the cache.</doc> + <use-enum ref="ENUM190" /> + </bitfield> + <bitfield name="WR_COMP_ENABLE" high="4" low="4"> + <doc>Enables writing of compressed Z data from cache to memory,</doc> + <use-enum ref="ENUM191" /> + </bitfield> + <bitfield name="ZB_CB_CLEAR" high="5" low="5"> + <doc>This bit is set when the Z buffer is used to help the CB in clearing a region. Part of the region is cleared by the color buffer and part will be cleared by the Z buffer. Since the Z buffer does not have any write masks in the cache, full micro- tiles need to be written. If a partial micro-tile is touched, then the un-touched part will be unknowns. The cache will operate in write-allocate mode and quads will be accumulated in the cache and then evicted to main memory. The color value is supplied through the ZB_DEPTHCLEARVALUE register.</doc> + <use-enum ref="ENUM192" /> + </bitfield> + <bitfield name="FORCE_COMPRESSED_STENCIL_V" high="6" low="6"> + <doc>Enabling this bit will force all the compressed stencil values</doc> + </bitfield> + <bitfield name="ZEQUAL_OPTIMIZE_DISABLE" high="7" low="7"> + <doc>By default this is 0 (enabled). When NEWZ=OLDZ, then writes do not occur to save BW.</doc> + <value value="0" name="ENABLE_NOT_UPDATING_THE_Z_BUFFER_IF_NEWZ"><doc>Enable not updating the Z buffer if NewZ=OldZ</doc></value> + <value value="1" name="DISABLE_ABOVE_FEATURE"><doc>Disable above feature (in case there is a bug)</doc></value> + </bitfield> + <bitfield name="SEQUAL_OPTIMIZE_DISABLE" high="8" low="8"> + <doc>By default this is 0 (enabled). When NEW_STENCIL=OLD_STENCIL, then writes do not occur to save BW.</doc> + <value value="0" name="ENABLE_NOT_UPDATING_THE_STENCIL_BUFFER_IF_NEWS"><doc>Enable not updating the Stencil buffer if NewS=OldS</doc></value> + <value value="1" name="DISABLE_ABOVE_FEATURE"><doc>Disable above feature (in case there is a bug)</doc></value> + </bitfield> + <bitfield name="BMASK_DISABLE" high="10" low="10"> + <doc>Controls whether bytemasking is used or not.</doc> + <value value="0" name="ENABLE_BYTEMASKING"><doc>Enable bytemasking</doc></value> + <value value="1" name="DISABLE_BYTEMASKING"><doc>Disable bytemasking</doc></value> + </bitfield> + <bitfield name="HIZ_EQUAL_REJECT_ENABLE" high="11" low="11"> + <doc>Enables hiz rejects when the z function is equals.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="HIZ_FP_INVERT" high="15" low="15"> + <doc>Determines whether leading zeros or ones are eliminated.</doc> + <value value="0" name="COUNT_LEADING_1S"><doc>Count leading 1s</doc></value> + <value value="1" name="COUNT_LEADING_0S"><doc>Count leading 0s</doc></value> + </bitfield> + <bitfield name="TILE_OVERWRITE_RECOMPRESSI" high="16" low="16"> + <doc>The zb tries to detect single plane equations that completely</doc> + </bitfield> + <bitfield name="CONTIGUOUS_6XAA_SAMPLES_DI" high="17" low="17"> + <doc>This disables storing samples contiguously in 6xaa.</doc> + </bitfield> + <bitfield name="PEQ_PACKING_ENABLE" high="18" low="18"> + <doc>Enables packing of the plane equations to eliminate wasted peq slots.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="COVERED_PTR_MASKING_ENABL" high="19" low="19"> + <doc>Enables discarding of pointers from pixels that are going to be</doc> + </bitfield> + </reg32> + <reg32 name="ZB_CNTL" access="rw" offset="0x4F00"> + <doc>Z Buffer Control</doc> + <bitfield name="STENCIL_ENABLE" high="0" low="0"> + <doc>Enables stenciling.</doc> + <use-enum ref="ENUM178" /> + </bitfield> + <bitfield name="Z_ENABLE" high="1" low="1"> + <doc>Enables Z functions.</doc> + <use-enum ref="ENUM178" /> + </bitfield> + <bitfield name="ZWRITEENABLE" high="2" low="2"> + <doc>Enables writing of the Z buffer.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="ZSIGNED_COMPARE" high="3" low="3"> + <doc>Enable signed Z buffer comparison , for W-buffering.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="STENCIL_FRONT_BACK" high="4" low="4"> + <doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK bit to one specifies that stencilfunc/stencilfail/stencilzpass/stencilzfail registers are used if the quad is generated from front faced primitive and stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf are used if the quad is generated from a back faced primitive. If the STENCIL_FRONT_BACK is not set, then stencilfunc/stencilfail/stencilzpass/stencilzfail registers determine the operation independent of the front/back face state of the quad.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + <bitfield name="ZSIGNED_MAGNITUDE" high="5" low="5"> + <doc>Specifies the signed number type to use for the Z buffer comparison. This only has an effect when ZSIGNED_COMPARE is enabled.</doc> + <value value="0" name="TWOS_COMPLEMENT"><doc>Twos complement</doc></value> + <value value="1" name="SIGNED_MAGNITUDE"><doc>Signed magnitude</doc></value> + </bitfield> + <bitfield name="STENCIL_REFMASK_FRONT_BACK" high="6" low="6"> + <doc></doc> + <use-enum ref="ENUM5" /> + </bitfield> + </reg32> + <reg32 name="ZB_FIFO_SIZE" access="rw" offset="0x4FD0"> + <doc>Sets the fifo sizes</doc> + <bitfield name="OP_FIFO_SIZE" high="1" low="0"> + <doc>Determines the size of the op fifo</doc> + <use-enum ref="ENUM216" /> + </bitfield> + </reg32> + <reg32 name="ZB_FORMAT" access="rw" offset="0x4F10"> + <doc>Format of the Data in the Z buffer</doc> + <bitfield name="DEPTHFORMAT" high="3" low="0"> + <doc>Specifies the format of the Z buffer.</doc> + <use-enum ref="ENUM196" /> + </bitfield> + <bitfield name="INVERT" high="4" low="4"> + <doc></doc> + <value value="0" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 1`s</doc></value> + <value value="1" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 0`s.</doc></value> + </bitfield> + <bitfield name="PEQ8" high="5" low="5"> + <doc>This bit is unused</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_OFFSET" access="rw" offset="0x4F44"> + <doc>Hierarchical Z Memory Offset</doc> + <bitfield name="HIZ_OFFSET" high="17" low="2"> + <doc>DWORD offset into HiZ RAM.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_RDINDEX" access="rw" offset="0x4F50"> + <doc>Hierarchical Z Read Index</doc> + <bitfield name="HIZ_RDINDEX" high="17" low="2"> + <doc>Read index into HiZ RAM.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_HIZ_WRINDEX" access="rw" offset="0x4F48"> + <doc>Hierarchical Z Write Index</doc> + <bitfield name="HIZ_WRINDEX" high="17" low="2"> + <doc>Self-incrementing write index into the HiZ RAM. Starting write index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is written, this index will autoincrement. HIZ_OFFSET and HIZ_PITCH are not used to compute read/write address to HIZ ram, when it is accessed through WRINDEX and DWORD</doc> + </bitfield> + </reg32> + <reg32 name="ZB_STENCILREFMASK_BF" access="rw" offset="0x4FD4"> + <doc>Stencil Reference Value and Mask for backfacing quads</doc> + <bitfield name="STENCILREF" high="7" low="0"> + <doc>Specifies the reference stencil value.</doc> + </bitfield> + <bitfield name="STENCILMASK" high="15" low="8"> + <doc>This value is ANDed with both the reference and the current stencil value prior to the stencil test.</doc> + </bitfield> + <bitfield name="STENCILWRITEMASK" high="23" low="16"> + <doc>Specifies the write mask for the stencil planes.</doc> + </bitfield> + </reg32> + <reg32 name="ZB_ZSTENCILCNTL" access="rw" offset="0x4F04"> + <doc>Z and Stencil Function Control</doc> + <bitfield name="ZFUNC" high="2" low="0"> + <doc>Specifies the Z function.</doc> + <use-enum ref="ENUM202" /> + </bitfield> + <bitfield name="STENCILFUNC" high="5" low="3"> + <doc>Specifies the stencil function.</doc> + <use-enum ref="ENUM203" /> + </bitfield> + <bitfield name="STENCILFAIL" high="8" low="6"> + <doc>Specifies the stencil value to be written if the stencil test fails.</doc> + <use-enum ref="ENUM204" /> + </bitfield> + <bitfield name="STENCILZPASS" high="11" low="9"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled).</doc> + </bitfield> + <bitfield name="STENCILZFAIL" high="14" low="12"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails.</doc> + </bitfield> + <bitfield name="STENCILFUNC_BF" high="17" low="15"> + <doc>Same encoding as STENCILFUNC. Specifies the stencil function for back faced quads , if STENCIL_FRONT_BACK = 1.</doc> + </bitfield> + <bitfield name="STENCILFAIL_BF" high="20" low="18"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test fails for back faced quads, if STENCIL_FRONT_BACK = 1</doc> + </bitfield> + <bitfield name="STENCILZPASS_BF" high="23" low="21"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled) for back faced quads, if STENCIL_FRONT_BACK = 1</doc> + </bitfield> + <bitfield name="STENCILZFAIL_BF" high="26" low="24"> + <doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails for back faced quads, if STENCIL_FRONT_BACK =1</doc> + </bitfield> + <bitfield name="ZERO_OUTPUT_MASK" high="27" low="27"> + <doc>Zeroes the zb coverage mask output. This does not affect the updating of the depth or stencil values.</doc> + <use-enum ref="ENUM5" /> + </bitfield> + </reg32> +</group> + +<variant id="r300"> + <use-group ref="rX00_regs" /> + <use-group ref="r300_regs" /> +</variant> +<variant id="r500"> + <use-group ref="rX00_regs" /> + <use-group ref="r500_regs" /> +</variant> +</database> |