i965/skl: Emit new 3DSTATE_VF_COMPONENT_PACKINGvf_comp_pack

This turns on packing as a no-op (all components get stored).

NOTE: It's tempting to put this change into the logic which reorders the edge
flag, however that has potential to drop SGVs.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

3 files changed, 74 insertions, 4 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e7d1a9f791..43ead60eef 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1983,6 +1983,7 @@ enum brw_message_target {
 # define GEN6_URB_GS_SIZE_SHIFT				0
 
 #define _3DSTATE_VF                             0x780c /* GEN7.5+ */
+#define SKL_COMPONENT_PACKING_ENABLE                    (1 << 9)
 #define HSW_CUT_INDEX_ENABLE                            (1 << 8)
 
 #define _3DSTATE_VF_INSTANCING                  0x7849 /* GEN8+ */
@@ -1998,6 +1999,8 @@ enum brw_message_target {
 
 #define _3DSTATE_VF_TOPOLOGY                    0x784b /* GEN8+ */
 
+#define _3DSTATE_VF_COMPONENT_PACKING           0x7855 /* GEN9+ */
+
 #define _3DSTATE_WM_CHROMAKEY			0x784c /* GEN8+ */
 
 #define _3DSTATE_URB_VS                         0x7830 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index e329cc73b7..2010c0539e 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -190,6 +190,9 @@ haswell_upload_cut_index(struct brw_context *brw)
    const unsigned cut_index_setting =
       ctx->Array._PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
 
+   const unsigned packing =
+      brw->vb.nr_enabled ? SKL_COMPONENT_PACKING_ENABLE : 0;
+
    /* BRW_NEW_INDEX_BUFFER */
    unsigned cut_index;
    if (brw->ib.ib) {
@@ -204,7 +207,7 @@ haswell_upload_cut_index(struct brw_context *brw)
    }
 
    BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | (2 - 2));
+   OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | packing | (2 - 2));
    OUT_BATCH(cut_index);
    ADVANCE_BATCH();
 }
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index cda212f7f4..3dea14f5a9 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -48,6 +48,23 @@ is_passthru_format(uint32_t format)
    }
 }
 
+#define VERTEX_ELEMENT_ENABLE_NONE  0
+#define VERTEX_ELEMENT_ENABLE_X     1
+#define VERTEX_ELEMENT_ENABLE_Y     2
+#define VERTEX_ELEMENT_ENABLE_XY    3
+#define VERTEX_ELEMENT_ENABLE_Z     4
+#define VERTEX_ELEMENT_ENABLE_XZ    5
+#define VERTEX_ELEMENT_ENABLE_YZ    6
+#define VERTEX_ELEMENT_ENABLE_XYZ   7
+#define VERTEX_ELEMENT_ENABLE_W     8
+#define VERTEX_ELEMENT_ENABLE_XW    9
+#define VERTEX_ELEMENT_ENABLE_YW    10
+#define VERTEX_ELEMENT_ENABLE_XYW   11
+#define VERTEX_ELEMENT_ENABLE_ZW    12
+#define VERTEX_ELEMENT_ENABLE_XZW   13
+#define VERTEX_ELEMENT_ENABLE_YZW   14
+#define VERTEX_ELEMENT_ENABLE_XYZW  15
+
 static void
 gen8_emit_vertices(struct brw_context *brw)
 {
@@ -63,6 +80,11 @@ gen8_emit_vertices(struct brw_context *brw)
    const bool needs_sgvs = brw->vs.prog_data->uses_instanceid ||
                            brw->vs.prog_data->uses_vertexid;
 
+   uint32_t component_packing_enables[4] = {0};
+#define set_packing(element, val) do  { \
+   component_packing_enables[(element) / 8] |= (val) << (4 * ((element) % 8)); \
+} while (0)
+
 
    if (needs_sgvs) {
       unsigned vue = brw->vb.nr_enabled;
@@ -79,6 +101,8 @@ gen8_emit_vertices(struct brw_context *brw)
                 "Trying to insert VID/IID past 33rd vertex element, "
                 "need to reorder the vertex attrbutes.");
 
+      set_packing(vue, VERTEX_ELEMENT_ENABLE_XYZW);
+
       unsigned dw1 = 0;
       if (brw->vs.prog_data->uses_vertexid) {
          dw1 |= GEN8_SGVS_ENABLE_VERTEX_ID |
@@ -128,7 +152,9 @@ gen8_emit_vertices(struct brw_context *brw)
                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
       ADVANCE_BATCH();
-      return;
+
+      set_packing(0, VERTEX_ELEMENT_ENABLE_XYZW);
+      goto out;
    }
 
    /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
@@ -200,8 +226,8 @@ gen8_emit_vertices(struct brw_context *brw)
 
    BEGIN_BATCH(1 + nr_elements * 2);
    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
-   unsigned ve;
-   for (ve = 0; ve < brw->vb.nr_enabled; ve++) {
+   unsigned ve = 0;
+   for (; ve < brw->vb.nr_enabled; ve++) {
       struct brw_vertex_element *input = brw->vb.enabled[ve];
       uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
@@ -215,6 +241,11 @@ gen8_emit_vertices(struct brw_context *brw)
        */
       assert(!(is_passthru_format(format) && uses_edge_flag));
 
+      /* The VE with edge flag doesn't get packed. Additionally, the VE with
+       * edge flag must be the last VE.
+       */
+      set_packing(ve, VERTEX_ELEMENT_ENABLE_XYZW);
+
       /* The gen4 driver expects edgeflag to come in as a float, and passes
        * that float on to the tests in the clipper.  Mesa's current vertex
        * attribute value for EdgeFlag is stored as a float, which works out.
@@ -285,6 +316,9 @@ gen8_emit_vertices(struct brw_context *brw)
                 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
    }
 
+   if (gen6_edgeflag_input)
+      ve--;
+
    if (needs_sgvs_element) {
       if (brw->vs.prog_data->uses_basevertex ||
           brw->vs.prog_data->uses_baseinstance) {
@@ -295,12 +329,17 @@ gen8_emit_vertices(struct brw_context *brw)
                    (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
+
+         set_packing(ve, VERTEX_ELEMENT_ENABLE_XYZW);
+         ve++;
       } else {
          OUT_BATCH(GEN6_VE0_VALID);
          OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
+         set_packing(ve, VERTEX_ELEMENT_ENABLE_XYZW);
+         ve++;
       }
    }
 
@@ -312,6 +351,9 @@ gen8_emit_vertices(struct brw_context *brw)
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
+
+      set_packing(ve, VERTEX_ELEMENT_ENABLE_XYZW);
+      ve++;
    }
 
    if (gen6_edgeflag_input) {
@@ -360,6 +402,28 @@ gen8_emit_vertices(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
+
+#undef set_packing
+
+out:
+   if (brw->gen >= 9) {
+      /* From Instruction] 3DSTATE_VF_COMPONENT_PACKING:
+       *   "At least one component of one "valid" Vertex Element must be
+       *   enabled."
+       */
+      assert(component_packing_enables[0] ||
+             component_packing_enables[1] ||
+             component_packing_enables[2] ||
+             component_packing_enables[3]);
+
+      BEGIN_BATCH(5);
+      OUT_BATCH(_3DSTATE_VF_COMPONENT_PACKING << 16 | (5 - 2));
+      OUT_BATCH(component_packing_enables[0]);
+      OUT_BATCH(component_packing_enables[1]);
+      OUT_BATCH(component_packing_enables[2]);
+      OUT_BATCH(component_packing_enables[3]);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state gen8_vertices = {