diff options
| author | Ben Widawsky <ben@bwidawsk.net> | 2016-04-21 20:14:58 -0700 |
|---|---|---|
| committer | Ben Widawsky <ben@bwidawsk.net> | 2017-01-03 15:09:10 -0800 |
| commit | 052d476968c8c59790c3110c3681b905600d4019 (patch) | |
| tree | d8ffb35c87077ac9fda3615d9665d30d75f0d401 | |
| parent | abcaba497d8c90a1e9dcede71261bdee16e2ed4e (diff) | |
HACK: i965: Always use Y-tiled buffers on SKL+for-janesma
Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.
Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.
This has an almost universal positive impact on benchmarks, some improving by as
much as 20%.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index d0e3ac6875..2c28ca7f14 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -546,11 +546,16 @@ intel_create_image(__DRIscreen *dri_screen, { __DRIimage *image; struct intel_screen *screen = dri_screen->driverPrivate; + const struct gen_device_info *devinfo = &screen->devinfo; uint32_t tiling; int cpp; unsigned long pitch; - tiling = I915_TILING_X; + if (devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } if (use & __DRI_IMAGE_USE_CURSOR) { if (width != 64 || height != 64) return NULL; @@ -1206,11 +1211,18 @@ intel_init_bufmgr(struct intel_screen *screen) static bool intel_detect_swizzling(struct intel_screen *screen) { + const struct gen_device_info *devinfo = &screen->devinfo; drm_intel_bo *buffer; unsigned long flags = 0; unsigned long aligned_pitch; - uint32_t tiling = I915_TILING_X; uint32_t swizzle_mode = 0; + uint32_t tiling; + + if (devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test", 64, 64, 4, @@ -1716,6 +1728,7 @@ intelAllocateBuffer(__DRIscreen *dri_screen, { struct intel_buffer *intelBuffer; struct intel_screen *screen = dri_screen->driverPrivate; + const struct gen_device_info *devinfo = &screen->devinfo; assert(attachment == __DRI_BUFFER_FRONT_LEFT || attachment == __DRI_BUFFER_BACK_LEFT); @@ -1725,7 +1738,12 @@ intelAllocateBuffer(__DRIscreen *dri_screen, return NULL; /* The front and back buffers are color buffers, which are X tiled. */ - uint32_t tiling = I915_TILING_X; + uint32_t tiling; + if (devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } unsigned long pitch; int cpp = format / 8; intelBuffer->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, |