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authorChris Wilson <chris@chris-wilson.co.uk>2011-02-01 13:35:36 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2011-02-01 13:37:04 +0000
commit3c5c8ba71c4c32dcac1cf0493210d21fc9b33c8a (patch)
treead650b0f236e822c221049ff3d43d76cdb87bc87 /tools
parentc1e9795050b1e4b76c7f9acd3cc5071f0ecb06ed (diff)
Search for the first Intel dri device.
This is vital in a multi-GPU system so that we only test the Intel card and not the discrete GPUs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tools')
-rw-r--r--tools/intel_audio_dump.c2
-rw-r--r--tools/intel_decode.c8
-rw-r--r--tools/intel_disable_clock_gating.c2
-rw-r--r--tools/intel_gpu_top.c2
-rw-r--r--tools/intel_gtt.c2
5 files changed, 8 insertions, 8 deletions
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index fc8af442..ef81b6a6 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -1197,7 +1197,7 @@ int main(int argc, char **argv)
if (HAS_PCH_SPLIT(devid) || getenv("HAS_PCH_SPLIT")) {
intel_check_pch();
dump_cpt();
- } else if (IS_IRONLAKE(devid))
+ } else if (IS_GEN5(devid))
dump_ironlake();
else
dump_eaglelake();
diff --git a/tools/intel_decode.c b/tools/intel_decode.c
index 2c414a1e..971473fa 100644
--- a/tools/intel_decode.c
+++ b/tools/intel_decode.c
@@ -1644,7 +1644,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
case 0x6101:
if (IS_GEN6(devid))
sba_len = 10;
- else if (IS_IRONLAKE(devid))
+ else if (IS_GEN5(devid))
sba_len = 8;
else
sba_len = 6;
@@ -1663,14 +1663,14 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
if (IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "dynamic");
state_base_out(data, hw_offset, i++, "indirect");
- if (IS_IRONLAKE(devid) || IS_GEN6(devid))
+ if (IS_GEN5(devid) || IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "instruction");
state_max_out(data, hw_offset, i++, "general");
if (IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "dynamic");
state_max_out(data, hw_offset, i++, "indirect");
- if (IS_IRONLAKE(devid) || IS_GEN6(devid))
+ if (IS_GEN5(devid) || IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "instruction");
return len;
@@ -2071,7 +2071,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
instr_out(data, hw_offset, 0,
"3DSTATE_DEPTH_BUFFER\n");
- if (IS_IRONLAKE(devid) || IS_GEN6(devid))
+ if (IS_GEN5(devid) || IS_GEN6(devid))
instr_out(data, hw_offset, 1, "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
get_965_surfacetype(data[1] >> 29),
get_965_depthformat((data[1] >> 18) & 0x7),
diff --git a/tools/intel_disable_clock_gating.c b/tools/intel_disable_clock_gating.c
index e702fa6e..9b802de1 100644
--- a/tools/intel_disable_clock_gating.c
+++ b/tools/intel_disable_clock_gating.c
@@ -40,7 +40,7 @@ int main(int argc, char** argv)
pci_dev = intel_get_pci_device();
intel_get_mmio(pci_dev);
- if (IS_IRONLAKE(pci_dev->device_id)) {
+ if (IS_GEN5(pci_dev->device_id)) {
printf("Restore method:\n");
printf("intel_reg_write 0x%x 0x%08x\n",
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 19fa0e94..e9fbf43d 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -409,7 +409,7 @@ int main(int argc, char **argv)
}
ring_init(&render_ring);
- if (IS_GEN4(devid) || IS_IRONLAKE(devid))
+ if (IS_GEN4(devid) || IS_GEN5(devid))
ring_init(&bsd_ring);
if (IS_GEN6(devid)) {
ring_init(&bsd6_ring);
diff --git a/tools/intel_gtt.c b/tools/intel_gtt.c
index 2c1639cd..bc6d222d 100644
--- a/tools/intel_gtt.c
+++ b/tools/intel_gtt.c
@@ -56,7 +56,7 @@ int main(int argc, char **argv)
exit(1);
}
- if (IS_G4X(devid) || IS_IRONLAKE(devid))
+ if (IS_G4X(devid) || IS_GEN5(devid))
gtt = ((unsigned char *)mmio + MB(2));
else if (IS_965(devid))
gtt = ((unsigned char *)mmio + KB(512));