diff options
| author | Chon Ming Lee <chon.ming.lee@intel.com> | 2013-12-04 20:44:33 +0800 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-12-05 13:04:36 +0200 |
| commit | 0b67c0c421fb736b5086f69a7cc5415f66c3d369 (patch) | |
| tree | 70f59961b53ce4371c793028e9e9c7a6911a9a89 /lib | |
| parent | f5643c4a270baa4da33676950e36b1681d6d93dc (diff) | |
Update dpio read/write to take in extra PHY parameter.
The extra parameter is for future platform.
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/intel_dpio.c | 19 | ||||
| -rw-r--r-- | lib/intel_gpu_tools.h | 4 |
2 files changed, 17 insertions, 6 deletions
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c index acfd2018..7e22095e 100644 --- a/lib/intel_dpio.c +++ b/lib/intel_dpio.c @@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t val) *ptr = val; } +static int get_dpio_port(int phy) { + + struct pci_device *dev = intel_get_pci_device(); + int dpio_port; + + if (IS_VALLEYVIEW(dev->device_id)) + dpio_port = DPIO_PORTID; + + return dpio_port; +} + /* * In SoCs like Valleyview some of the PLL & Lane control registers * can be accessed only through IO side band fabric called DPIO */ uint32_t -intel_dpio_reg_read(uint32_t reg) +intel_dpio_reg_read(uint32_t reg, int phy) { /* Check whether the side band fabric is ready to accept commands */ do { @@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg) intel_display_reg_write(DPIO_REG, reg); intel_display_reg_write(DPIO_PKT, DPIO_RID | - DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE); + DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE); do { usleep(1); } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY); @@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg) * can be accessed only through IO side band fabric called DPIO */ void -intel_dpio_reg_write(uint32_t reg, uint32_t val) +intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy) { /* Check whether the side band fabric is ready to accept commands */ do { @@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val) intel_display_reg_write(DPIO_DATA, val); intel_display_reg_write(DPIO_REG, reg); intel_display_reg_write(DPIO_PKT, DPIO_RID | - DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE); + DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE); do { usleep(1); } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY); diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h index 412e4651..b242243c 100644 --- a/lib/intel_gpu_tools.h +++ b/lib/intel_gpu_tools.h @@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val); int intel_register_access_needs_fakewake(void); /* Following functions are relevant only for SoCs like Valleyview */ -uint32_t intel_dpio_reg_read(uint32_t reg); -void intel_dpio_reg_write(uint32_t reg, uint32_t val); +uint32_t intel_dpio_reg_read(uint32_t reg, int phy); +void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy); int intel_punit_read(uint8_t addr, uint32_t *val); int intel_punit_write(uint8_t addr, uint32_t val); |