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Diffstat (limited to 'src/i830_display.c')
-rw-r--r--src/i830_display.c98
1 files changed, 14 insertions, 84 deletions
diff --git a/src/i830_display.c b/src/i830_display.c
index a44143fd..a7eafb97 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -245,6 +245,8 @@ intel_find_pll_i8xx_and_i9xx(const intel_limit_t *, xf86CrtcPtr,
static Bool
intel_find_pll_g4x(const intel_limit_t *, xf86CrtcPtr,
int, int, intel_clock_t *);
+static void
+i830_crtc_load_lut(xf86CrtcPtr crtc);
static const intel_limit_t intel_limits[] = {
{ /* INTEL_LIMIT_I8XX_DVO_DAC */
@@ -696,7 +698,6 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y)
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
- int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
unsigned long Start, Offset, Stride;
int dspbase = (plane == 0 ? DSPABASE : DSPBBASE);
@@ -735,30 +736,6 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y)
OUTREG(dspbase, Start + Offset);
POSTING_READ(dspbase);
}
-
-#ifdef XF86DRI
- if (pI830->directRenderingType == DRI_XF86DRI) {
- drmI830Sarea *sPriv = (drmI830Sarea *) DRIGetSAREAPrivate(pScrn->pScreen);
-
- if (!sPriv)
- return;
-
- switch (pipe) {
- case 0:
- sPriv->pipeA_x = x;
- sPriv->pipeA_y = y;
- break;
- case 1:
- sPriv->pipeB_x = x;
- sPriv->pipeB_y = y;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Can't update pipe %d in SAREA\n", pipe);
- break;
- }
- }
-#endif
}
/*
@@ -1060,7 +1037,7 @@ i830_use_fb_compression(xf86CrtcPtr crtc)
return TRUE;
}
-#if defined(DRM_IOCTL_MODESET_CTL) && (defined(XF86DRI) || defined(DRI2))
+#if defined(DRM_IOCTL_MODESET_CTL)
static void i830_modeset_ctl(xf86CrtcPtr crtc, int pre)
{
ScrnInfoPtr pScrn = crtc->scrn;
@@ -1092,7 +1069,7 @@ static void i830_modeset_ctl(xf86CrtcPtr crtc, int dpms_state)
{
return;
}
-#endif /* DRM_IOCTL_MODESET_CTL && (XF86DRI || DRI2) */
+#endif /* DRM_IOCTL_MODESET_CTL */
static void
i830_disable_vga_plane (xf86CrtcPtr crtc)
@@ -1113,6 +1090,9 @@ i830_disable_vga_plane (xf86CrtcPtr crtc)
sr01 = INREG8(SRX + 1);
OUTREG8(SRX + 1, sr01 | (1 << 5));
usleep(30);
+ /* disable center mode on 965GM and G4X platform */
+ if (IS_I965GM(pI830) || IS_G4X(pI830))
+ vgacntrl &= ~(3 << 24);
vgacntrl |= VGA_DISP_DISABLE;
@@ -1121,7 +1101,7 @@ i830_disable_vga_plane (xf86CrtcPtr crtc)
}
-void
+static void
i830_crtc_enable(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
@@ -1281,54 +1261,22 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
}
intel_crtc->dpms_mode = mode;
-
-#ifdef XF86DRI
- if (pI830->directRenderingType == DRI_XF86DRI) {
- drmI830Sarea *sPriv = (drmI830Sarea *) DRIGetSAREAPrivate(pScrn->pScreen);
- Bool enabled = crtc->enabled && mode != DPMSModeOff;
-
- I830DRISetVBlankInterrupt (pScrn, TRUE);
-
- if (!sPriv)
- return;
-
- switch (pipe) {
- case 0:
- sPriv->pipeA_w = enabled ? crtc->mode.HDisplay : 0;
- sPriv->pipeA_h = enabled ? crtc->mode.VDisplay : 0;
- break;
- case 1:
- sPriv->pipeB_w = enabled ? crtc->mode.HDisplay : 0;
- sPriv->pipeB_h = enabled ? crtc->mode.VDisplay : 0;
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Can't update pipe %d in SAREA\n", pipe);
- break;
- }
- }
-#endif
}
static Bool
i830_crtc_lock (xf86CrtcPtr crtc)
{
- /* Sync the engine before mode switch */
- i830WaitSync(crtc->scrn);
+ /* Sync the engine before mode switch, to finish any outstanding
+ * WAIT_FOR_EVENTS that may rely on CRTC state.
+ */
+ I830Sync(crtc->scrn);
-#ifdef XF86DRI
- return I830DRILock(crtc->scrn);
-#else
return FALSE;
-#endif
}
static void
i830_crtc_unlock (xf86CrtcPtr crtc)
{
-#ifdef XF86DRI
- I830DRIUnlock (crtc->scrn);
-#endif
}
static void
@@ -1363,11 +1311,6 @@ i830_crtc_commit (xf86CrtcPtr crtc)
/* Reenable FB compression if possible */
if (i830_use_fb_compression(crtc))
i830_enable_fb_compression(crtc);
-
-#ifdef XF86DRI
- /* Tell DRI1 the news about new output config */
- i830_update_dri_buffers(crtc->scrn);
-#endif
}
void
@@ -1407,11 +1350,7 @@ i830_get_core_clock_speed(ScrnInfoPtr pScrn)
else if (IS_I915GM(pI830)) {
uint16_t gcfgc;
-#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u16 (pI830->PciInfo, &gcfgc, I915_GCFGC);
-#else
- gcfgc = pciReadWord(pI830->PciTag, I915_GCFGC);
-#endif
if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
return 133000;
else {
@@ -1426,14 +1365,9 @@ i830_get_core_clock_speed(ScrnInfoPtr pScrn)
} else if (IS_I865G(pI830))
return 266000;
else if (IS_I855(pI830)) {
-#if XSERVER_LIBPCIACCESS
struct pci_device *bridge = intel_host_bridge ();
uint16_t hpllcc;
pci_device_cfg_read_u16 (bridge, &hpllcc, I855_HPLLCC);
-#else
- PCITAG bridge = pciTag(0, 0, 0); /* This is always the host bridge */
- uint16_t hpllcc = pciReadWord(bridge, I855_HPLLCC);
-#endif
/* Assume that the hardware is in the high speed state. This
* should be the default.
@@ -1914,16 +1848,13 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
OUTREG(dspcntr_reg, dspcntr);
/* Flush the plane changes */
i830PipeSetBase(crtc, x, y);
-#ifdef XF86DRI
- I830DRISetVBlankInterrupt (pScrn, TRUE);
-#endif
-
+
i830WaitForVblank(pScrn);
}
/** Loads the palette/gamma unit for the CRTC with the prepared values */
-void
+static void
i830_crtc_load_lut(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
@@ -2397,7 +2328,6 @@ static const xf86CrtcFuncsRec i830_crtc_funcs = {
.set_cursor_position = i830_crtc_set_cursor_position,
.show_cursor = i830_crtc_show_cursor,
.hide_cursor = i830_crtc_hide_cursor,
-/* .load_cursor_image = i830_crtc_load_cursor_image, */
.load_cursor_argb = i830_crtc_load_cursor_argb,
.destroy = NULL, /* XXX */
#if RANDR_13_INTERFACE
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 08:55:06 +0000