i810: Move into a legacy directory.

The driver is still built but is no longer under active development so
move it and supporting files to a new directory.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

44 files changed, 1294 insertions, 1077 deletions

diff --git a/configure.ac b/configure.ac
index b2a48e27..9e88d210 100644
--- a/configure.ac
+++ b/configure.ac
@@ -156,6 +156,9 @@ AC_OUTPUT([
 	src/xvmc/shader/Makefile
 	src/xvmc/shader/mc/Makefile
 	src/xvmc/shader/vld/Makefile
+	src/legacy/Makefile
+	src/legacy/i810/Makefile
+	src/legacy/i810/xvmc/Makefile
 	man/Makefile
 	src/render_program/Makefile
 ])
diff --git a/src/Makefile.am b/src/Makefile.am
index 864660e2..9a502cc4 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -18,7 +18,7 @@
 #  IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 #  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
-SUBDIRS = xvmc render_program
+SUBDIRS = xvmc render_program legacy
 
 # this is obnoxious:
 # -module lets us name the module exactly how we want
@@ -32,35 +32,25 @@ AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
 intel_drv_la_LTLIBRARIES = intel_drv.la
 intel_drv_la_LDFLAGS = -module -avoid-version
 intel_drv_ladir = @moduledir@/drivers
-intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la
+intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la legacy/liblegacy.la
 intel_drv_la_LIBADD += @PCIACCESS_LIBS@
 
+NULL:=#
+
 INTEL_DRI_SRCS = \
-         i810_dri.c \
-         i810_dri.h \
          i830_dri.c \
-         i810_hwmc.c
+	 $(NULL)
 
 INTEL_XVMC_SRCS = \
 	 i830_hwmc.h \
-	 i830_hwmc.c
+	 i830_hwmc.c \
+	 $(NULL)
 
 intel_drv_la_SOURCES = \
          brw_defines.h \
          brw_structs.h \
          common.h \
-         i810_accel.c \
-         i810_common.h \
-         i810_cursor.c \
-         i810_dga.c \
-         i810_driver.c \
-         i810.h \
-         i810_io.c \
-         i810_memory.c \
-         i810_reg.h \
-         i810_ring.h \
-         i810_video.c \
-         i810_wmark.c \
+	 intel_module.c \
 	 i830_3d.c \
          i830_accel.c \
          i830_batchbuffer.c \
@@ -80,21 +70,26 @@ intel_drv_la_SOURCES = \
 	 i830_render.c \
 	 i915_render.c \
 	 i965_render.c \
-	 drmmode_display.c
+	 drmmode_display.c \
+	 $(NULL)
 
 EXTRA_DIST = 		\
 	$(XMODE_SRCS)	\
 	$(INTEL_DRI_SRCS) \
-	$(INTEL_XVMC_SRCS)
+	$(INTEL_XVMC_SRCS) \
+	$(NULL)
 
 if DRI
 intel_drv_la_SOURCES += \
-	$(INTEL_DRI_SRCS)
+	$(INTEL_DRI_SRCS) \
+	$(NULL)
 intel_drv_la_LIBADD += \
-	$(DRI_LIBS)
+	$(DRI_LIBS) \
+	$(NULL)
 endif
 
 if XVMC
 intel_drv_la_SOURCES += \
-	$(INTEL_XVMC_SRCS)
+	$(INTEL_XVMC_SRCS) \
+	$(NULL)
 endif
diff --git a/src/common.h b/src/common.h
index 30f1c781..f244e08e 100644
--- a/src/common.h
+++ b/src/common.h
@@ -143,16 +143,6 @@ static inline void memcpy_volatile(volatile void *dst, const void *src,
    }									\
 } while (0)
 
-/* To remove all debugging, make sure I810_DEBUG is defined as a
- * preprocessor symbol, and equal to zero.
- */
-#if 1
-#define I810_DEBUG 0
-#endif
-#ifndef I810_DEBUG
-#warning "Debugging enabled - expect reduced performance"
-extern int I810_DEBUG;
-#endif
 
 #define DEBUG_VERBOSE_ACCEL  0x1
 #define DEBUG_VERBOSE_SYNC   0x2
@@ -169,229 +159,6 @@ extern int I810_DEBUG;
  */
 #define I810_REG_SIZE 0x80000
 
-#ifndef PCI_CHIP_I810
-#define PCI_CHIP_I810              0x7121
-#define PCI_CHIP_I810_DC100        0x7123
-#define PCI_CHIP_I810_E            0x7125
-#define PCI_CHIP_I815              0x1132
-#define PCI_CHIP_I810_BRIDGE       0x7120
-#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
-#define PCI_CHIP_I810_E_BRIDGE     0x7124
-#define PCI_CHIP_I815_BRIDGE       0x1130
-#endif
-
-#ifndef PCI_CHIP_I830_M
-#define PCI_CHIP_I830_M            0x3577
-#define PCI_CHIP_I830_M_BRIDGE     0x3575
-#endif
-
-#ifndef PCI_CHIP_845_G
-#define PCI_CHIP_845_G		   0x2562
-#define PCI_CHIP_845_G_BRIDGE	   0x2560
-#endif
-
-#ifndef PCI_CHIP_I855_GM
-#define PCI_CHIP_I855_GM	   0x3582
-#define PCI_CHIP_I855_GM_BRIDGE	   0x3580
-#endif
-
-#ifndef PCI_CHIP_I865_G
-#define PCI_CHIP_I865_G		   0x2572
-#define PCI_CHIP_I865_G_BRIDGE	   0x2570
-#endif
-
-#ifndef PCI_CHIP_I915_G
-#define PCI_CHIP_I915_G		   0x2582
-#define PCI_CHIP_I915_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I915_GM
-#define PCI_CHIP_I915_GM	   0x2592
-#define PCI_CHIP_I915_GM_BRIDGE	   0x2590
-#endif
-
-#ifndef PCI_CHIP_E7221_G
-#define PCI_CHIP_E7221_G	   0x258A
-/* Same as I915_G_BRIDGE */
-#define PCI_CHIP_E7221_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I945_G
-#define PCI_CHIP_I945_G        0x2772
-#define PCI_CHIP_I945_G_BRIDGE 0x2770
-#endif
-
-#ifndef PCI_CHIP_I945_GM
-#define PCI_CHIP_I945_GM        0x27A2
-#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
-#endif
-
-#ifndef PCI_CHIP_I945_GME
-#define PCI_CHIP_I945_GME	 0x27AE
-#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
-#endif
-
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM		0xA011
-#define PCI_CHIP_IGD_GM_BRIDGE	0xA010
-#define PCI_CHIP_IGD_G		0xA001
-#define PCI_CHIP_IGD_G_BRIDGE	0xA000
-#endif
-
-#ifndef PCI_CHIP_G35_G
-#define PCI_CHIP_G35_G		0x2982
-#define PCI_CHIP_G35_G_BRIDGE 	0x2980
-#endif
-
-#ifndef PCI_CHIP_I965_Q
-#define PCI_CHIP_I965_Q		0x2992
-#define PCI_CHIP_I965_Q_BRIDGE 	0x2990
-#endif
-
-#ifndef PCI_CHIP_I965_G
-#define PCI_CHIP_I965_G		0x29A2
-#define PCI_CHIP_I965_G_BRIDGE 	0x29A0
-#endif
-
-#ifndef PCI_CHIP_I946_GZ
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I946_GZ_BRIDGE 	0x2970
-#endif
-
-#ifndef PCI_CHIP_I965_GM
-#define PCI_CHIP_I965_GM        0x2A02
-#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
-#endif
-
-#ifndef PCI_CHIP_I965_GME
-#define PCI_CHIP_I965_GME       0x2A12
-#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
-#endif
-
-#ifndef PCI_CHIP_G33_G
-#define PCI_CHIP_G33_G		0x29C2
-#define PCI_CHIP_G33_G_BRIDGE 	0x29C0
-#endif
-
-#ifndef PCI_CHIP_Q35_G
-#define PCI_CHIP_Q35_G		0x29B2
-#define PCI_CHIP_Q35_G_BRIDGE 	0x29B0
-#endif
-
-#ifndef PCI_CHIP_Q33_G
-#define PCI_CHIP_Q33_G		0x29D2
-#define PCI_CHIP_Q33_G_BRIDGE 	0x29D0
-#endif
-
-#ifndef PCI_CHIP_GM45_GM
-#define PCI_CHIP_GM45_GM	0x2A42
-#define PCI_CHIP_GM45_BRIDGE    0x2A40
-#endif
-
-#ifndef PCI_CHIP_IGD_E_G
-#define PCI_CHIP_IGD_E_G	0x2E02
-#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
-#endif
-
-#ifndef PCI_CHIP_G45_G
-#define PCI_CHIP_G45_G		0x2E22
-#define PCI_CHIP_G45_G_BRIDGE	0x2E20
-#endif
-
-#ifndef PCI_CHIP_Q45_G
-#define PCI_CHIP_Q45_G		0x2E12
-#define PCI_CHIP_Q45_G_BRIDGE	0x2E10
-#endif
-
-#ifndef PCI_CHIP_G41_G
-#define PCI_CHIP_G41_G		0x2E32
-#define PCI_CHIP_G41_G_BRIDGE	0x2E30
-#endif
-
-#ifndef PCI_CHIP_B43_G
-#define PCI_CHIP_B43_G		0x2E42
-#define PCI_CHIP_B43_G_BRIDGE	0x2E40
-#endif
-
-#ifndef PCI_CHIP_IGDNG_D_G
-#define PCI_CHIP_IGDNG_D_G		0x0042
-#define PCI_CHIP_IGDNG_D_G_BRIDGE	0x0040
-#endif
-
-#ifndef PCI_CHIP_IGDNG_M_G
-#define PCI_CHIP_IGDNG_M_G		0x0046
-#define PCI_CHIP_IGDNG_M_G_BRIDGE	0x0044
-#endif
-
-#ifndef PCI_CHIP_SANDYBRIDGE
-#define PCI_CHIP_SANDYBRIDGE		0x0102
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100
-#define PCI_CHIP_SANDYBRIDGE_M		0x0106
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104
-#endif
-
-#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
-#define VENDOR_ID(p)      (p)->vendor_id
-#define DEVICE_ID(p)      (p)->device_id
-#define SUBVENDOR_ID(p)	  (p)->subvendor_id
-#define SUBSYS_ID(p)      (p)->subdevice_id
-#define CHIP_REVISION(p)  (p)->revision
-
-#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 ||	\
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E)
-#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815)
-#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M)
-#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G)
-#define IS_I85X(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM)
-#define IS_I852(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
-#define IS_I855(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
-#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G)
-
-#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
-#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
-#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
-#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
-#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
-#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
-#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
-#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
-#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
-#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
-#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \
-			 IS_G4X(pI810) || \
-			 IS_IGDNG(pI810) || \
-			 IS_GEN6(pI810))
-#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
- 			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
-			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
-			    IS_IGD(pI810))
-
-#define IS_I9XX(pI810) (IS_I915G(pI810) ||			\
-			IS_I915GM(pI810) ||			\
-			IS_I945G(pI810) ||			\
-			IS_I945GM(pI810) ||			\
-			IS_I965G(pI810) ||			\
-			IS_G33CLASS(pI810))
-
-#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-
-#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M)
-
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
-/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
-#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
-
 #define GTT_PAGE_SIZE			KB(4)
 #define ROUND_TO(x, y)			(((x) + (y) - 1) / (y) * (y))
 #define ROUND_DOWN_TO(x, y)		((x) / (y) * (y))
diff --git a/src/i830.h b/src/i830.h
index 64acda3a..f8e4d496 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -51,7 +51,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "compiler.h"
 #include "xf86PciInfo.h"
 #include "xf86Pci.h"
-#include "i810_reg.h"
 #include "xf86Cursor.h"
 #include "xf86xv.h"
 #include "vgaHW.h"
@@ -70,6 +69,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "intel_bufmgr.h"
 #include "i915_drm.h"
 
+#include "intel_driver.h"
+
 #include "uxa.h"
 Bool i830_uxa_init(ScreenPtr pScreen);
 void i830_uxa_create_screen_resources(ScreenPtr pScreen);
@@ -324,7 +325,7 @@ typedef struct intel_screen_private {
 	unsigned long LinearAddr;
 	EntityInfoPtr pEnt;
 	struct pci_device *PciInfo;
-	uint8_t variant;
+	struct intel_chipset chipset;
 
 	unsigned int BR[20];
 
@@ -656,4 +657,6 @@ static inline Bool pixmap_is_scanout(PixmapPtr pixmap)
 	return pixmap == screen->GetScreenPixmap(screen);
 }
 
+const OptionInfoRec *i830_available_options(int chipid, int busid);
+
 #endif /* _I830_H_ */
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 9e8a5ede..1e5f03bd 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -42,7 +42,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include "xf86.h"
 #include "i830.h"
-#include "i810_reg.h"
 #include "i915_drm.h"
 
 unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap)
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index 2b7227ba..84b699a6 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -36,6 +36,7 @@
 
 #include "xf86.h"
 #include "i830.h"
+#include "i830_reg.h"
 #include "i915_drm.h"
 
 #define DUMP_BATCHBUFFERS NULL /* "/tmp/i915-batchbuffers.dump" */
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 4315bbac..21aae8d9 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -197,11 +197,6 @@ do {									\
 			   __FUNCTION__,				\
 			   intel->batch_used - intel->batch_emit_start,	\
 			   intel->batch_emitting);			\
-	if ((intel->batch_emitting > 8) &&				\
-	    (I810_DEBUG & DEBUG_ALWAYS_SYNC)) {				\
-		/* Note: not actually syncing, just flushing each batch. */ \
-		intel_batch_submit(scrn, FALSE);			\
-	}								\
 	intel->batch_emitting = 0;					\
 } while (0)
 
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 34e2336d..37d93cc7 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -61,6 +61,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "GL/glxtokens.h"
 
 #include "i830.h"
+#include "i830_reg.h"
 
 #include "i915_drm.h"
 
diff --git a/src/i830_driver.c b/src/i830_driver.c
index b8e0c0b4..2c165f44 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -77,6 +77,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "i830_hwmc.h"
 #endif
 
+#include "legacy/legacy.h"
+
 #include <sys/ioctl.h>
 #include "i915_drm.h"
 #include <xf86drmMode.h>
@@ -86,72 +88,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NB_OF(x) (sizeof (x) / sizeof (*x))
 
 /* *INDENT-OFF* */
-static SymTabRec I830Chipsets[] = {
-   {PCI_CHIP_I830_M,		"i830"},
-   {PCI_CHIP_845_G,		"845G"},
-   {PCI_CHIP_I855_GM,		"852GM/855GM"},
-   {PCI_CHIP_I865_G,		"865G"},
-   {PCI_CHIP_I915_G,		"915G"},
-   {PCI_CHIP_E7221_G,		"E7221 (i915)"},
-   {PCI_CHIP_I915_GM,		"915GM"},
-   {PCI_CHIP_I945_G,		"945G"},
-   {PCI_CHIP_I945_GM,		"945GM"},
-   {PCI_CHIP_I945_GME,		"945GME"},
-   {PCI_CHIP_IGD_GM,		"Pineview GM"},
-   {PCI_CHIP_IGD_G,		"Pineview G"},
-   {PCI_CHIP_I965_G,		"965G"},
-   {PCI_CHIP_G35_G,		"G35"},
-   {PCI_CHIP_I965_Q,		"965Q"},
-   {PCI_CHIP_I946_GZ,		"946GZ"},
-   {PCI_CHIP_I965_GM,		"965GM"},
-   {PCI_CHIP_I965_GME,		"965GME/GLE"},
-   {PCI_CHIP_G33_G,		"G33"},
-   {PCI_CHIP_Q35_G,		"Q35"},
-   {PCI_CHIP_Q33_G,		"Q33"},
-   {PCI_CHIP_GM45_GM,		"GM45"},
-   {PCI_CHIP_IGD_E_G,		"4 Series"},
-   {PCI_CHIP_G45_G,		"G45/G43"},
-   {PCI_CHIP_Q45_G,		"Q45/Q43"},
-   {PCI_CHIP_G41_G,		"G41"},
-   {PCI_CHIP_B43_G,		"B43"},
-   {PCI_CHIP_IGDNG_D_G,		"Clarkdale"},
-   {PCI_CHIP_IGDNG_M_G,		"Arrandale"},
-   {-1,				NULL}
-};
-
-static PciChipsets I830PciChipsets[] = {
-   {PCI_CHIP_I830_M,		PCI_CHIP_I830_M,	NULL},
-   {PCI_CHIP_845_G,		PCI_CHIP_845_G,		NULL},
-   {PCI_CHIP_I855_GM,		PCI_CHIP_I855_GM,	NULL},
-   {PCI_CHIP_I865_G,		PCI_CHIP_I865_G,	NULL},
-   {PCI_CHIP_I915_G,		PCI_CHIP_I915_G,	NULL},
-   {PCI_CHIP_E7221_G,		PCI_CHIP_E7221_G,	NULL},
-   {PCI_CHIP_I915_GM,		PCI_CHIP_I915_GM,	NULL},
-   {PCI_CHIP_I945_G,		PCI_CHIP_I945_G,	NULL},
-   {PCI_CHIP_I945_GM,		PCI_CHIP_I945_GM,	NULL},
-   {PCI_CHIP_I945_GME,		PCI_CHIP_I945_GME,	NULL},
-   {PCI_CHIP_IGD_GM,		PCI_CHIP_IGD_GM,	NULL},
-   {PCI_CHIP_IGD_G,		PCI_CHIP_IGD_G,		NULL},
-   {PCI_CHIP_I965_G,		PCI_CHIP_I965_G,	NULL},
-   {PCI_CHIP_G35_G,		PCI_CHIP_G35_G,		NULL},
-   {PCI_CHIP_I965_Q,		PCI_CHIP_I965_Q,	NULL},
-   {PCI_CHIP_I946_GZ,		PCI_CHIP_I946_GZ,	NULL},
-   {PCI_CHIP_I965_GM,		PCI_CHIP_I965_GM,	NULL},
-   {PCI_CHIP_I965_GME,		PCI_CHIP_I965_GME,	NULL},
-   {PCI_CHIP_G33_G,		PCI_CHIP_G33_G,		NULL},
-   {PCI_CHIP_Q35_G,		PCI_CHIP_Q35_G,		NULL},
-   {PCI_CHIP_Q33_G,		PCI_CHIP_Q33_G,		NULL},
-   {PCI_CHIP_GM45_GM,		PCI_CHIP_GM45_GM,	NULL},
-   {PCI_CHIP_IGD_E_G,		PCI_CHIP_IGD_E_G,	NULL},
-   {PCI_CHIP_G45_G,		PCI_CHIP_G45_G,		NULL},
-   {PCI_CHIP_Q45_G,		PCI_CHIP_Q45_G,		NULL},
-   {PCI_CHIP_G41_G,		PCI_CHIP_G41_G,		NULL},
-   {PCI_CHIP_B43_G,		PCI_CHIP_B43_G,		NULL},
-   {PCI_CHIP_IGDNG_D_G,		PCI_CHIP_IGDNG_D_G,		NULL},
-   {PCI_CHIP_IGDNG_M_G,		PCI_CHIP_IGDNG_M_G,		NULL},
-   {-1,				-1,			NULL}
-};
-
 /*
  * Note: "ColorKey" is provided for compatibility with the i810 driver.
  * However, the correct option name is "VideoKey".  "ColorKey" usually
@@ -159,6 +95,7 @@ static PciChipsets I830PciChipsets[] = {
  */
 
 typedef enum {
+   OPTION_ACCELMETHOD,
    OPTION_DRI,
    OPTION_VIDEO_KEY,
    OPTION_COLOR_KEY,
@@ -175,6 +112,7 @@ typedef enum {
 } I830Opts;
 
 static OptionInfoRec I830Options[] = {
+   {OPTION_ACCELMETHOD,	"AccelMethod",	OPTV_ANYSTR,	{0},	FALSE},
    {OPTION_DRI,		"DRI",		OPTV_BOOLEAN,	{0},	TRUE},
    {OPTION_COLOR_KEY,	"ColorKey",	OPTV_INTEGER,	{0},	FALSE},
    {OPTION_VIDEO_KEY,	"VideoKey",	OPTV_INTEGER,	{0},	FALSE},
@@ -217,15 +155,9 @@ I830DPRINTF(const char *filename, int line, const char *function,
 #endif /* #ifdef I830DEBUG */
 
 /* Export I830 options to i830 driver where necessary */
-const OptionInfoRec *I830AvailableOptions(int chipid, int busid)
+const OptionInfoRec *i830_available_options(int chipid, int busid)
 {
-	int i;
-
-	for (i = 0; I830PciChipsets[i].PCIid > 0; i++) {
-		if (chipid == I830PciChipsets[i].PCIid)
-			return I830Options;
-	}
-	return NULL;
+	return I830Options;
 }
 
 static Bool I830GetRec(ScrnInfoPtr scrn)
@@ -385,135 +317,18 @@ static void i830_detect_chipset(ScrnInfoPtr scrn)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 	MessageType from = X_PROBED;
-	const char *chipname;
-	uint32_t capid;
 
-	switch (DEVICE_ID(intel->PciInfo)) {
-	case PCI_CHIP_I830_M:
-		chipname = "830M";
-		break;
-	case PCI_CHIP_845_G:
-		chipname = "845G";
-		break;
-	case PCI_CHIP_I855_GM:
-		/* Check capid register to find the chipset variant */
-		pci_device_cfg_read_u32(intel->PciInfo, &capid, I85X_CAPID);
-		intel->variant =
-		    (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
-		switch (intel->variant) {
-		case I855_GM:
-			chipname = "855GM";
-			break;
-		case I855_GME:
-			chipname = "855GME";
-			break;
-		case I852_GM:
-			chipname = "852GM";
-			break;
-		case I852_GME:
-			chipname = "852GME";
-			break;
-		default:
-			xf86DrvMsg(scrn->scrnIndex, X_INFO,
-				   "Unknown 852GM/855GM variant: 0x%x)\n",
-				   intel->variant);
-			chipname = "852GM/855GM (unknown variant)";
-			break;
-		}
-		break;
-	case PCI_CHIP_I865_G:
-		chipname = "865G";
-		break;
-	case PCI_CHIP_I915_G:
-		chipname = "915G";
-		break;
-	case PCI_CHIP_E7221_G:
-		chipname = "E7221 (i915)";
-		break;
-	case PCI_CHIP_I915_GM:
-		chipname = "915GM";
-		break;
-	case PCI_CHIP_I945_G:
-		chipname = "945G";
-		break;
-	case PCI_CHIP_I945_GM:
-		chipname = "945GM";
-		break;
-	case PCI_CHIP_I945_GME:
-		chipname = "945GME";
-		break;
-	case PCI_CHIP_IGD_GM:
-		chipname = "Pineview GM";
-		break;
-	case PCI_CHIP_IGD_G:
-		chipname = "Pineview G";
-		break;
-	case PCI_CHIP_I965_G:
-		chipname = "965G";
-		break;
-	case PCI_CHIP_G35_G:
-		chipname = "G35";
-		break;
-	case PCI_CHIP_I965_Q:
-		chipname = "965Q";
-		break;
-	case PCI_CHIP_I946_GZ:
-		chipname = "946GZ";
-		break;
-	case PCI_CHIP_I965_GM:
-		chipname = "965GM";
-		break;
-	case PCI_CHIP_I965_GME:
-		chipname = "965GME/GLE";
-		break;
-	case PCI_CHIP_G33_G:
-		chipname = "G33";
-		break;
-	case PCI_CHIP_Q35_G:
-		chipname = "Q35";
-		break;
-	case PCI_CHIP_Q33_G:
-		chipname = "Q33";
-		break;
-	case PCI_CHIP_GM45_GM:
-		chipname = "GM45";
-		break;
-	case PCI_CHIP_IGD_E_G:
-		chipname = "4 Series";
-		break;
-	case PCI_CHIP_G45_G:
-		chipname = "G45/G43";
-		break;
-	case PCI_CHIP_Q45_G:
-		chipname = "Q45/Q43";
-		break;
-	case PCI_CHIP_G41_G:
-		chipname = "G41";
-		break;
-	case PCI_CHIP_B43_G:
-		chipname = "B43";
-		break;
-	case PCI_CHIP_IGDNG_D_G:
-		chipname = "Clarkdale";
-		break;
-	case PCI_CHIP_IGDNG_M_G:
-		chipname = "Arrandale";
-		break;
-	default:
-		chipname = "unknown chipset";
-		break;
-	}
-	xf86DrvMsg(scrn->scrnIndex, X_INFO,
-		   "Integrated Graphics Chipset: Intel(R) %s\n", chipname);
+	intel_detect_chipset(scrn,
+			     intel->PciInfo,
+			     &intel->chipset);
 
 	/* Set the Chipset and ChipRev, allowing config file entries to override. */
 	if (intel->pEnt->device->chipset && *intel->pEnt->device->chipset) {
 		scrn->chipset = intel->pEnt->device->chipset;
 		from = X_CONFIG;
 	} else if (intel->pEnt->device->chipID >= 0) {
-		scrn->chipset = (char *)xf86TokenToString(I830Chipsets,
-							   intel->pEnt->device->
-							   chipID);
+		scrn->chipset = (char *)xf86TokenToString(intel_chipsets,
+							   intel->pEnt->device->chipID);
 		from = X_CONFIG;
 		xf86DrvMsg(scrn->scrnIndex, X_CONFIG,
 			   "ChipID override: 0x%04X\n",
@@ -521,9 +336,8 @@ static void i830_detect_chipset(ScrnInfoPtr scrn)
 		DEVICE_ID(intel->PciInfo) = intel->pEnt->device->chipID;
 	} else {
 		from = X_PROBED;
-		scrn->chipset = (char *)xf86TokenToString(I830Chipsets,
-							   DEVICE_ID(intel->
-								     PciInfo));
+		scrn->chipset = (char *)xf86TokenToString(intel_chipsets,
+							   DEVICE_ID(intel->PciInfo));
 	}
 
 	if (intel->pEnt->device->chipRev >= 0) {
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 50e31636..5e530aa5 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -84,7 +84,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "xf86_OSproc.h"
 
 #include "i830.h"
-#include "i810_reg.h"
 #include "i915_drm.h"
 
 /**
diff --git a/src/i830_reg.h b/src/i830_reg.h
index 3bba44da..40808962 100644
--- a/src/i830_reg.h
+++ b/src/i830_reg.h
@@ -30,6 +30,73 @@
 
 #define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value)
 
+/* Flush */
+#define MI_FLUSH			(0x04<<23)
+#define MI_WRITE_DIRTY_STATE		(1<<4)
+#define MI_END_SCENE			(1<<3)
+#define MI_GLOBAL_SNAPSHOT_COUNT_RESET	(1<<3)
+#define MI_INHIBIT_RENDER_CACHE_FLUSH	(1<<2)
+#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
+#define MI_INVALIDATE_MAP_CACHE		(1<<0)
+/* broadwater flush bits */
+#define BRW_MI_GLOBAL_SNAPSHOT_RESET   (1 << 3)
+
+#define MI_BATCH_BUFFER_END	(0xA << 23)
+
+/* Noop */
+#define MI_NOOP				0x00
+#define MI_NOOP_WRITE_ID		(1<<22)
+#define MI_NOOP_ID_MASK			(1<<22 - 1)
+
+/* Wait for Events */
+#define MI_WAIT_FOR_EVENT			(0x03<<23)
+#define MI_WAIT_FOR_PIPEB_SVBLANK		(1<<18)
+#define MI_WAIT_FOR_PIPEA_SVBLANK		(1<<17)
+#define MI_WAIT_FOR_OVERLAY_FLIP		(1<<16)
+#define MI_WAIT_FOR_PIPEB_VBLANK		(1<<7)
+#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW	(1<<5)
+#define MI_WAIT_FOR_PIPEA_VBLANK		(1<<3)
+#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW	(1<<1)
+
+/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */
+#define MI_LOAD_SCAN_LINES_INCL			(0x12<<23)
+#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA	(0)
+#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB	(0x1<<20)
+
+/* BLT commands */
+#define COLOR_BLT_CMD		((2<<29)|(0x40<<22)|(0x3))
+#define COLOR_BLT_WRITE_ALPHA	(1<<21)
+#define COLOR_BLT_WRITE_RGB	(1<<20)
+
+#define XY_COLOR_BLT_CMD		((2<<29)|(0x50<<22)|(0x4))
+#define XY_COLOR_BLT_WRITE_ALPHA	(1<<21)
+#define XY_COLOR_BLT_WRITE_RGB		(1<<20)
+#define XY_COLOR_BLT_TILED		(1<<11)
+
+#define XY_SETUP_CLIP_BLT_CMD		((2<<29)|(3<<22)|1)
+
+#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
+#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
+#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15)
+#define XY_SRC_COPY_BLT_DST_TILED	(1<<11)
+
+#define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|0x4)
+#define SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define SRC_COPY_BLT_WRITE_RGB		(1<<20)
+
+#define XY_PAT_BLT_IMMEDIATE		((2<<29)|(0x72<<22))
+
+#define XY_MONO_PAT_BLT_CMD		((0x2<<29)|(0x52<<22)|0x7)
+#define XY_MONO_PAT_VERT_SEED		((1<<10)|(1<<9)|(1<<8))
+#define XY_MONO_PAT_HORT_SEED		((1<<14)|(1<<13)|(1<<12))
+#define XY_MONO_PAT_BLT_WRITE_ALPHA	(1<<21)
+#define XY_MONO_PAT_BLT_WRITE_RGB	(1<<20)
+
+#define XY_MONO_SRC_BLT_CMD		((0x2<<29)|(0x54<<22)|(0x6))
+#define XY_MONO_SRC_BLT_WRITE_ALPHA	(1<<21)
+#define XY_MONO_SRC_BLT_WRITE_RGB	(1<<20)
+
 #define CMD_3D (0x3<<29)
 
 #define PRIM3D_INLINE		(CMD_3D | (0x1f<<24))
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index 61e857ff..8075ff54 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -34,7 +34,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "xf86.h"
 #include "xaarop.h"
 #include "i830.h"
-#include "i810_reg.h"
+#include "i830_reg.h"
 #include "i915_drm.h"
 #include "brw_defines.h"
 #include <string.h>
diff --git a/src/i830_video.c b/src/i830_video.c
index 86f3f774..bfa25de6 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -65,6 +65,7 @@
 #include "windowstr.h"
 #include "damage.h"
 #include "i830.h"
+#include "i830_reg.h"
 #include "i830_video.h"
 #include "xf86xv.h"
 #include <X11/extensions/Xv.h>
diff --git a/src/i915_3d.c b/src/i915_3d.c
index 906043b1..de919eec 100644
--- a/src/i915_3d.c
+++ b/src/i915_3d.c
@@ -106,7 +106,5 @@ void I915EmitInvarientState(ScrnInfoPtr scrn)
 	OUT_BATCH(_3DSTATE_STIPPLE);
 	OUT_BATCH(0x00000000);
 
-	OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE |
-		  0);
-	OUT_BATCH(MI_NOOP);
+	OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 }
diff --git a/src/i965_reg.h b/src/i965_reg.h
new file mode 100644
index 00000000..fe419dc1
--- /dev/null
+++ b/src/i965_reg.h
@@ -0,0 +1,241 @@
+/*
+ * New regs for broadwater -- we need to split this file up sensibly somehow.
+ */
+#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
+					   ((Pipeline) << 27) | \
+					   ((Opcode) << 24) | \
+					   ((Subopcode) << 16))
+
+#define BRW_URB_FENCE				BRW_3D(0, 0, 0)
+#define BRW_CS_URB_STATE			BRW_3D(0, 0, 1)
+#define BRW_CONSTANT_BUFFER			BRW_3D(0, 0, 2)
+#define BRW_STATE_PREFETCH			BRW_3D(0, 0, 3)
+
+#define BRW_STATE_BASE_ADDRESS			BRW_3D(0, 1, 1)
+#define BRW_STATE_SIP				BRW_3D(0, 1, 2)
+#define BRW_PIPELINE_SELECT			BRW_3D(0, 1, 4)
+
+#define NEW_PIPELINE_SELECT			BRW_3D(1, 1, 4)
+
+#define BRW_MEDIA_STATE_POINTERS		BRW_3D(2, 0, 0)
+#define BRW_MEDIA_OBJECT			BRW_3D(2, 1, 0)
+
+#define BRW_3DSTATE_PIPELINED_POINTERS		BRW_3D(3, 0, 0)
+#define BRW_3DSTATE_BINDING_TABLE_POINTERS	BRW_3D(3, 0, 1)
+#define BRW_3DSTATE_VERTEX_BUFFERS		BRW_3D(3, 0, 8)
+#define BRW_3DSTATE_VERTEX_ELEMENTS		BRW_3D(3, 0, 9)
+#define BRW_3DSTATE_INDEX_BUFFER		BRW_3D(3, 0, 0xa)
+#define BRW_3DSTATE_VF_STATISTICS		BRW_3D(3, 0, 0xb)
+
+#define BRW_3DSTATE_DRAWING_RECTANGLE		BRW_3D(3, 1, 0)
+#define BRW_3DSTATE_CONSTANT_COLOR		BRW_3D(3, 1, 1)
+#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD	BRW_3D(3, 1, 2)
+#define BRW_3DSTATE_CHROMA_KEY			BRW_3D(3, 1, 4)
+#define BRW_3DSTATE_DEPTH_BUFFER		BRW_3D(3, 1, 5)
+#define BRW_3DSTATE_POLY_STIPPLE_OFFSET		BRW_3D(3, 1, 6)
+#define BRW_3DSTATE_POLY_STIPPLE_PATTERN	BRW_3D(3, 1, 7)
+#define BRW_3DSTATE_LINE_STIPPLE		BRW_3D(3, 1, 8)
+#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP	BRW_3D(3, 1, 9)
+/* These two are BLC and CTG only, not BW or CL */
+#define BRW_3DSTATE_AA_LINE_PARAMS		BRW_3D(3, 1, 0xa)
+#define BRW_3DSTATE_GS_SVB_INDEX		BRW_3D(3, 1, 0xb)
+
+#define BRW_PIPE_CONTROL			BRW_3D(3, 2, 0)
+
+#define BRW_3DPRIMITIVE				BRW_3D(3, 3, 0)
+
+#define PIPELINE_SELECT_3D		0
+#define PIPELINE_SELECT_MEDIA		1
+
+#define UF0_CS_REALLOC			(1 << 13)
+#define UF0_VFE_REALLOC			(1 << 12)
+#define UF0_SF_REALLOC			(1 << 11)
+#define UF0_CLIP_REALLOC		(1 << 10)
+#define UF0_GS_REALLOC			(1 << 9)
+#define UF0_VS_REALLOC			(1 << 8)
+#define UF1_CLIP_FENCE_SHIFT		20
+#define UF1_GS_FENCE_SHIFT		10
+#define UF1_VS_FENCE_SHIFT		0
+#define UF2_CS_FENCE_SHIFT		20
+#define UF2_VFE_FENCE_SHIFT		10
+#define UF2_SF_FENCE_SHIFT		0
+
+/* for BRW_STATE_BASE_ADDRESS */
+#define BASE_ADDRESS_MODIFY		(1 << 0)
+
+/* for BRW_3DSTATE_PIPELINED_POINTERS */
+#define BRW_GS_DISABLE		       0
+#define BRW_GS_ENABLE		       1
+#define BRW_CLIP_DISABLE	       0
+#define BRW_CLIP_ENABLE		       1
+
+/* for BRW_PIPE_CONTROL */
+#define BRW_PIPE_CONTROL_NOWRITE       (0 << 14)
+#define BRW_PIPE_CONTROL_WRITE_QWORD   (1 << 14)
+#define BRW_PIPE_CONTROL_WRITE_DEPTH   (2 << 14)
+#define BRW_PIPE_CONTROL_WRITE_TIME    (3 << 14)
+#define BRW_PIPE_CONTROL_DEPTH_STALL   (1 << 13)
+#define BRW_PIPE_CONTROL_WC_FLUSH      (1 << 12)
+#define BRW_PIPE_CONTROL_IS_FLUSH      (1 << 11)
+#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
+#define BRW_PIPE_CONTROL_GLOBAL_GTT    (1 << 2)
+#define BRW_PIPE_CONTROL_LOCAL_PGTT    (0 << 2)
+
+/* VERTEX_BUFFER_STATE Structure */
+#define VB0_BUFFER_INDEX_SHIFT		27
+#define VB0_VERTEXDATA			(0 << 26)
+#define VB0_INSTANCEDATA		(1 << 26)
+#define VB0_BUFFER_PITCH_SHIFT		0
+
+/* VERTEX_ELEMENT_STATE Structure */
+#define VE0_VERTEX_BUFFER_INDEX_SHIFT	27
+#define VE0_VALID			(1 << 26)
+#define VE0_FORMAT_SHIFT		16
+#define VE0_OFFSET_SHIFT		0
+#define VE1_VFCOMPONENT_0_SHIFT		28
+#define VE1_VFCOMPONENT_1_SHIFT		24
+#define VE1_VFCOMPONENT_2_SHIFT		20
+#define VE1_VFCOMPONENT_3_SHIFT		16
+#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT	0
+
+/* 3DPRIMITIVE bits */
+#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
+#define BRW_3DPRIMITIVE_VERTEX_RANDOM	  (1 << 15)
+/* Primitive types are in brw_defines.h */
+#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT	  10
+
+#define BRW_SVG_CTL		       0x7400
+
+#define BRW_SVG_CTL_GS_BA	       (0 << 8)
+#define BRW_SVG_CTL_SS_BA	       (1 << 8)
+#define BRW_SVG_CTL_IO_BA	       (2 << 8)
+#define BRW_SVG_CTL_GS_AUB	       (3 << 8)
+#define BRW_SVG_CTL_IO_AUB	       (4 << 8)
+#define BRW_SVG_CTL_SIP		       (5 << 8)
+
+#define BRW_SVG_RDATA		       0x7404
+#define BRW_SVG_WORK_CTL	       0x7408
+
+#define BRW_VF_CTL		       0x7500
+
+#define BRW_VF_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
+#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID	   (0 << 8)
+#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG	   (1 << 8)
+#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE   (0 << 4)
+#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX	   (1 << 4)
+#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES	   (1 << 3)
+#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE	   (1 << 2)
+#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE	   (1 << 1)
+#define BRW_VF_CTL_SNAPSHOT_ENABLE	     	   (1 << 0)
+
+#define BRW_VF_STRG_VAL		       0x7504
+#define BRW_VF_STR_VL_OVR	       0x7508
+#define BRW_VF_VC_OVR		       0x750c
+#define BRW_VF_STR_PSKIP	       0x7510
+#define BRW_VF_MAX_PRIM		       0x7514
+#define BRW_VF_RDATA		       0x7518
+
+#define BRW_VS_CTL		       0x7600
+#define BRW_VS_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
+#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0	   (0 << 8)
+#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1	   (1 << 8)
+#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT	   (2 << 8)
+#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER  (3 << 8)
+#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS		   (1 << 2)
+#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE	   (1 << 1)
+#define BRW_VS_CTL_SNAPSHOT_ENABLE		   (1 << 0)
+
+#define BRW_VS_STRG_VAL		       0x7604
+#define BRW_VS_RDATA		       0x7608
+
+#define BRW_SF_CTL		       0x7b00
+#define BRW_SF_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID	   (0 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID	   (2 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID	   (4 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT	   (6 << 8)
+#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER  (7 << 8)
+#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE  (1 << 4)
+#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE	   (1 << 3)
+#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS		   (1 << 2)
+#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE	   (1 << 1)
+#define BRW_SF_CTL_SNAPSHOT_ENABLE		   (1 << 0)
+
+#define BRW_SF_STRG_VAL		       0x7b04
+#define BRW_SF_RDATA		       0x7b18
+
+#define BRW_WIZ_CTL		       0x7c00
+#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
+#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT	   16
+#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER   (0 << 8)
+#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE     (1 << 8)
+#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE   (2 << 8)
+#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH	      (1 << 6)
+#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS    (1 << 5)
+#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE   (1 << 4)
+#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG	      (1 << 3)
+#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS	      (1 << 2)
+#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE	      (1 << 1)
+#define BRW_WIZ_CTL_SNAPSHOT_ENABLE		      (1 << 0)
+
+#define BRW_WIZ_STRG_VAL			      0x7c04
+#define BRW_WIZ_RDATA				      0x7c18
+
+#define BRW_TS_CTL		       0x7e00
+#define BRW_TS_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
+#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR	   (0 << 8)
+#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR   (3 << 8)
+#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS	   (1 << 2)
+#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS  	   (1 << 1)
+#define BRW_TS_CTL_SNAPSHOT_ENABLE		   (1 << 0)
+
+#define BRW_TS_STRG_VAL		       0x7e04
+#define BRW_TS_RDATA		       0x7e08
+
+#define BRW_TD_CTL		       0x8000
+#define BRW_TD_CTL_MUX_SHIFT	       8
+#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH	   (1 << 7)
+#define BRW_TD_CTL_FORCE_EXTERNAL_HALT		   (1 << 6)
+#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE	   (1 << 5)
+#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE  (1 << 4)
+#define BRW_TD_CTL_BREAKPOINT_ENABLE		   (1 << 2)
+#define BRW_TD_CTL2		       0x8004
+#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28)
+#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE      (1 << 26)
+#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE	      (1 << 25)
+#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT	      16
+#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE	      (1 << 8)
+#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7)
+#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE	      (1 << 6)
+#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE	      (1 << 5)
+#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE     (1 << 4)
+#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE	      (1 << 3)
+#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE	      (1 << 0)
+#define BRW_TD_VF_VS_EMSK	       0x8008
+#define BRW_TD_GS_EMSK		       0x800c
+#define BRW_TD_CLIP_EMSK	       0x8010
+#define BRW_TD_SF_EMSK		       0x8014
+#define BRW_TD_WIZ_EMSK		       0x8018
+#define BRW_TD_0_6_EHTRG_VAL	       0x801c
+#define BRW_TD_0_7_EHTRG_VAL	       0x8020
+#define BRW_TD_0_6_EHTRG_MSK           0x8024
+#define BRW_TD_0_7_EHTRG_MSK	       0x8028
+#define BRW_TD_RDATA		       0x802c
+#define BRW_TD_TS_EMSK		       0x8030
+
+#define BRW_EU_CTL		       0x8800
+#define BRW_EU_CTL_SELECT_SHIFT	       16
+#define BRW_EU_CTL_DATA_MUX_SHIFT      8
+#define BRW_EU_ATT_0		       0x8810
+#define BRW_EU_ATT_1		       0x8814
+#define BRW_EU_ATT_DATA_0	       0x8820
+#define BRW_EU_ATT_DATA_1	       0x8824
+#define BRW_EU_ATT_CLR_0	       0x8830
+#define BRW_EU_ATT_CLR_1	       0x8834
+#define BRW_EU_RDATA		       0x8840
+
+/* End regs for broadwater */
+
diff --git a/src/i965_render.c b/src/i965_render.c
index 9ba6105a..1402d148 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -36,7 +36,8 @@
 #include <assert.h>
 #include "xf86.h"
 #include "i830.h"
-#include "i915_reg.h"
+#include "i830_reg.h"
+#include "i965_reg.h"
 
 /* bring in brw structs */
 #include "brw_defines.h"
diff --git a/src/i965_video.c b/src/i965_video.c
index a5136e06..9ec94dde 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -36,12 +36,15 @@
 #include "fourcc.h"
 
 #include "i830.h"
+#include "i830_reg.h"
 #include "i830_video.h"
 #include "i830_hwmc.h"
+#include "i965_reg.h"
 #include "brw_defines.h"
 #include "brw_structs.h"
 #include <string.h>
 
+
 /* Make assert() work. */
 #undef NDEBUG
 #include <assert.h>
diff --git a/src/intel_driver.h b/src/intel_driver.h
new file mode 100644
index 00000000..3e4a79da
--- /dev/null
+++ b/src/intel_driver.h
@@ -0,0 +1,254 @@
+#ifndef INTEL_DRIVER_H
+#define INTEL_DRIVER_H
+
+#define INTEL_VERSION 4000
+#define INTEL_NAME "intel"
+#define INTEL_DRIVER_NAME "intel"
+
+#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
+#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
+#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
+
+#ifndef PCI_CHIP_I810
+#define PCI_CHIP_I810              0x7121
+#define PCI_CHIP_I810_DC100        0x7123
+#define PCI_CHIP_I810_E            0x7125
+#define PCI_CHIP_I815              0x1132
+#define PCI_CHIP_I810_BRIDGE       0x7120
+#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
+#define PCI_CHIP_I810_E_BRIDGE     0x7124
+#define PCI_CHIP_I815_BRIDGE       0x1130
+#endif
+
+#ifndef PCI_CHIP_I830_M
+#define PCI_CHIP_I830_M            0x3577
+#define PCI_CHIP_I830_M_BRIDGE     0x3575
+#endif
+
+#ifndef PCI_CHIP_845_G
+#define PCI_CHIP_845_G		   0x2562
+#define PCI_CHIP_845_G_BRIDGE	   0x2560
+#endif
+
+#ifndef PCI_CHIP_I855_GM
+#define PCI_CHIP_I855_GM	   0x3582
+#define PCI_CHIP_I855_GM_BRIDGE	   0x3580
+#endif
+
+#ifndef PCI_CHIP_I865_G
+#define PCI_CHIP_I865_G		   0x2572
+#define PCI_CHIP_I865_G_BRIDGE	   0x2570
+#endif
+
+#ifndef PCI_CHIP_I915_G
+#define PCI_CHIP_I915_G		   0x2582
+#define PCI_CHIP_I915_G_BRIDGE	   0x2580
+#endif
+
+#ifndef PCI_CHIP_I915_GM
+#define PCI_CHIP_I915_GM	   0x2592
+#define PCI_CHIP_I915_GM_BRIDGE	   0x2590
+#endif
+
+#ifndef PCI_CHIP_E7221_G
+#define PCI_CHIP_E7221_G	   0x258A
+/* Same as I915_G_BRIDGE */
+#define PCI_CHIP_E7221_G_BRIDGE	   0x2580
+#endif
+
+#ifndef PCI_CHIP_I945_G
+#define PCI_CHIP_I945_G        0x2772
+#define PCI_CHIP_I945_G_BRIDGE 0x2770
+#endif
+
+#ifndef PCI_CHIP_I945_GM
+#define PCI_CHIP_I945_GM        0x27A2
+#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
+#endif
+
+#ifndef PCI_CHIP_I945_GME
+#define PCI_CHIP_I945_GME	 0x27AE
+#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
+#endif
+
+#ifndef PCI_CHIP_IGD_GM
+#define PCI_CHIP_IGD_GM		0xA011
+#define PCI_CHIP_IGD_GM_BRIDGE	0xA010
+#define PCI_CHIP_IGD_G		0xA001
+#define PCI_CHIP_IGD_G_BRIDGE	0xA000
+#endif
+
+#ifndef PCI_CHIP_G35_G
+#define PCI_CHIP_G35_G		0x2982
+#define PCI_CHIP_G35_G_BRIDGE 	0x2980
+#endif
+
+#ifndef PCI_CHIP_I965_Q
+#define PCI_CHIP_I965_Q		0x2992
+#define PCI_CHIP_I965_Q_BRIDGE 	0x2990
+#endif
+
+#ifndef PCI_CHIP_I965_G
+#define PCI_CHIP_I965_G		0x29A2
+#define PCI_CHIP_I965_G_BRIDGE 	0x29A0
+#endif
+
+#ifndef PCI_CHIP_I946_GZ
+#define PCI_CHIP_I946_GZ		0x2972
+#define PCI_CHIP_I946_GZ_BRIDGE 	0x2970
+#endif
+
+#ifndef PCI_CHIP_I965_GM
+#define PCI_CHIP_I965_GM        0x2A02
+#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
+#endif
+
+#ifndef PCI_CHIP_I965_GME
+#define PCI_CHIP_I965_GME       0x2A12
+#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
+#endif
+
+#ifndef PCI_CHIP_G33_G
+#define PCI_CHIP_G33_G		0x29C2
+#define PCI_CHIP_G33_G_BRIDGE 	0x29C0
+#endif
+
+#ifndef PCI_CHIP_Q35_G
+#define PCI_CHIP_Q35_G		0x29B2
+#define PCI_CHIP_Q35_G_BRIDGE 	0x29B0
+#endif
+
+#ifndef PCI_CHIP_Q33_G
+#define PCI_CHIP_Q33_G		0x29D2
+#define PCI_CHIP_Q33_G_BRIDGE 	0x29D0
+#endif
+
+#ifndef PCI_CHIP_GM45_GM
+#define PCI_CHIP_GM45_GM	0x2A42
+#define PCI_CHIP_GM45_BRIDGE    0x2A40
+#endif
+
+#ifndef PCI_CHIP_IGD_E_G
+#define PCI_CHIP_IGD_E_G	0x2E02
+#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
+#endif
+
+#ifndef PCI_CHIP_G45_G
+#define PCI_CHIP_G45_G		0x2E22
+#define PCI_CHIP_G45_G_BRIDGE	0x2E20
+#endif
+
+#ifndef PCI_CHIP_Q45_G
+#define PCI_CHIP_Q45_G		0x2E12
+#define PCI_CHIP_Q45_G_BRIDGE	0x2E10
+#endif
+
+#ifndef PCI_CHIP_G41_G
+#define PCI_CHIP_G41_G		0x2E32
+#define PCI_CHIP_G41_G_BRIDGE	0x2E30
+#endif
+
+#ifndef PCI_CHIP_B43_G
+#define PCI_CHIP_B43_G		0x2E42
+#define PCI_CHIP_B43_G_BRIDGE	0x2E40
+#endif
+
+#ifndef PCI_CHIP_IGDNG_D_G
+#define PCI_CHIP_IGDNG_D_G		0x0042
+#define PCI_CHIP_IGDNG_D_G_BRIDGE	0x0040
+#endif
+
+#ifndef PCI_CHIP_IGDNG_M_G
+#define PCI_CHIP_IGDNG_M_G		0x0046
+#define PCI_CHIP_IGDNG_M_G_BRIDGE	0x0044
+#endif
+
+#ifndef PCI_CHIP_SANDYBRIDGE
+#define PCI_CHIP_SANDYBRIDGE		0x0102
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100
+#define PCI_CHIP_SANDYBRIDGE_M		0x0106
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104
+#endif
+
+#define I85X_CAPID			0x44
+#define I85X_VARIANT_MASK			0x7
+#define I85X_VARIANT_SHIFT			5
+#define I855_GME				0x0
+#define I855_GM					0x4
+#define I852_GME				0x2
+#define I852_GM					0x5
+
+#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
+#define VENDOR_ID(p)      (p)->vendor_id
+#define DEVICE_ID(p)      (p)->device_id
+#define SUBVENDOR_ID(p)	  (p)->subvendor_id
+#define SUBSYS_ID(p)      (p)->subdevice_id
+#define CHIP_REVISION(p)  (p)->revision
+
+#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 ||	\
+			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
+			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E)
+#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815)
+#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M)
+#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G)
+#define IS_I85X(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM)
+#define IS_I852(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
+#define IS_I855(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
+#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G)
+
+#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
+#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
+#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
+#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
+#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
+#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
+#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
+#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
+#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
+#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
+#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
+#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
+#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \
+			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \
+			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || \
+			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || \
+			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || \
+			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \
+			 IS_G4X(pI810) || \
+			 IS_IGDNG(pI810) || \
+			 IS_GEN6(pI810))
+#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
+ 			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
+			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
+			    IS_IGD(pI810))
+
+#define IS_I9XX(pI810) (IS_I915G(pI810) ||			\
+			IS_I915GM(pI810) ||			\
+			IS_I945G(pI810) ||			\
+			IS_I945GM(pI810) ||			\
+			IS_I965G(pI810) ||			\
+			IS_G33CLASS(pI810))
+
+#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
+
+#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE || \
+			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M)
+
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
+/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
+#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
+
+extern SymTabRec *intel_chipsets;
+
+struct intel_chipset {
+    const char *name;
+    int variant;
+};
+
+void intel_detect_chipset(ScrnInfoPtr scrn,
+			  struct pci_device *pci,
+			  struct intel_chipset *chipset);
+
+#endif /* INTEL_DRIVER_H */
diff --git a/src/intel_module.c b/src/intel_module.c
new file mode 100644
index 00000000..1624d06d
--- /dev/null
+++ b/src/intel_module.c
@@ -0,0 +1,447 @@
+/*
+ * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "xf86.h"
+#include "xf86_OSproc.h"
+#include "xf86cmap.h"
+
+#include "common.h"
+#include "i830.h"
+#include "intel_driver.h"
+#include "legacy/legacy.h"
+
+static const SymTabRec _intel_chipsets[] = {
+    {PCI_CHIP_I810,		"i810"},
+    {PCI_CHIP_I810_DC100,	"i810-dc100"},
+    {PCI_CHIP_I810_E,		"i810e"},
+    {PCI_CHIP_I815,		"i815"},
+    {PCI_CHIP_I830_M,		"i830M"},
+    {PCI_CHIP_845_G,		"845G"},
+    {PCI_CHIP_I855_GM,		"852GM/855GM"},
+    {PCI_CHIP_I865_G,		"865G"},
+    {PCI_CHIP_I915_G,		"915G"},
+    {PCI_CHIP_E7221_G,		"E7221 (i915)"},
+    {PCI_CHIP_I915_GM,		"915GM"},
+    {PCI_CHIP_I945_G,		"945G"},
+    {PCI_CHIP_I945_GM,		"945GM"},
+    {PCI_CHIP_I945_GME,		"945GME"},
+    {PCI_CHIP_IGD_GM,		"Pineview GM"},
+    {PCI_CHIP_IGD_G,		"Pineview G"},
+    {PCI_CHIP_I965_G,		"965G"},
+    {PCI_CHIP_G35_G,		"G35"},
+    {PCI_CHIP_I965_Q,		"965Q"},
+    {PCI_CHIP_I946_GZ,		"946GZ"},
+    {PCI_CHIP_I965_GM,		"965GM"},
+    {PCI_CHIP_I965_GME,		"965GME/GLE"},
+    {PCI_CHIP_G33_G,		"G33"},
+    {PCI_CHIP_Q35_G,		"Q35"},
+    {PCI_CHIP_Q33_G,		"Q33"},
+    {PCI_CHIP_GM45_GM,		"GM45"},
+    {PCI_CHIP_IGD_E_G,		"4 Series"},
+    {PCI_CHIP_G45_G,		"G45/G43"},
+    {PCI_CHIP_Q45_G,		"Q45/Q43"},
+    {PCI_CHIP_G41_G,		"G41"},
+    {PCI_CHIP_B43_G,		"B43"},
+    {PCI_CHIP_IGDNG_D_G,		"Clarkdale"},
+    {PCI_CHIP_IGDNG_M_G,		"Arrandale"},
+    {-1,				NULL}
+};
+SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
+
+#define INTEL_DEVICE_MATCH(d,i) \
+{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
+
+static const struct pci_id_match intel_device_match[] = {
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M, 0 ),
+    { 0, 0, 0 },
+};
+
+static PciChipsets intel_pci_chipsets[] = {
+    {PCI_CHIP_I810,		PCI_CHIP_I810,		NULL},
+    {PCI_CHIP_I810_DC100,	PCI_CHIP_I810_DC100,	NULL},
+    {PCI_CHIP_I810_E,		PCI_CHIP_I810_E,	NULL},
+    {PCI_CHIP_I815,		PCI_CHIP_I815,		NULL},
+    {PCI_CHIP_I830_M,		PCI_CHIP_I830_M,	NULL},
+    {PCI_CHIP_845_G,		PCI_CHIP_845_G,		NULL},
+    {PCI_CHIP_I855_GM,		PCI_CHIP_I855_GM,	NULL},
+    {PCI_CHIP_I865_G,		PCI_CHIP_I865_G,	NULL},
+    {PCI_CHIP_I915_G,		PCI_CHIP_I915_G,	NULL},
+    {PCI_CHIP_E7221_G,		PCI_CHIP_E7221_G,	NULL},
+    {PCI_CHIP_I915_GM,		PCI_CHIP_I915_GM,	NULL},
+    {PCI_CHIP_I945_G,		PCI_CHIP_I945_G,	NULL},
+    {PCI_CHIP_I945_GM,		PCI_CHIP_I945_GM,	NULL},
+    {PCI_CHIP_I945_GME,		PCI_CHIP_I945_GME,	NULL},
+    {PCI_CHIP_IGD_GM,		PCI_CHIP_IGD_GM,	NULL},
+    {PCI_CHIP_IGD_G,		PCI_CHIP_IGD_G,		NULL},
+    {PCI_CHIP_I965_G,		PCI_CHIP_I965_G,	NULL},
+    {PCI_CHIP_G35_G,		PCI_CHIP_G35_G,		NULL},
+    {PCI_CHIP_I965_Q,		PCI_CHIP_I965_Q,	NULL},
+    {PCI_CHIP_I946_GZ,		PCI_CHIP_I946_GZ,	NULL},
+    {PCI_CHIP_I965_GM,		PCI_CHIP_I965_GM,	NULL},
+    {PCI_CHIP_I965_GME,		PCI_CHIP_I965_GME,	NULL},
+    {PCI_CHIP_G33_G,		PCI_CHIP_G33_G,		NULL},
+    {PCI_CHIP_Q35_G,		PCI_CHIP_Q35_G,		NULL},
+    {PCI_CHIP_Q33_G,		PCI_CHIP_Q33_G,		NULL},
+    {PCI_CHIP_GM45_GM,		PCI_CHIP_GM45_GM,	NULL},
+    {PCI_CHIP_IGD_E_G,		PCI_CHIP_IGD_E_G,	NULL},
+    {PCI_CHIP_G45_G,		PCI_CHIP_G45_G,		NULL},
+    {PCI_CHIP_Q45_G,		PCI_CHIP_Q45_G,		NULL},
+    {PCI_CHIP_G41_G,		PCI_CHIP_G41_G,		NULL},
+    {PCI_CHIP_B43_G,		PCI_CHIP_B43_G,		NULL},
+    {PCI_CHIP_IGDNG_D_G,		PCI_CHIP_IGDNG_D_G,	NULL},
+    {PCI_CHIP_IGDNG_M_G,		PCI_CHIP_IGDNG_M_G,	NULL},
+    {-1,				-1, NULL }
+};
+
+void intel_detect_chipset(ScrnInfoPtr scrn,
+			  struct pci_device *pci,
+			  struct intel_chipset *chipset)
+{
+    uint32_t capid;
+
+    switch (DEVICE_ID(pci)) {
+    case PCI_CHIP_I810:
+	chipset->name = "i810";
+	break;
+    case PCI_CHIP_I810_DC100:
+	chipset->name = "i810-dc100";
+	break;
+    case PCI_CHIP_I810_E:
+	chipset->name = "i810e";
+	break;
+    case PCI_CHIP_I815:
+	chipset->name = "i815";
+	break;
+    case PCI_CHIP_I830_M:
+	chipset->name = "830M";
+	break;
+    case PCI_CHIP_845_G:
+	chipset->name = "845G";
+	break;
+    case PCI_CHIP_I855_GM:
+	/* Check capid register to find the chipset variant */
+	pci_device_cfg_read_u32(pci, &capid, I85X_CAPID);
+	chipset->variant =
+	    (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
+	switch (chipset->variant) {
+	case I855_GM:
+	    chipset->name = "855GM";
+	    break;
+	case I855_GME:
+	    chipset->name = "855GME";
+	    break;
+	case I852_GM:
+	    chipset->name = "852GM";
+	    break;
+	case I852_GME:
+	    chipset->name = "852GME";
+	    break;
+	default:
+	    xf86DrvMsg(scrn->scrnIndex, X_INFO,
+		       "Unknown 852GM/855GM variant: 0x%x)\n",
+		       chipset->variant);
+	    chipset->name = "852GM/855GM (unknown variant)";
+	    break;
+	}
+	break;
+    case PCI_CHIP_I865_G:
+	chipset->name = "865G";
+	break;
+    case PCI_CHIP_I915_G:
+	chipset->name = "915G";
+	break;
+    case PCI_CHIP_E7221_G:
+	chipset->name = "E7221 (i915)";
+	break;
+    case PCI_CHIP_I915_GM:
+	chipset->name = "915GM";
+	break;
+    case PCI_CHIP_I945_G:
+	chipset->name = "945G";
+	break;
+    case PCI_CHIP_I945_GM:
+	chipset->name = "945GM";
+	break;
+    case PCI_CHIP_I945_GME:
+	chipset->name = "945GME";
+	break;
+    case PCI_CHIP_IGD_GM:
+	chipset->name = "Pineview GM";
+	break;
+    case PCI_CHIP_IGD_G:
+	chipset->name = "Pineview G";
+	break;
+    case PCI_CHIP_I965_G:
+	chipset->name = "965G";
+	break;
+    case PCI_CHIP_G35_G:
+	chipset->name = "G35";
+	break;
+    case PCI_CHIP_I965_Q:
+	chipset->name = "965Q";
+	break;
+    case PCI_CHIP_I946_GZ:
+	chipset->name = "946GZ";
+	break;
+    case PCI_CHIP_I965_GM:
+	chipset->name = "965GM";
+	break;
+    case PCI_CHIP_I965_GME:
+	chipset->name = "965GME/GLE";
+	break;
+    case PCI_CHIP_G33_G:
+	chipset->name = "G33";
+	break;
+    case PCI_CHIP_Q35_G:
+	chipset->name = "Q35";
+	break;
+    case PCI_CHIP_Q33_G:
+	chipset->name = "Q33";
+	break;
+    case PCI_CHIP_GM45_GM:
+	chipset->name = "GM45";
+	break;
+    case PCI_CHIP_IGD_E_G:
+	chipset->name = "4 Series";
+	break;
+    case PCI_CHIP_G45_G:
+	chipset->name = "G45/G43";
+	break;
+    case PCI_CHIP_Q45_G:
+	chipset->name = "Q45/Q43";
+	break;
+    case PCI_CHIP_G41_G:
+	chipset->name = "G41";
+	break;
+    case PCI_CHIP_B43_G:
+	chipset->name = "B43";
+	break;
+    case PCI_CHIP_IGDNG_D_G:
+	chipset->name = "Clarkdale";
+	break;
+    case PCI_CHIP_IGDNG_M_G:
+	chipset->name = "Arrandale";
+	break;
+    default:
+	chipset->name = "unknown chipset";
+	break;
+    }
+
+    xf86DrvMsg(scrn->scrnIndex, X_INFO,
+	       "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name);
+}
+
+/*
+ * intel_identify --
+ *
+ * Returns the string name for the driver based on the chipset.
+ *
+ */
+static void intel_identify(int flags)
+{
+    xf86PrintChipsets(INTEL_NAME,
+		      "Driver for Intel Integrated Graphics Chipsets",
+		      intel_chipsets);
+}
+
+static Bool intel_driver_func(ScrnInfoPtr pScrn,
+			      xorgDriverFuncOp op,
+			      pointer ptr)
+{
+    xorgHWFlags *flag;
+
+    switch (op) {
+    case GET_REQUIRED_HW_INTERFACES:
+	flag = (CARD32*)ptr;
+#ifdef KMS_ONLY
+	(*flag) = 0;
+#else
+	(*flag) = HW_IO | HW_MMIO;
+#endif
+	return TRUE;
+    default:
+	/* Unknown or deprecated function */
+	return FALSE;
+    }
+}
+
+/*
+ * intel_pci_probe --
+ *
+ * Look through the PCI bus to find cards that are intel boards.
+ * Setup the dispatch table for the rest of the driver functions.
+ *
+ */
+static Bool intel_pci_probe (DriverPtr		driver,
+			     int		entity_num,
+			     struct pci_device	*device,
+			     intptr_t		match_data)
+{
+    ScrnInfoPtr scrn = NULL;
+
+    scrn = xf86ConfigPciEntity(scrn, 0, entity_num, intel_pci_chipsets,
+			       NULL,
+			       NULL, NULL, NULL, NULL);
+    if (scrn != NULL) {
+	scrn->driverVersion = INTEL_VERSION;
+	scrn->driverName = INTEL_DRIVER_NAME;
+	scrn->name = INTEL_NAME;
+	scrn->Probe = NULL;
+
+#if KMS_ONLY
+	intel_init_scrn(scrn);
+#else
+	switch (DEVICE_ID(device)) {
+	case PCI_CHIP_I810:
+	case PCI_CHIP_I810_DC100:
+	case PCI_CHIP_I810_E:
+	case PCI_CHIP_I815:
+	    lg_i810_init(scrn);
+	    break;
+
+	default:
+	    intel_init_scrn(scrn);
+	    break;
+	}
+#endif
+    }
+    return scrn != NULL;
+}
+
+#ifdef XFree86LOADER
+
+static MODULESETUPPROTO(intel_setup);
+
+static XF86ModuleVersionInfo intel_version = {
+    "intel",
+    MODULEVENDORSTRING,
+    MODINFOSTRING1,
+    MODINFOSTRING2,
+    XORG_VERSION_CURRENT,
+    INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
+    ABI_CLASS_VIDEODRV,
+    ABI_VIDEODRV_VERSION,
+    MOD_CLASS_VIDEODRV,
+    {0, 0, 0, 0}
+};
+
+static const OptionInfoRec *
+intel_available_options(int chipid, int busid)
+{
+#if KMS_ONLY
+	return i830_available_options(chipid, busid);
+#else
+    switch (chipid) {
+    case PCI_CHIP_I810:
+    case PCI_CHIP_I810_DC100:
+    case PCI_CHIP_I810_E:
+    case PCI_CHIP_I815:
+	    return lg_i810_available_options(chipid, busid);
+
+    default:
+	    return i830_available_options(chipid, busid);
+    }
+#endif
+}
+
+static DriverRec intel = {
+    INTEL_VERSION,
+    INTEL_DRIVER_NAME,
+    intel_identify,
+    NULL,
+    intel_available_options,
+    NULL,
+    0,
+    intel_driver_func,
+    intel_device_match,
+    intel_pci_probe
+};
+
+static pointer intel_setup(pointer module,
+			   pointer opts,
+			   int *errmaj,
+			   int *errmin)
+{
+    static Bool setupDone = 0;
+
+    /* This module should be loaded only once, but check to be sure.
+    */
+    if (!setupDone) {
+	setupDone = 1;
+	xf86AddDriver(&intel, module, HaveDriverFuncs);
+
+	/*
+	 * The return value must be non-NULL on success even though there
+	 * is no TearDownProc.
+	 */
+	return (pointer) 1;
+    } else {
+	if (errmaj)
+	    *errmaj = LDR_ONCEONLY;
+	return NULL;
+    }
+}
+
+_X_EXPORT XF86ModuleData intelModuleData = { &intel_version, intel_setup, NULL };
+#endif
diff --git a/src/legacy/Makefile.am b/src/legacy/Makefile.am
new file mode 100644
index 00000000..af10c016
--- /dev/null
+++ b/src/legacy/Makefile.am
@@ -0,0 +1,17 @@
+SUBDIRS =
+noinst_LTLIBRARIES = liblegacy.la
+
+NULL:=#
+
+liblegacy_la_SOURCES =
+liblegacy_la_LIBADD =
+
+if ! KMS_ONLY
+SUBDIRS += i810
+liblegacy_la_SOURCES +=
+liblegacy_la_LIBADD += \
+		       i810/liblegacy-i810.la \
+		       $(NULL)
+endif
+
+EXTRA_DIST = README
diff --git a/src/legacy/README b/src/legacy/README
new file mode 100644
index 00000000..65c32f6c
--- /dev/null
+++ b/src/legacy/README
@@ -0,0 +1,6 @@
+Welcome to the attic!
+
+The code contained herein is no longer under active development and is not the
+target for new features or other improvements. Instead, we have placed it here
+to mature gracefully and still provide hardware compatibility for those
+antiquated devices that turn up when you least expect them.
diff --git a/src/legacy/i810/Makefile.am b/src/legacy/i810/Makefile.am
new file mode 100644
index 00000000..aab7f512
--- /dev/null
+++ b/src/legacy/i810/Makefile.am
@@ -0,0 +1,33 @@
+SUBDIRS = xvmc
+
+noinst_LTLIBRARIES = liblegacy-i810.la
+
+AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ @PCIACCESS_CFLAGS@ -I$(top_srcdir)/src
+
+liblegacy_i810_la_SOURCES = \
+         i810_accel.c \
+         i810_common.h \
+         i810_cursor.c \
+         i810_dga.c \
+         i810_driver.c \
+         i810.h \
+         i810_io.c \
+         i810_memory.c \
+         i810_reg.h \
+         i810_ring.h \
+         i810_video.c \
+         i810_wmark.c
+
+if DRI
+liblegacy_i810_la_SOURCES +=\
+         i810_dri.c \
+         i810_dri.h \
+	 $(NULL)
+endif
+
+if XVMC
+liblegacy_i810_la_SOURCES += \
+	i810_hwmc.h \
+	i810_hwmc.c \
+	$(NULL)
+endif
diff --git a/src/i810.h b/src/legacy/i810/i810.h
index 93b8b760..b39cfff3 100644
--- a/src/i810.h
+++ b/src/legacy/i810/i810.h
@@ -61,16 +61,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "i810_dri.h"
 #endif
 
-#include "common.h"
+#include "i810_common.h"
 #include "i810_ring.h"
 
-#define I810_VERSION 4000
-#define I810_NAME "intel"
-#define I810_DRIVER_NAME "intel"
-
-#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
-#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
-#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
+#include "intel_driver.h"
 
 /* HWMC Surfaces */
 #define I810_MAX_SURFACES 7
diff --git a/src/i810_accel.c b/src/legacy/i810/i810_accel.c
index ae4a6544..ae4a6544 100644
--- a/src/i810_accel.c
+++ b/src/legacy/i810/i810_accel.c
diff --git a/src/i810_common.h b/src/legacy/i810/i810_common.h
index 29be444b..ea28f4ab 100644
--- a/src/i810_common.h
+++ b/src/legacy/i810/i810_common.h
@@ -35,6 +35,138 @@
 #ifndef _I810_COMMON_H_
 #define _I810_COMMON_H_
 
+/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
+#if !defined(__GNUC__) && !defined(__FUNCTION__)
+# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */
+#  define __FUNCTION__ __func__
+# else
+#  define __FUNCTION__ ""
+# endif
+#endif
+
+#define PFX __FILE__,__LINE__,__FUNCTION__
+#define FUNCTION_NAME __FUNCTION__
+
+#define KB(x) ((x) * 1024)
+#define MB(x) ((x) * KB(1024))
+
+/* Using usleep() makes things noticably slow. */
+#if 0
+#define DELAY(x) usleep(x)
+#else
+#define DELAY(x) do {;} while (0)
+#endif
+
+#define PrintErrorState I810PrintErrorState
+#define WaitRingFunc I810WaitLpRing
+#define RecPtr pI810
+
+static inline void memset_volatile(volatile void *b, int c, size_t len)
+{
+    int i;
+    
+    for (i = 0; i < len; i++)
+	((volatile char *)b)[i] = c;
+}
+
+static inline void memcpy_volatile(volatile void *dst, const void *src,
+				   size_t len)
+{
+    int i;
+    
+    for (i = 0; i < len; i++)
+	((volatile char *)dst)[i] = ((volatile char *)src)[i];
+}
+
+/* Memory mapped register access macros */
+#define INREG8(addr)        *(volatile uint8_t *)(RecPtr->MMIOBase + (addr))
+#define INREG16(addr)       *(volatile uint16_t *)(RecPtr->MMIOBase + (addr))
+#define INREG(addr)         *(volatile uint32_t *)(RecPtr->MMIOBase + (addr))
+#define INGTT(addr)         *(volatile uint32_t *)(RecPtr->GTTBase + (addr))
+#define POSTING_READ(addr)  (void)INREG(addr)
+
+#define OUTREG8(addr, val) do {						\
+   *(volatile uint8_t *)(RecPtr->MMIOBase  + (addr)) = (val);		\
+   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
+      ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
+		(unsigned long)(val), FUNCTION_NAME);			\
+   }									\
+} while (0)
+
+#define OUTREG16(addr, val) do {					\
+   *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
+   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
+      ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
+		(unsigned long)(val), FUNCTION_NAME);			\
+   }									\
+} while (0)
+
+#define OUTREG(addr, val) do {						\
+   *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
+   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
+      ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
+		(unsigned long)(val), FUNCTION_NAME);			\
+   }									\
+} while (0)
+
+/* To remove all debugging, make sure I810_DEBUG is defined as a
+ * preprocessor symbol, and equal to zero.
+ */
+#if 1
+#define I810_DEBUG 0
+#endif
+#ifndef I810_DEBUG
+#warning "Debugging enabled - expect reduced performance"
+extern int I810_DEBUG;
+#endif
+
+#define DEBUG_VERBOSE_ACCEL  0x1
+#define DEBUG_VERBOSE_SYNC   0x2
+#define DEBUG_VERBOSE_VGA    0x4
+#define DEBUG_VERBOSE_RING   0x8
+#define DEBUG_VERBOSE_OUTREG 0x10
+#define DEBUG_VERBOSE_MEMORY 0x20
+#define DEBUG_VERBOSE_CURSOR 0x40
+#define DEBUG_ALWAYS_SYNC    0x80
+#define DEBUG_VERBOSE_DRI    0x100
+#define DEBUG_VERBOSE_BIOS   0x200
+
+/* Size of the mmio region.
+ */
+#define I810_REG_SIZE 0x80000
+
+#define GTT_PAGE_SIZE			KB(4)
+#define ROUND_TO(x, y)			(((x) + (y) - 1) / (y) * (y))
+#define ROUND_DOWN_TO(x, y)		((x) / (y) * (y))
+#define ROUND_TO_PAGE(x)		ROUND_TO((x), GTT_PAGE_SIZE)
+#define ROUND_TO_MB(x)			ROUND_TO((x), MB(1))
+#define PRIMARY_RINGBUFFER_SIZE		KB(128)
+#define MIN_SCRATCH_BUFFER_SIZE		KB(16)
+#define MAX_SCRATCH_BUFFER_SIZE		KB(64)
+#define HWCURSOR_SIZE			GTT_PAGE_SIZE
+#define HWCURSOR_SIZE_ARGB		GTT_PAGE_SIZE * 4
+
+/* Use a 64x64 HW cursor */
+#define I810_CURSOR_X			64
+#define I810_CURSOR_Y			I810_CURSOR_X
+
+#define PIPE_NAME(n)			('A' + (n))
+
+extern struct pci_device *
+intel_host_bridge (void);
+
+/**
+ * Hints to CreatePixmap to tell the driver how the pixmap is going to be
+ * used.
+ *
+ * Compare to CREATE_PIXMAP_USAGE_* in the server.
+ */
+enum {
+	INTEL_CREATE_PIXMAP_TILING_X = 0x10000000,
+	INTEL_CREATE_PIXMAP_TILING_Y,
+	INTEL_CREATE_PIXMAP_TILING_NONE,
+};
+
 #ifndef _I810_DEFINES_
 #define _I810_DEFINES_
 #define I810_USE_BATCH 1
diff --git a/src/i810_cursor.c b/src/legacy/i810/i810_cursor.c
index 898a1364..898a1364 100644
--- a/src/i810_cursor.c
+++ b/src/legacy/i810/i810_cursor.c
diff --git a/src/i810_dga.c b/src/legacy/i810/i810_dga.c
index 52a01b76..d9ddda04 100644
--- a/src/i810_dga.c
+++ b/src/legacy/i810/i810_dga.c
@@ -78,8 +78,6 @@ I810DGAInit(ScreenPtr pScreen)
    int Bpp = pScrn->bitsPerPixel >> 3;
    int num = 0;
 
-   MARKER();
-
    pMode = firstMode = pScrn->modes;
 
    while (pMode) {
@@ -148,10 +146,7 @@ I810_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode)
    int index = pScrn->pScreen->myNum;
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    if (!pMode) {			/* restore the original mode */
-      DPRINTF(PFX, "Restoring original mode (from DGA mode)\n");
       if (pI810->DGAactive) {
 	 pScrn->currentMode = I810SavedDGAModes[index];
 	 pScrn->SwitchMode(index, pScrn->currentMode, 0);
@@ -160,7 +155,6 @@ I810_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode)
       }
    } else {
       if (!pI810->DGAactive) {
-	 DPRINTF(PFX, "Setting DGA mode\n");
 	 I810SavedDGAModes[index] = pScrn->currentMode;
 	 pI810->DGAactive = TRUE;
       }
@@ -176,8 +170,6 @@ I810_GetViewport(ScrnInfoPtr pScrn)
 {
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    return pI810->DGAViewportStatus;
 }
 
@@ -187,8 +179,6 @@ I810_SetViewport(ScrnInfoPtr pScrn, int x, int y, int flags)
    I810Ptr pI810 = I810PTR(pScrn);
    vgaHWPtr hwp = VGAHWPTR(pScrn);
 
-   MARKER();
-
    pScrn->AdjustFrame(pScrn->pScreen->myNum, x, y, flags);
 
    /* wait for retrace */
@@ -204,8 +194,6 @@ I810_FillRect(ScrnInfoPtr pScrn,
 {
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    if (pI810->AccelInfoRec) {
       (*pI810->AccelInfoRec->SetupForSolidFill) (pScrn, color, GXcopy, ~0);
       (*pI810->AccelInfoRec->SubsequentSolidFillRect) (pScrn, x, y, w, h);
@@ -218,8 +206,6 @@ I810_Sync(ScrnInfoPtr pScrn)
 {
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    if (pI810->AccelInfoRec) {
       (*pI810->AccelInfoRec->Sync) (pScrn);
    }
@@ -231,8 +217,6 @@ I810_BlitRect(ScrnInfoPtr pScrn,
 {
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    if (pI810->AccelInfoRec) {
       int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1;
       int ydir = (srcy < dsty) ? -1 : 1;
@@ -252,8 +236,6 @@ I810_BlitTransRect(ScrnInfoPtr pScrn,
 		   int w, int h, int dstx, int dsty, unsigned long color)
 {
 
-   MARKER();
-
    /* this one should be separate since the XAA function would
     * prohibit usage of ~0 as the key */
 }
@@ -266,17 +248,11 @@ I810_OpenFramebuffer(ScrnInfoPtr pScrn,
 {
    I810Ptr pI810 = I810PTR(pScrn);
 
-   MARKER();
-
    *name = NULL;			/* no special device */
    *mem = (unsigned char *)pI810->LinearAddr;
    *size = pI810->FbMapSize;
    *offset = 0;
    *flags = DGA_NEED_ROOT;
 
-   DPRINTF(PFX,
-	   " mem == 0x%.8x (pI810->LinearAddr)\n"
-	   "size == %lu (pI810->FbMapSize)\n", *mem, *size);
-
    return TRUE;
 }
diff --git a/src/i810_dri.c b/src/legacy/i810/i810_dri.c
index ecb94af1..ecb94af1 100644
--- a/src/i810_dri.c
+++ b/src/legacy/i810/i810_dri.c
diff --git a/src/i810_dri.h b/src/legacy/i810/i810_dri.h
index 16b6f087..16b6f087 100644
--- a/src/i810_dri.h
+++ b/src/legacy/i810/i810_dri.h
diff --git a/src/i810_driver.c b/src/legacy/i810/i810_driver.c
index 088b5524..3fc9d044 100644
--- a/src/i810_driver.c
+++ b/src/legacy/i810/i810_driver.c
@@ -70,22 +70,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "vbe.h"
 
 #include "i810.h"
-#include "i830.h"
 
 #ifdef XF86DRI
 #include "dri.h"
 #endif
 
-/* Required Functions: */
+#include "../legacy.h"
 
-static void I810Identify(int flags);
-static Bool I810DriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer ptr);
-static Bool intel_pci_probe (DriverPtr		drv,
-			     int		entity_num,
-			     struct pci_device	*dev,
-			     intptr_t		match_data);
-
-#ifndef I830_ONLY
 static Bool I810PreInit(ScrnInfoPtr pScrn, int flags);
 static Bool I810ScreenInit(int Index, ScreenPtr pScreen, int argc,
 			   char **argv);
@@ -99,146 +90,7 @@ static void I810DisplayPowerManagementSet(ScrnInfoPtr pScrn,
 					  int flags);
 static ModeStatus I810ValidMode(int scrnIndex, DisplayModePtr mode,
 				Bool verbose, int flags);
-#endif /* I830_ONLY */
-
-#define INTEL_DEVICE_MATCH(d,i) \
-    { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
-
-static const struct pci_id_match intel_device_match[] = {
-#ifndef I830_ONLY
-   INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
-#endif
-   INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE, 0 ),
-   INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M, 0 ),
-    { 0, 0, 0 },
-};
-
-_X_EXPORT DriverRec I810 = {
-   I810_VERSION,
-   I810_DRIVER_NAME,
-   I810Identify,
-   NULL,
-   I810AvailableOptions,
-   NULL,
-   0,
-   I810DriverFunc,
-   intel_device_match,
-   intel_pci_probe
-};
-
-/* *INDENT-OFF* */
-/* Chipsets */
-static SymTabRec I810Chipsets[] = {
-#ifndef I830_ONLY
-   {PCI_CHIP_I810,		"i810"},
-   {PCI_CHIP_I810_DC100,	"i810-dc100"},
-   {PCI_CHIP_I810_E,		"i810e"},
-   {PCI_CHIP_I815,		"i815"},
-#endif
-   {PCI_CHIP_I830_M,		"i830M"},
-   {PCI_CHIP_845_G,		"845G"},
-   {PCI_CHIP_I855_GM,		"852GM/855GM"},
-   {PCI_CHIP_I865_G,		"865G"},
-   {PCI_CHIP_I915_G,		"915G"},
-   {PCI_CHIP_E7221_G,		"E7221 (i915)"},
-   {PCI_CHIP_I915_GM,		"915GM"},
-   {PCI_CHIP_I945_G,		"945G"},
-   {PCI_CHIP_I945_GM,		"945GM"},
-   {PCI_CHIP_I945_GME,		"945GME"},
-   {PCI_CHIP_IGD_GM,		"Pineview GM"},
-   {PCI_CHIP_IGD_G,		"Pineview G"},
-   {PCI_CHIP_I965_G,		"965G"},
-   {PCI_CHIP_G35_G,		"G35"},
-   {PCI_CHIP_I965_Q,		"965Q"},
-   {PCI_CHIP_I946_GZ,		"946GZ"},
-   {PCI_CHIP_I965_GM,		"965GM"},
-   {PCI_CHIP_I965_GME,		"965GME/GLE"},
-   {PCI_CHIP_G33_G,		"G33"},
-   {PCI_CHIP_Q35_G,		"Q35"},
-   {PCI_CHIP_Q33_G,		"Q33"},
-   {PCI_CHIP_GM45_GM,		"GM45"},
-   {PCI_CHIP_IGD_E_G,		"4 Series"},
-   {PCI_CHIP_G45_G,		"G45/G43"},
-   {PCI_CHIP_Q45_G,		"Q45/Q43"},
-   {PCI_CHIP_G41_G,		"G41"},
-   {PCI_CHIP_B43_G,		"B43"},
-   {PCI_CHIP_IGDNG_D_G,		"Clarkdale"},
-   {PCI_CHIP_IGDNG_M_G,		"Arrandale"},
-   {-1,				NULL}
-};
 
-static PciChipsets I810PciChipsets[] = {
-#ifndef I830_ONLY
-   {PCI_CHIP_I810,		PCI_CHIP_I810,		NULL},
-   {PCI_CHIP_I810_DC100,	PCI_CHIP_I810_DC100,	NULL},
-   {PCI_CHIP_I810_E,		PCI_CHIP_I810_E,	NULL},
-   {PCI_CHIP_I815,		PCI_CHIP_I815,		NULL},
-#endif
-   {PCI_CHIP_I830_M,		PCI_CHIP_I830_M,	NULL},
-   {PCI_CHIP_845_G,		PCI_CHIP_845_G,		NULL},
-   {PCI_CHIP_I855_GM,		PCI_CHIP_I855_GM,	NULL},
-   {PCI_CHIP_I865_G,		PCI_CHIP_I865_G,	NULL},
-   {PCI_CHIP_I915_G,		PCI_CHIP_I915_G,	NULL},
-   {PCI_CHIP_E7221_G,		PCI_CHIP_E7221_G,	NULL},
-   {PCI_CHIP_I915_GM,		PCI_CHIP_I915_GM,	NULL},
-   {PCI_CHIP_I945_G,		PCI_CHIP_I945_G,	NULL},
-   {PCI_CHIP_I945_GM,		PCI_CHIP_I945_GM,	NULL},
-   {PCI_CHIP_I945_GME,		PCI_CHIP_I945_GME,	NULL},
-   {PCI_CHIP_IGD_GM,		PCI_CHIP_IGD_GM,	NULL},
-   {PCI_CHIP_IGD_G,		PCI_CHIP_IGD_G,		NULL},
-   {PCI_CHIP_I965_G,		PCI_CHIP_I965_G,	NULL},
-   {PCI_CHIP_G35_G,		PCI_CHIP_G35_G,		NULL},
-   {PCI_CHIP_I965_Q,		PCI_CHIP_I965_Q,	NULL},
-   {PCI_CHIP_I946_GZ,		PCI_CHIP_I946_GZ,	NULL},
-   {PCI_CHIP_I965_GM,		PCI_CHIP_I965_GM,	NULL},
-   {PCI_CHIP_I965_GME,		PCI_CHIP_I965_GME,	NULL},
-   {PCI_CHIP_G33_G,		PCI_CHIP_G33_G,		NULL},
-   {PCI_CHIP_Q35_G,		PCI_CHIP_Q35_G,		NULL},
-   {PCI_CHIP_Q33_G,		PCI_CHIP_Q33_G,		NULL},
-   {PCI_CHIP_GM45_GM,		PCI_CHIP_GM45_GM,	NULL},
-   {PCI_CHIP_IGD_E_G,		PCI_CHIP_IGD_E_G,	NULL},
-   {PCI_CHIP_G45_G,		PCI_CHIP_G45_G,		NULL},
-   {PCI_CHIP_Q45_G,		PCI_CHIP_Q45_G,		NULL},
-   {PCI_CHIP_G41_G,		PCI_CHIP_G41_G,		NULL},
-   {PCI_CHIP_B43_G,		PCI_CHIP_B43_G,		NULL},
-   {PCI_CHIP_IGDNG_D_G,		PCI_CHIP_IGDNG_D_G,	NULL},
-   {PCI_CHIP_IGDNG_M_G,		PCI_CHIP_IGDNG_M_G,	NULL},
-   {-1,				-1, NULL }
-};
-
-#ifndef I830_ONLY
 typedef enum {
    OPTION_NOACCEL,
    OPTION_SW_CURSOR,
@@ -266,7 +118,6 @@ static const OptionInfoRec I810Options[] = {
    {-1,				NULL,		OPTV_NONE,	{0}, FALSE}
 };
 /* *INDENT-ON* */
-#endif
 
 #ifndef I810_DEBUG
 int I810_DEBUG = (0
@@ -281,7 +132,6 @@ int I810_DEBUG = (0
       );
 #endif
 
-#ifndef I830_ONLY
 #ifdef XF86DRI
 static int i810_pitches[] = {
    512,
@@ -291,57 +141,9 @@ static int i810_pitches[] = {
    0
 };
 #endif
-#endif
 
 int I830EntityIndex = -1;
 
-#ifdef XFree86LOADER
-
-static MODULESETUPPROTO(i810Setup);
-
-static XF86ModuleVersionInfo intelVersRec = {
-   "intel",
-   MODULEVENDORSTRING,
-   MODINFOSTRING1,
-   MODINFOSTRING2,
-   XORG_VERSION_CURRENT,
-   INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
-   ABI_CLASS_VIDEODRV,
-   ABI_VIDEODRV_VERSION,
-   MOD_CLASS_VIDEODRV,
-   {0, 0, 0, 0}
-};
-
-_X_EXPORT XF86ModuleData intelModuleData = { &intelVersRec, i810Setup, NULL };
-
-static pointer
-i810Setup(pointer module, pointer opts, int *errmaj, int *errmin)
-{
-   static Bool setupDone = 0;
-
-   /* This module should be loaded only once, but check to be sure.
-    */
-   if (!setupDone) {
-      setupDone = 1;
-      xf86AddDriver(&I810, module,
-		    HaveDriverFuncs
-		    );
-
-      /*
-       * The return value must be non-NULL on success even though there
-       * is no TearDownProc.
-       */
-      return (pointer) 1;
-   } else {
-      if (errmaj)
-	 *errmaj = LDR_ONCEONLY;
-      return NULL;
-   }
-}
-
-#endif
-
-#ifndef I830_ONLY
 /*
  * I810GetRec and I810FreeRec --
  *
@@ -369,55 +171,6 @@ I810FreeRec(ScrnInfoPtr pScrn)
    free(pScrn->driverPrivate);
    pScrn->driverPrivate = NULL;
 }
-#endif
-
-/*
- * I810Identify --
- *
- * Returns the string name for the driver based on the chipset. In this
- * case it will always be an I810, so we can return a static string.
- *
- */
-static void
-I810Identify(int flags)
-{
-   xf86PrintChipsets(I810_NAME, "Driver for Intel Integrated Graphics Chipsets",
-		     I810Chipsets);
-}
-
-const OptionInfoRec *
-I810AvailableOptions(int chipid, int busid)
-{
-#ifndef I830_ONLY
-   const OptionInfoRec *pOptions;
-
-   if ((pOptions = I830AvailableOptions(chipid, busid)))
-      return pOptions;
-   return I810Options;
-#else
-   return I830AvailableOptions(chipid, busid);
-#endif
-}
-
-static Bool
-I810DriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer ptr)
-{
-    xorgHWFlags *flag;
-
-    switch (op) {
-        case GET_REQUIRED_HW_INTERFACES:
-            flag = (CARD32*)ptr;
-#ifdef KMS_ONLY
-            (*flag) = 0;
-#else
-	    (*flag) = HW_IO | HW_MMIO;
-#endif
-            return TRUE;
-        default:
-	    /* Unknown or deprecated function */
-            return FALSE;
-    }
-}
 
 struct pci_device *
 intel_host_bridge (void)
@@ -434,55 +187,6 @@ intel_host_bridge (void)
     return bridge;
 }
 
-/*
- * intel_pci_probe --
- *
- * Look through the PCI bus to find cards that are intel boards.
- * Setup the dispatch table for the rest of the driver functions.
- *
- */
-static Bool intel_pci_probe (DriverPtr		driver,
-			     int		entity_num,
-			     struct pci_device	*device,
-			     intptr_t		match_data)
-{
-    ScrnInfoPtr	    scrn = NULL;
-
-    scrn = xf86ConfigPciEntity (scrn, 0, entity_num, I810PciChipsets,
-				NULL,
-				NULL, NULL, NULL, NULL);
-    if (scrn != NULL)
-    {
-	scrn->driverVersion = I810_VERSION;
-	scrn->driverName = I810_DRIVER_NAME;
-	scrn->name = I810_NAME;
-	scrn->Probe = NULL;
-
-	switch (DEVICE_ID(device)) {
-#ifndef I830_ONLY
-	case PCI_CHIP_I810:
-	case PCI_CHIP_I810_DC100:
-	case PCI_CHIP_I810_E:
-	case PCI_CHIP_I815:
-	    scrn->PreInit = I810PreInit;
-	    scrn->ScreenInit = I810ScreenInit;
-	    scrn->SwitchMode = I810SwitchMode;
-	    scrn->AdjustFrame = I810AdjustFrame;
-	    scrn->EnterVT = I810EnterVT;
-	    scrn->LeaveVT = I810LeaveVT;
-	    scrn->FreeScreen = I810FreeScreen;
-	    scrn->ValidMode = I810ValidMode;
-	    break;
-#endif
-	default:
-	    intel_init_scrn(scrn);
-	    break;
-	}
-    }
-    return scrn != NULL;
-}
-
-#ifndef I830_ONLY
 static void
 I810ProbeDDC(ScrnInfoPtr pScrn, int index)
 {
@@ -539,6 +243,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
    rgb defaultWeight = { 0, 0, 0 };
    int mem;
    Bool enable;
+   struct intel_chipset chipset;
 
    if (pScrn->numEntities != 1)
       return FALSE;
@@ -676,6 +381,8 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
    /* We have to use PIO to probe, because we haven't mapped yet */
    I810SetPIOAccess(pI810);
 
+   intel_detect_chipset(pScrn, pI810->PciInfo, &chipset);
+
    /*
     * Set the Chipset and ChipRev, allowing config file entries to
     * override.
@@ -684,14 +391,14 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
       pScrn->chipset = pI810->pEnt->device->chipset;
       from = X_CONFIG;
    } else if (pI810->pEnt->device->chipID >= 0) {
-      pScrn->chipset = (char *)xf86TokenToString(I810Chipsets,
+      pScrn->chipset = (char *)xf86TokenToString(intel_chipsets,
 						 pI810->pEnt->device->chipID);
       from = X_CONFIG;
       xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
 		 pI810->pEnt->device->chipID);
    } else {
       from = X_PROBED;
-      pScrn->chipset = (char *)xf86TokenToString(I810Chipsets,
+      pScrn->chipset = (char *)xf86TokenToString(intel_chipsets,
 						 DEVICE_ID(pI810->PciInfo));
    }
    if (pI810->pEnt->device->chipRev >= 0) {
@@ -1843,19 +1550,10 @@ I810AllocateFront(ScrnInfoPtr pScrn)
       xf86DrvMsg(pScrn->scrnIndex,
 		 X_WARNING, "Framebuffer allocation failed\n");
       return FALSE;
-   } else
-      DPRINTF(PFX,
-	      "Frame buffer at 0x%.8x (%luk, %lu bytes)\n",
-	      pI810->FrontBuffer.Start,
-	      pI810->FrontBuffer.Size / 1024, pI810->FrontBuffer.Size);
+   }
 
    memset(pI810->LpRing, 0, sizeof(I810RingBuffer));
    if (I810AllocLow(&(pI810->LpRing->mem), &(pI810->SysMem), 16 * 4096)) {
-      DPRINTF(PFX,
-	      "Ring buffer at 0x%.8x (%luk, %lu bytes)\n",
-	      pI810->LpRing->mem.Start,
-	      pI810->LpRing->mem.Size / 1024, pI810->LpRing->mem.Size);
-
       pI810->LpRing->tail_mask = pI810->LpRing->mem.Size - 1;
       pI810->LpRing->virtual_start = pI810->FbBase + pI810->LpRing->mem.Start;
       pI810->LpRing->head = 0;
@@ -1869,11 +1567,6 @@ I810AllocateFront(ScrnInfoPtr pScrn)
 
    if (I810AllocLow(&pI810->Scratch, &(pI810->SysMem), 64 * 1024) ||
        I810AllocLow(&pI810->Scratch, &(pI810->SysMem), 16 * 1024)) {
-      DPRINTF(PFX,
-	      "Scratch memory at 0x%.8x (%luk, %lu bytes)\n",
-	      pI810->Scratch.Start,
-	      pI810->Scratch.Size / 1024, pI810->Scratch.Size);
-
       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocated Scratch Memory\n");
    } else {
       xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -2407,4 +2100,22 @@ I810DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode,
    /* Set the DPMS mode */
    OUTREG8(DPMS_SYNC_SELECT, DPMSSyncSelect);
 }
-#endif /* I830_ONLY */
+
+const OptionInfoRec *
+lg_i810_available_options(int chipid, int busid)
+{
+   return I810Options;
+}
+
+
+void lg_i810_init(ScrnInfoPtr scrn)
+{
+    scrn->PreInit = I810PreInit;
+    scrn->ScreenInit = I810ScreenInit;
+    scrn->SwitchMode = I810SwitchMode;
+    scrn->AdjustFrame = I810AdjustFrame;
+    scrn->EnterVT = I810EnterVT;
+    scrn->LeaveVT = I810LeaveVT;
+    scrn->FreeScreen = I810FreeScreen;
+    scrn->ValidMode = I810ValidMode;
+}
diff --git a/src/i810_hwmc.c b/src/legacy/i810/i810_hwmc.c
index 724e1bea..724e1bea 100644
--- a/src/i810_hwmc.c
+++ b/src/legacy/i810/i810_hwmc.c
diff --git a/src/i810_io.c b/src/legacy/i810/i810_io.c
index a6cf3058..a6cf3058 100644
--- a/src/i810_io.c
+++ b/src/legacy/i810/i810_io.c
diff --git a/src/i810_memory.c b/src/legacy/i810/i810_memory.c
index f57ddbe2..f57ddbe2 100644
--- a/src/i810_memory.c
+++ b/src/legacy/i810/i810_memory.c
diff --git a/src/i810_reg.h b/src/legacy/i810/i810_reg.h
index 191ddb2a..2b679346 100644
--- a/src/i810_reg.h
+++ b/src/legacy/i810/i810_reg.h
@@ -2445,14 +2445,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define INTEL_GMCH_GMS_STOLEN_352M		(0xd << 4)
 
 
-#define I85X_CAPID			0x44
-#define I85X_VARIANT_MASK			0x7
-#define I85X_VARIANT_SHIFT			5
-#define I855_GME				0x0
-#define I855_GM					0x4
-#define I852_GME				0x2
-#define I852_GM					0x5
-
 #define I915_GCFGC			0xf0
 #define I915_LOW_FREQUENCY_ENABLE		(1 << 7)
 #define I915_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
@@ -2574,247 +2566,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define ENABLE_FOG_CONST	(1<<24)
 #define ENABLE_FOG_DENSITY	(1<<23)
 
-/*
- * New regs for broadwater -- we need to split this file up sensibly somehow.
- */
-#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
-					   ((Pipeline) << 27) | \
-					   ((Opcode) << 24) | \
-					   ((Subopcode) << 16))
-
-#define BRW_URB_FENCE				BRW_3D(0, 0, 0)
-#define BRW_CS_URB_STATE			BRW_3D(0, 0, 1)
-#define BRW_CONSTANT_BUFFER			BRW_3D(0, 0, 2)
-#define BRW_STATE_PREFETCH			BRW_3D(0, 0, 3)
-
-#define BRW_STATE_BASE_ADDRESS			BRW_3D(0, 1, 1)
-#define BRW_STATE_SIP				BRW_3D(0, 1, 2)
-#define BRW_PIPELINE_SELECT			BRW_3D(0, 1, 4)
-
-#define NEW_PIPELINE_SELECT			BRW_3D(1, 1, 4)
-
-#define BRW_MEDIA_STATE_POINTERS		BRW_3D(2, 0, 0)
-#define BRW_MEDIA_OBJECT			BRW_3D(2, 1, 0)
-
-#define BRW_3DSTATE_PIPELINED_POINTERS		BRW_3D(3, 0, 0)
-#define BRW_3DSTATE_BINDING_TABLE_POINTERS	BRW_3D(3, 0, 1)
-#define BRW_3DSTATE_VERTEX_BUFFERS		BRW_3D(3, 0, 8)
-#define BRW_3DSTATE_VERTEX_ELEMENTS		BRW_3D(3, 0, 9)
-#define BRW_3DSTATE_INDEX_BUFFER		BRW_3D(3, 0, 0xa)
-#define BRW_3DSTATE_VF_STATISTICS		BRW_3D(3, 0, 0xb)
-
-#define BRW_3DSTATE_DRAWING_RECTANGLE		BRW_3D(3, 1, 0)
-#define BRW_3DSTATE_CONSTANT_COLOR		BRW_3D(3, 1, 1)
-#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD	BRW_3D(3, 1, 2)
-#define BRW_3DSTATE_CHROMA_KEY			BRW_3D(3, 1, 4)
-#define BRW_3DSTATE_DEPTH_BUFFER		BRW_3D(3, 1, 5)
-#define BRW_3DSTATE_POLY_STIPPLE_OFFSET		BRW_3D(3, 1, 6)
-#define BRW_3DSTATE_POLY_STIPPLE_PATTERN	BRW_3D(3, 1, 7)
-#define BRW_3DSTATE_LINE_STIPPLE		BRW_3D(3, 1, 8)
-#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP	BRW_3D(3, 1, 9)
-/* These two are BLC and CTG only, not BW or CL */
-#define BRW_3DSTATE_AA_LINE_PARAMS		BRW_3D(3, 1, 0xa)
-#define BRW_3DSTATE_GS_SVB_INDEX		BRW_3D(3, 1, 0xb)
-
-#define BRW_PIPE_CONTROL			BRW_3D(3, 2, 0)
-
-#define BRW_3DPRIMITIVE				BRW_3D(3, 3, 0)
-
-#define PIPELINE_SELECT_3D		0
-#define PIPELINE_SELECT_MEDIA		1
-
-#define UF0_CS_REALLOC			(1 << 13)
-#define UF0_VFE_REALLOC			(1 << 12)
-#define UF0_SF_REALLOC			(1 << 11)
-#define UF0_CLIP_REALLOC		(1 << 10)
-#define UF0_GS_REALLOC			(1 << 9)
-#define UF0_VS_REALLOC			(1 << 8)
-#define UF1_CLIP_FENCE_SHIFT		20
-#define UF1_GS_FENCE_SHIFT		10
-#define UF1_VS_FENCE_SHIFT		0
-#define UF2_CS_FENCE_SHIFT		20
-#define UF2_VFE_FENCE_SHIFT		10
-#define UF2_SF_FENCE_SHIFT		0
-
-/* for BRW_STATE_BASE_ADDRESS */
-#define BASE_ADDRESS_MODIFY		(1 << 0)
-
-/* for BRW_3DSTATE_PIPELINED_POINTERS */
-#define BRW_GS_DISABLE		       0
-#define BRW_GS_ENABLE		       1
-#define BRW_CLIP_DISABLE	       0
-#define BRW_CLIP_ENABLE		       1
-
-/* for BRW_PIPE_CONTROL */
-#define BRW_PIPE_CONTROL_NOWRITE       (0 << 14)
-#define BRW_PIPE_CONTROL_WRITE_QWORD   (1 << 14)
-#define BRW_PIPE_CONTROL_WRITE_DEPTH   (2 << 14)
-#define BRW_PIPE_CONTROL_WRITE_TIME    (3 << 14)
-#define BRW_PIPE_CONTROL_DEPTH_STALL   (1 << 13)
-#define BRW_PIPE_CONTROL_WC_FLUSH      (1 << 12)
-#define BRW_PIPE_CONTROL_IS_FLUSH      (1 << 11)
-#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
-#define BRW_PIPE_CONTROL_GLOBAL_GTT    (1 << 2)
-#define BRW_PIPE_CONTROL_LOCAL_PGTT    (0 << 2)
-
-/* VERTEX_BUFFER_STATE Structure */
-#define VB0_BUFFER_INDEX_SHIFT		27
-#define VB0_VERTEXDATA			(0 << 26)
-#define VB0_INSTANCEDATA		(1 << 26)
-#define VB0_BUFFER_PITCH_SHIFT		0
-
-/* VERTEX_ELEMENT_STATE Structure */
-#define VE0_VERTEX_BUFFER_INDEX_SHIFT	27
-#define VE0_VALID			(1 << 26)
-#define VE0_FORMAT_SHIFT		16
-#define VE0_OFFSET_SHIFT		0
-#define VE1_VFCOMPONENT_0_SHIFT		28
-#define VE1_VFCOMPONENT_1_SHIFT		24
-#define VE1_VFCOMPONENT_2_SHIFT		20
-#define VE1_VFCOMPONENT_3_SHIFT		16
-#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT	0
-
-/* 3DPRIMITIVE bits */
-#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
-#define BRW_3DPRIMITIVE_VERTEX_RANDOM	  (1 << 15)
-/* Primitive types are in brw_defines.h */
-#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT	  10
-
-#define BRW_SVG_CTL		       0x7400
-
-#define BRW_SVG_CTL_GS_BA	       (0 << 8)
-#define BRW_SVG_CTL_SS_BA	       (1 << 8)
-#define BRW_SVG_CTL_IO_BA	       (2 << 8)
-#define BRW_SVG_CTL_GS_AUB	       (3 << 8)
-#define BRW_SVG_CTL_IO_AUB	       (4 << 8)
-#define BRW_SVG_CTL_SIP		       (5 << 8)
-
-#define BRW_SVG_RDATA		       0x7404
-#define BRW_SVG_WORK_CTL	       0x7408
-
-#define BRW_VF_CTL		       0x7500
-
-#define BRW_VF_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
-#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID	   (0 << 8)
-#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG	   (1 << 8)
-#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE   (0 << 4)
-#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX	   (1 << 4)
-#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES	   (1 << 3)
-#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE	   (1 << 2)
-#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE	   (1 << 1)
-#define BRW_VF_CTL_SNAPSHOT_ENABLE	     	   (1 << 0)
-
-#define BRW_VF_STRG_VAL		       0x7504
-#define BRW_VF_STR_VL_OVR	       0x7508
-#define BRW_VF_VC_OVR		       0x750c
-#define BRW_VF_STR_PSKIP	       0x7510
-#define BRW_VF_MAX_PRIM		       0x7514
-#define BRW_VF_RDATA		       0x7518
-
-#define BRW_VS_CTL		       0x7600
-#define BRW_VS_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
-#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0	   (0 << 8)
-#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1	   (1 << 8)
-#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT	   (2 << 8)
-#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER  (3 << 8)
-#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS		   (1 << 2)
-#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE	   (1 << 1)
-#define BRW_VS_CTL_SNAPSHOT_ENABLE		   (1 << 0)
-
-#define BRW_VS_STRG_VAL		       0x7604
-#define BRW_VS_RDATA		       0x7608
-
-#define BRW_SF_CTL		       0x7b00
-#define BRW_SF_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID	   (0 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID	   (2 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID	   (4 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT	   (6 << 8)
-#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER  (7 << 8)
-#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE  (1 << 4)
-#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE	   (1 << 3)
-#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS		   (1 << 2)
-#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE	   (1 << 1)
-#define BRW_SF_CTL_SNAPSHOT_ENABLE		   (1 << 0)
-
-#define BRW_SF_STRG_VAL		       0x7b04
-#define BRW_SF_RDATA		       0x7b18
-
-#define BRW_WIZ_CTL		       0x7c00
-#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
-#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT	   16
-#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER   (0 << 8)
-#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE     (1 << 8)
-#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE   (2 << 8)
-#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH	      (1 << 6)
-#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS    (1 << 5)
-#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE   (1 << 4)
-#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG	      (1 << 3)
-#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS	      (1 << 2)
-#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE	      (1 << 1)
-#define BRW_WIZ_CTL_SNAPSHOT_ENABLE		      (1 << 0)
-
-#define BRW_WIZ_STRG_VAL			      0x7c04
-#define BRW_WIZ_RDATA				      0x7c18
-
-#define BRW_TS_CTL		       0x7e00
-#define BRW_TS_CTL_SNAPSHOT_COMPLETE		   (1 << 31)
-#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR	   (0 << 8)
-#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR   (3 << 8)
-#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS	   (1 << 2)
-#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS  	   (1 << 1)
-#define BRW_TS_CTL_SNAPSHOT_ENABLE		   (1 << 0)
-
-#define BRW_TS_STRG_VAL		       0x7e04
-#define BRW_TS_RDATA		       0x7e08
-
-#define BRW_TD_CTL		       0x8000
-#define BRW_TD_CTL_MUX_SHIFT	       8
-#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH	   (1 << 7)
-#define BRW_TD_CTL_FORCE_EXTERNAL_HALT		   (1 << 6)
-#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE	   (1 << 5)
-#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE  (1 << 4)
-#define BRW_TD_CTL_BREAKPOINT_ENABLE		   (1 << 2)
-#define BRW_TD_CTL2		       0x8004
-#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28)
-#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE      (1 << 26)
-#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE	      (1 << 25)
-#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT	      16
-#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE	      (1 << 8)
-#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7)
-#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE	      (1 << 6)
-#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE	      (1 << 5)
-#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE     (1 << 4)
-#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE	      (1 << 3)
-#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE	      (1 << 0)
-#define BRW_TD_VF_VS_EMSK	       0x8008
-#define BRW_TD_GS_EMSK		       0x800c
-#define BRW_TD_CLIP_EMSK	       0x8010
-#define BRW_TD_SF_EMSK		       0x8014
-#define BRW_TD_WIZ_EMSK		       0x8018
-#define BRW_TD_0_6_EHTRG_VAL	       0x801c
-#define BRW_TD_0_7_EHTRG_VAL	       0x8020
-#define BRW_TD_0_6_EHTRG_MSK           0x8024
-#define BRW_TD_0_7_EHTRG_MSK	       0x8028
-#define BRW_TD_RDATA		       0x802c
-#define BRW_TD_TS_EMSK		       0x8030
-
-#define BRW_EU_CTL		       0x8800
-#define BRW_EU_CTL_SELECT_SHIFT	       16
-#define BRW_EU_CTL_DATA_MUX_SHIFT      8
-#define BRW_EU_ATT_0		       0x8810
-#define BRW_EU_ATT_1		       0x8814
-#define BRW_EU_ATT_DATA_0	       0x8820
-#define BRW_EU_ATT_DATA_1	       0x8824
-#define BRW_EU_ATT_CLR_0	       0x8830
-#define BRW_EU_ATT_CLR_1	       0x8834
-#define BRW_EU_RDATA		       0x8840
-
-/* End regs for broadwater */
-
 #define MAX_DISPLAY_PIPES	2
 
 typedef enum {
diff --git a/src/i810_ring.h b/src/legacy/i810/i810_ring.h
index e6e354fd..e6e354fd 100644
--- a/src/i810_ring.h
+++ b/src/legacy/i810/i810_ring.h
diff --git a/src/i810_video.c b/src/legacy/i810/i810_video.c
index 7e3db8c7..7e3db8c7 100644
--- a/src/i810_video.c
+++ b/src/legacy/i810/i810_video.c
diff --git a/src/i810_wmark.c b/src/legacy/i810/i810_wmark.c
index 71b2a825..71b2a825 100644
--- a/src/i810_wmark.c
+++ b/src/legacy/i810/i810_wmark.c
diff --git a/src/xvmc/I810XvMC.c b/src/legacy/i810/xvmc/I810XvMC.c
index 0754ff44..0754ff44 100644
--- a/src/xvmc/I810XvMC.c
+++ b/src/legacy/i810/xvmc/I810XvMC.c
diff --git a/src/xvmc/I810XvMC.h b/src/legacy/i810/xvmc/I810XvMC.h
index 9de32eba..9e311473 100644
--- a/src/xvmc/I810XvMC.h
+++ b/src/legacy/i810/xvmc/I810XvMC.h
@@ -42,7 +42,7 @@ THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #include <stdint.h>
 #include "xf86drm.h"
-#include "i810_common.h"
+#include "../i810_common.h"
 #include <X11/Xlibint.h>
 
 
diff --git a/src/legacy/i810/xvmc/Makefile.am b/src/legacy/i810/xvmc/Makefile.am
new file mode 100644
index 00000000..69add1e4
--- /dev/null
+++ b/src/legacy/i810/xvmc/Makefile.am
@@ -0,0 +1,11 @@
+if XVMC
+lib_LTLIBRARIES=libI810XvMC.la
+endif
+
+libI810XvMC_la_SOURCES = I810XvMC.c \
+			 I810XvMC.h
+
+libI810XvMC_la_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
+			-DTRUE=1 -DFALSE=0
+libI810XvMC_la_LDFLAGS = -version-number 1:0:0
+libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@
diff --git a/src/legacy/legacy.h b/src/legacy/legacy.h
new file mode 100644
index 00000000..7bdd1729
--- /dev/null
+++ b/src/legacy/legacy.h
@@ -0,0 +1,3 @@
+/* The old i810 (only) driver. */
+const OptionInfoRec *lg_i810_available_options(int chipid, int busid);
+void lg_i810_init(ScrnInfoPtr scrn);
diff --git a/src/xvmc/Makefile.am b/src/xvmc/Makefile.am
index 09cb12e6..6ee7dc46 100644
--- a/src/xvmc/Makefile.am
+++ b/src/xvmc/Makefile.am
@@ -1,17 +1,9 @@
 if XVMC
-lib_LTLIBRARIES=libI810XvMC.la libIntelXvMC.la
+lib_LTLIBRARIES=libIntelXvMC.la
 endif
 
 SUBDIRS = shader
 
-libI810XvMC_la_SOURCES = I810XvMC.c \
-			 I810XvMC.h
-
-libI810XvMC_la_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \
-	-I$(top_srcdir)/src -DTRUE=1 -DFALSE=0
-libI810XvMC_la_LDFLAGS = -version-number 1:0:0
-libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@
-
 libIntelXvMC_la_SOURCES = intel_xvmc.c \
         intel_xvmc.h                   \
         intel_xvmc_dump.c              \
diff --git a/src/xvmc/i965_xvmc.c b/src/xvmc/i965_xvmc.c
index 52b93e32..76cd289b 100644
--- a/src/xvmc/i965_xvmc.c
+++ b/src/xvmc/i965_xvmc.c
@@ -25,7 +25,8 @@
  *
  */
 #include "intel_xvmc.h"
-#include "i810_reg.h"
+#include "i830_reg.h"
+#include "i965_reg.h"
 #include "brw_defines.h"
 #include "brw_structs.h"
 #include "intel_batchbuffer.h"
diff --git a/src/xvmc/xvmc_vld.c b/src/xvmc/xvmc_vld.c
index 9ef840b3..0eb2e2f9 100644
--- a/src/xvmc/xvmc_vld.c
+++ b/src/xvmc/xvmc_vld.c
@@ -25,7 +25,8 @@
  */
 #include "intel_xvmc.h"
 #include "i830_hwmc.h"
-#include "i810_reg.h"
+#include "i830_reg.h"
+#include "i965_reg.h"
 #include "brw_defines.h"
 #include "brw_structs.h"