diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-09-06 15:58:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-09-06 15:58:56 -0400 |
| commit | 58d008883165ba35c83041fa9ed84937163d5f76 (patch) | |
| tree | 9c77d3d3484009b78a91d3e549db1a136113e130 | |
| parent | 8a2e0fa917996e72bfc0dbdf228fc0bfb433d279 (diff) | |
radeon: pad CS to 8 DW
Aligns the IB to 8 DWs. The aligns the IB to the
CP fetch size. r6xx also require at least 4 DW
alignment to avoid a hw bug.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | radeon/radeon_cs_gem.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c index b9631400..b87c6b13 100644 --- a/radeon/radeon_cs_gem.c +++ b/radeon/radeon_cs_gem.c @@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs) unsigned i; int r; + while (cs->cdw & 7) + radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000); + #if CS_BOF_DUMP cs_gem_dump_bof(cs); #endif |